KR100806798B1 - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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KR100806798B1
KR100806798B1 KR1020060088424A KR20060088424A KR100806798B1 KR 100806798 B1 KR100806798 B1 KR 100806798B1 KR 1020060088424 A KR1020060088424 A KR 1020060088424A KR 20060088424 A KR20060088424 A KR 20060088424A KR 100806798 B1 KR100806798 B1 KR 100806798B1
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forming
photoresist pattern
semiconductor substrate
gate electrode
entire surface
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KR1020060088424A
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Korean (ko)
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김대영
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for fabricating a semiconductor device is provided to improve a role-off characteristic by forming a rounded trench on a semiconductor substrate and then forming a gate electrode solve thereon. A first photoresist pattern is formed on the entire surface of a semiconductor substrate(200), and then a wet etching process is performed on the substrate using the first photoresist pattern as an etch mask to form a rounded trench on the substrate. The first photoresist pattern is removed through ashing and cleaning processes, and then a gate oxide layer and a polycrystal silicon layer are deposited on the entire surface of the substrate. A second photoresist pattern is formed on the polycrystal silicon layer, and then the substrate is subjected to an etch back process to form a gate electrode(210).

Description

반도체 소자 형성방법{Method for Forming Semiconductor Device}Method for Forming Semiconductor Device {Method for Forming Semiconductor Device}

도 1은 종래 기술에 따른 반도체 소자 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method of forming a semiconductor device according to the prior art.

도 2a 내지 도 2 c는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

200 : 반도체 기판 204a : 산화막 패턴200 semiconductor substrate 204a oxide film pattern

206a : 폴리 실리콘 막 패턴 210 : 게이트 전극206a: polysilicon film pattern 210: gate electrode

본 발명은 반도체 소자 형성방법에 관한 것으로, 특히, 반도체 소자 형성공정에서 반도체 기판에 라운딩된 트렌치를 형성하여 게이트 전극의 단면적을 넓혀 로울-오프(role-off) 특성 저하 및 핫 캐리어 현상(Hot carrier effect)을 방지할 수 있도록 하는 반도체 소자 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to form rounded trenches in a semiconductor substrate in a semiconductor device forming process to widen the cross-sectional area of a gate electrode, thereby degrading roll-off characteristics and hot carrier phenomenon. The present invention relates to a method for forming a semiconductor device that can prevent effects.

도 1은 종래 기술에 따른 반도체 소자 형성방법을 설명하기 위한 단면도이다. 1 is a cross-sectional view illustrating a method of forming a semiconductor device according to the prior art.

도 1에서 도시된 바와 같이, 반도체 기판 상(5)에 게이트 전극(20)을 형성하 며, 게이트 전극(20)은 게이트 산화막 패턴(10) 및 게이트 폴리막 패턴(15)을 갖는다.As shown in FIG. 1, the gate electrode 20 is formed on the semiconductor substrate 5, and the gate electrode 20 has a gate oxide layer pattern 10 and a gate poly layer pattern 15.

이 후, 게이트 전극(20)을 마스크로 이용하는 이온 주입 공정을 수행하여 반도체 기판(5)에 소스 영역(30a) 및 드레인 영역(30b)을 형성한 후 게이트 전극(20) 양측 벽에 스페이서(35)를 형성한다.Thereafter, an ion implantation process using the gate electrode 20 as a mask is performed to form a source region 30a and a drain region 30b in the semiconductor substrate 5, and then the spacers 35 are formed on both walls of the gate electrode 20. ).

그러나, 종래 기술에서 반도체 기판상에 형성되는 게이트 전극의 단면적이 작아 게이트 및 드레인에 가해지는 바이어스가 국부 영역에서 순간적으로 집중되어 민감하게 반응하여 레지스터의 로울-오프(role-off) 특성 저하 및 핫 캐리어 현상(Hot carrier effer)과 같은 문제가 발생한다.However, in the related art, the cross-sectional area of the gate electrode formed on the semiconductor substrate is small, and the bias applied to the gate and the drain is momentarily concentrated in the local region and reacts sensitively, thereby degrading the roll-off characteristic of the resistor and hot. Problems such as hot carrier effer occur.

본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 반도체 소자 형성공정에서 반도체 기판에 라운딩된 트렌치를 형성하여 게이트 전극의 단면적을 넓혀 로울-오프(role-off) 특성 저하 및 핫 캐리어 현상(Hot carrier effer)을 방지할 수 있도록 하는 반도체 소자 형성방법을 제공하는 데 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above. In the semiconductor device forming process, a rounded trench is formed on the semiconductor substrate to increase the cross-sectional area of the gate electrode, thereby reducing roll-off characteristics. An object of the present invention is to provide a method of forming a semiconductor device capable of preventing a hot carrier phenomenon.

상기한 목적을 달성하기 위한 본 발명의 일실시 예에 따른 반도체 소자 형성방법의 일 특징은 반도체 기판 전면에 제1 포토 레지스트 패턴 형성하고, 상기 제1 포토 레지스트 패턴을 식각마스크로 습식식각 공정을 수행하여 상기 반도체 기판에 라운딩된 트렌치를 형성하는 단계, 상기 라운딩된 트렌치를 형성한 후, 에싱 및 세정공정을 통해 상기 제1 포토 레지스트패턴을 제거하고, 상기 라운딩된 트렌치를 포함하는 상기 반도체 기판 전면 상에 게이트 산화막 및 폴리 실리콘 막을 순차적으로 적층하는 단계 및 상기 적층된 폴리 실리콘 막 전면 상에 제2 포토 레지스트 패턴을 형성하고, 상기 제2 포토 레지스트 패턴을 식각마스크로 에치백(etch-back) 공정을 수행하여 게이트 전극을 형성하는 단계를 포함하여 이루어지는 것이다.
보다 바람직하게, 상기 제1 포토 레지스트 패턴을 제거한 후, 상기 라운딩된 트렌치를 포함하는 반도체 기판 전면을 DHF 및 O3 CLN(Cleaning)을 통해 세척하는 단계를 더 포함한다. According to an aspect of the present invention, there is provided a method of forming a semiconductor device, and a first photoresist pattern is formed on the entire surface of the semiconductor substrate, and the wet etching process is performed using the first photoresist pattern as an etching mask. Forming a rounded trench in the semiconductor substrate, forming the rounded trench, and then removing the first photoresist pattern through an ashing and cleaning process, and forming a rounded trench on the entire surface of the semiconductor substrate including the rounded trench. Sequentially depositing a gate oxide film and a polysilicon film, forming a second photoresist pattern on the entire surface of the stacked polysilicon film, and etching the second photoresist pattern with an etch mask. And forming a gate electrode by performing the same.
More preferably, after removing the first photoresist pattern, the method further includes washing the entire surface of the semiconductor substrate including the rounded trench through DHF and O 3 CLN (Cleaning).

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이하에서 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2 c는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도들이다.2A through 2C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

먼저, 도 2a를 살펴보면, 반도체 기판(20) 전면 상에 제1 포토 레지스트 패턴(202)을 형성하고, 형성된 제1 포토 레지스트 패턴(202)을 마스크로 이용하는 습식식각 공정습식식각 공정식각(Wet etch) 공정을 소정의 시간 동안 수행하여 반도체 기판(200)에 소정의 깊이를 갖는 라운딩된 트렌치를 형성한 후 도 2b에서 도시된 바와 같이, 에싱 및 세정공정을 수행하여 제1 포토 레지스트 패턴(202)을 제거한다. First, referring to FIG. 2A, a wet etch process wet etch process is performed by forming a first photoresist pattern 202 on the entire surface of a semiconductor substrate 20 and using the formed first photoresist pattern 202 as a mask. ) To form a rounded trench having a predetermined depth in the semiconductor substrate 200 by a predetermined time, and then, as illustrated in FIG. 2B, an ashing and a cleaning process are performed to perform the first photoresist pattern 202. Remove it.

그런 다음, 라운딩된 트렌치를 포함하는 반도체 기판(200) 전면(이하 반도체 기판 이라 칭함)을 DHF(Dilute hydro fluoride) 및 O3 CLN(Cleaning)을 수행하여 세척한 후 소정의 두께로 산화막(204) 및 폴리 실리콘 막(206)을 순차적으로 증착한다.Then, the entire surface of the semiconductor substrate 200 including the rounded trenches (hereinafter referred to as a semiconductor substrate) is cleaned by performing dilute hydro fluoride (DHF) and O 3 CLN (Cleaning), and then the oxide film 204 to a predetermined thickness. And the polysilicon film 206 is sequentially deposited.

이 후, 폴리 실리콘 막(206) 전면 상부에 제2 포토 레지스트 패턴(208)을 형성하고, 제2 포토 레지스트 패턴(208)을 마스크로 이용하는 에치백 공정 예컨대, 에치 백 공정을 수행하여 폴리 실리콘 막(206) 및 산화 막(204)을 선택적으로 식각하여 도 2c에서 도시된 바와 같이, 게이트 전극(210)을 형성한 후 에싱 및 세정공정을 수행하여 제2 포토 레지스트 패턴(208)을 제거한다.Thereafter, a second photoresist pattern 208 is formed on the entire upper surface of the polysilicon film 206, and an etch back process using the second photoresist pattern 208 as a mask is performed, for example, an polysilicon film. 206 and the oxide film 204 are selectively etched to form the gate electrode 210, and then the second photoresist pattern 208 is removed by performing an ashing and cleaning process as shown in FIG. 2C.

여기서, 라운딩된 트렌치를 형성한 후 게이트 전극(210)을 형성함으로써, 게이트 전극(210)의 단위 면적당 채널 면적이 증가하여, 캐리어 이동성 특성을 향상시킬 수 있다.Here, by forming the rounded trench and then forming the gate electrode 210, the channel area per unit area of the gate electrode 210 is increased, thereby improving carrier mobility characteristics.

또한, 소스 영역과 드레 영역 간의 거리가 증가하여 쇼트 채널에 의한 부작용을 방지할 수 있다.In addition, the distance between the source region and the drain region is increased to prevent side effects caused by the short channel.

이후, 공지의 후공정을 진행하는데, 도면에는 도시되지 않았지만, 게이트 전극(210)을 마스크로 이용하는 이온주입(Ion implantation)을 수행하여 LDD(Lightly Doping Drain) 접합 층을 형성시킨 후 게이트 전극을 포함하는 반도체 기판(200) 전면 상에 절연물질을 소정의 두께로 도포한 후 식각공정 예컨대, 에치 백(Etch Back)을 수행하여 게이트 전극(210) 측벽에 스페이서(Side Wall Spacer)를 형성한다.Subsequently, a known post-process is performed, although not shown in the drawing, a gate electrode is formed by forming an LDD (Lightly Doping Drain) bonding layer by performing ion implantation using the gate electrode 210 as a mask. After the insulating material is coated on the entire surface of the semiconductor substrate 200 to a predetermined thickness, an etching process, for example, an etch back is performed to form a spacer on the sidewall of the gate electrode 210.

게이트 전극(210) 측벽에 스페이서를 형성하고, 고농도의 불순물(n+/p+)을 주입하여 소스 영역 및 드레인 영역을 형성한 후, 반도체 기판(200)의 활성영역 및 게이트 전극(210)의 상면에 실리사이드층을 형성한다.A spacer is formed on the sidewall of the gate electrode 210 and a high concentration of impurities (n + / p +) are implanted to form a source region and a drain region, and then, on the active region of the semiconductor substrate 200 and the top surface of the gate electrode 210. The silicide layer is formed.

이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것이 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains can make various modifications and Modifications are possible.

그러므로, 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자 형성방법에서 반도체 기판에 라운딩된 트렌치를 형성한 후 게이트 전극을 형성함으로써, 게이트 전극의 단면적이 넓어 로울-오프(role-off) 특성 향상 및 핫 캐리어 현상을 방지하여 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, in the method of forming a semiconductor device according to the present invention, by forming a rounded trench on a semiconductor substrate and then forming a gate electrode, the cross-sectional area of the gate electrode is increased, thereby improving roll-off characteristics and hot carriers. There is an effect that can prevent the phenomenon to improve the characteristics and reliability of the semiconductor device.

Claims (4)

반도체 기판 전면에 제1 포토 레지스트 패턴 형성하고, 상기 제1 포토 레지스트 패턴을 식각마스크로 습식식각 공정을 수행하여 상기 반도체 기판에 라운딩된 트렌치를 형성하는 단계;Forming a rounded trench on the semiconductor substrate by forming a first photoresist pattern on the entire surface of the semiconductor substrate and performing a wet etching process using the first photoresist pattern as an etching mask; 상기 라운딩된 트렌치를 형성한 후, 에싱 및 세정공정을 통해 상기 제1 포토 레지스트패턴을 제거하고, 상기 라운딩된 트렌치를 포함하는 상기 반도체 기판 전면 상에 게이트 산화막 및 폴리 실리콘 막을 순차적으로 적층하는 단계; 및After forming the rounded trench, removing the first photoresist pattern through an ashing and cleaning process, and sequentially depositing a gate oxide film and a polysilicon film on an entire surface of the semiconductor substrate including the rounded trench; And 상기 적층된 폴리 실리콘 막 전면 상에 제2 포토 레지스트 패턴을 형성하고, 상기 제2 포토 레지스트 패턴을 식각마스크로 에치백(etch-back) 공정을 수행하여 게이트 전극을 형성하는 단계를 포함하여 이루어지는 반도체 소자 형성방법.And forming a gate electrode by forming a second photoresist pattern on the entire surface of the stacked polysilicon layer and performing an etch-back process using the second photoresist pattern as an etch mask. Device Formation Method. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 제1 포토 레지스트 패턴을 제거한 후, 상기 라운딩된 트렌치를 포함하는 반도체 기판 전면을 DHF 및 O3 CLN(Cleaning)을 통해 세척하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 형성방법.And removing the first photoresist pattern, and then cleaning the entire surface of the semiconductor substrate including the rounded trench through DHF and O 3 CLN (Cleaning). 삭제delete
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070035899A (en) * 2005-09-28 2007-04-02 주식회사 하이닉스반도체 Method for fabricating the same of semiconductor device with recess gate of flask shape

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