CN106024712B - A kind of production method of autoregistration GaAs PMOS device - Google Patents
A kind of production method of autoregistration GaAs PMOS device Download PDFInfo
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- CN106024712B CN106024712B CN201610613870.5A CN201610613870A CN106024712B CN 106024712 B CN106024712 B CN 106024712B CN 201610613870 A CN201610613870 A CN 201610613870A CN 106024712 B CN106024712 B CN 106024712B
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- autoregistration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Abstract
The present invention provides a kind of production methods of autoregistration GaAs PMOS device, and steps are as follows for the production method：(1) SiO is grown on gallium arsenide channel layer2300 nanometers of medium；(2) SiO is etched2Dielectric layer forms 85 degree of steps；(3) alumina medium is grown in gallium arsenide surface；(4) in SiO2Side wall forms titanium grid metal；(5) tungsten grid metal is formed；(6) remove the alumina medium and SiO other than grid metal overlay area2Medium；(9) autoregistration ion implanting forms source and drain areas；(10) source and drain metal electrodes are deposited in source and drain areas.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology fields, and in particular to a kind of autoregistration GaAs PMOS device
Production method is applied to high-performance Group III-V semiconductor CMOS technology.
Background technology
For III-V compound semiconductor materials is with respect to silicon materials, there is high carrier mobility, big energy gap etc.
Advantage, and have excellent characteristics in calorifics, optics and electromagnetism etc..Lack the PMOS devices to match with NMOS device
Part is always the major obstacle of application one of of the Group III-V semiconductor in extensive CMOS integrated circuits.Current research is reported
Show：Source and drain dead resistance is a key factor for influencing III-V PMOS device performance boosts greatly.Therefore, it is necessary to a kind of new
Approach self aligned PMOS device is realized on Group III-V semiconductor device architecture, reduce the parasitic electricity of source and drain of PMOS device
Resistance improves device performance, to meet the requirement of high-performance Group III-V semiconductor CMOS technology.
Invention content
(1) technical problems to be solved
The main object of the present invention is to provide a kind of autoregistration GaAs PMOS device production method, to realize with GaAs
For channel material, the autoregistration PMOS device of double grid metal electrode, the iii-v for channel material with high electron mobility is realized
Semiconductor N MOS device matches, and meets the requirement of high-performance Group III-V semiconductor CMOS technology.
(2) technical solution
In order to achieve the above objectives, the present invention provides a kind of autoregistration GaAs PMOS device production methods.Its making side
Method step is successively：
(1) SiO is grown on the gallium arsenide channel layer of a n-type doping2300 nanometers of medium；
(2) method for using ICP etchings, in SiO285 degree of steps are formed on dielectric layer；
(3) surface clean and passivation are carried out to the sample, grows 3 nanometers of alumina medium on surface；
(4) 60 nanometers of titanium is deposited in sample strip using the method for sputtering；
(5) method for using ICP etchings etches titanium, and the grid metal electrode of 30 nano thickness is formed in mesa sidewall；
(6) method sputtered 60 nanometers of depositing tungsten metal in sample strip are used；
(7) method for using ICP etchings etches tungsten metal, and the grid metal electrode of 30 nano thickness is formed in mesa sidewall；
(8) use photoresist mask, the method for plasma etching is etched away alumina medium other than grid metal and
SiO2Medium；
(9) autoregistration ion implanting is carried out to the sample, injection ion is Mg, and carries out injection activation, forms source-drain area
Domain；
(10) source and drain metal electrodes of Pt/Ti/Au are deposited in source and drain areas.
In the above scheme, the GaAs channel layers of the n-type doping, impurity are silicon, doping concentration is 3 ×
1017cm-3；
In the above scheme, the SiO2The etching of dielectric layer is performed etching using ICP etching systems；
In the above scheme, before growth aoxidizes alum gate medium, surface clean and passivation are carried out to GaAs channel surfaces, with
Realize the interfaces MOS of good no fermi level pinning；
In the above scheme, the grid metal Ti is formed by way of sputtering, to ensure having good side wall
Spreadability and side wall Ti metal thickness；
In the above scheme, the grid metal W is in formation by way of sputtering, to ensure its covering in side wall
Lid and side wall W metal thickness；
In the above scheme, the aluminium oxide and SiO2Removal all use fluorine-based plasma etching method,
Middle SiO2Removal use low damage etch；
In the above scheme, the grid metal distribution of electrodes be titanium electrode close to source, tungsten metal is close to drain terminal.
(3) advantageous effect
It can be seen from the above technical proposal that the invention has the advantages that：
A kind of production method of GaAs channel PMOS devices provided by the invention is passivated using GaP Interface Control layer technologies
The dangling bonds of interface realize interface state density, and reduce the scattering of carrier in raceway groove, while GaP boundary layers are gesture again
Barrier layer improves the two-dimensional electron gas in channel layer, realizes high mobility and high electron concentration double action；Using beryllium from
Sub- injection technology makes the technological temperature of device entirety be less than 500 DEG C, and processing compatibility is good；Due to the electronics of GaAs material
Mobility and hole mobility are relatively balanced, so this GaAs channel PMOS devices are invented, to meet high-performance III-V
The requirement of race's semiconductor CMOS technology.
Description of the drawings
Fig. 1 is GaAs channel PMOSs process flow chart provided by the invention；
Fig. 2-11 is that the GaAs channel PMOS devices that the present invention improves make implementation illustration；
Wherein 101 be gallium arsenide channel layer, and 102 be SiO2 mask layers, and 103 be alumina medium layer, and 104 be titanium grid metal
Layer, 105 be tungsten barrier metal layer, and 106 be source and drain ion implanted region, and 107 be source and drain metal electrodes.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
As shown in figs. 2-11, Fig. 2-11 is to present embodiments provide an a kind of production method for GaAs PMOS device.Its
Making step is successively：
(1) as shown in Fig. 2, forming the SiO of 300 nano thickness on the gallium arsenide channel (101) of n-type doping2Medium, it is raw
Long method is PECVD；
(2) as shown in figure 3, using the method for ICP etchings in SiO2A step for forming 85 degree is formed on medium；
(3) as shown in figure 4, growing 3 nanometers of alumina medium in sample surfaces, growing method is atomic layer deposition；
(4) as shown in figure 5, depositing 60 nanometers of titanium in sample strip using the method for sputtering in sample surfaces；
(5) as shown in fig. 6, etching titanium using the method for ICP etchings, the grid of 30 nano thickness are formed in mesa sidewall
Metal electrode；
(6) as shown in fig. 7, in sample strip, using 60 nanometers of the method depositing tungsten metal of sputtering；
(7) as shown in figure 8, etching tungsten metal using the method for ICP etchings, the grid of 30 nano thickness are formed in mesa sidewall
Metal electrode；
(8) as shown in figure 9, the method for using plasma etching be etched away alumina medium other than grid metal and
SiO2Medium；
(9) as shown in Figure 10, using grid metal and photoresist as mask, autoregistration ion implanting, injection are carried out to the sample
Ion is magnesium, and carries out injection activation, forms source and drain areas；
(10) as shown in figure 11, in the source and drain metal electrodes of source and drain areas deposition platinum/titanium/gold (5/10/200 nanometer).
In the above-described embodiments, the removal of SiO2 is etched using ICP system, etching gas CHF3, and throughput is
30sccm, radio-frequency power are 15 watts, and ICP power is 150 watts, and chamber pressure is 0.8 pa.
In the above-described embodiments, the removal of aluminium oxide is etched using ICP system, etching gas CHF3, and throughput is
30sccm, radio-frequency power are 40 watts, and ICP power is 180 watts, and chamber pressure is 0.8 pa.
In the above-described embodiments, the etching of titanium and tungsten metal all uses ICP system, etching gas SF6, throughput
For 20sccm, radio-frequency power is 20 watts, and ICP power is 120 watts, and chamber pressure is 0.3 pa.
In the above-described embodiments, the dosage of magnesium ion injection is 1 × 1013, energy 30KeV.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (6)
1. a kind of production method of autoregistration GaAs PMOS device, production method step are successively：
(1) SiO is grown on N-type gallium arsenide channel layer2300 nanometers of medium；
(2) SiO is etched2Dielectric layer forms 85 degree of steps；
(3) alumina medium is grown in gallium arsenide surface, the alumina medium is as gate medium；
(4) 60 nanometers of titanium is deposited；
(5) it uses ICP to etch titanium, titanium grid metal is formed in mesa sidewall；
(6) 60 nanometers of depositing tungsten metal；
(7) it uses ICP to etch tungsten metal, tungsten grid metal is formed in mesa sidewall；
(8) remove the alumina medium and SiO other than grid metal overlay area2Medium；
(9) autoregistration ion implanting forms source and drain areas；
(10) source and drain metal electrodes are deposited in source and drain areas.
2. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the oxygen
The thickness for changing aluminium medium is 3 nanometers.
3. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the titanium
The grid length of MOS device has been codetermined with the width and gate dielectric layer sidewall thickness of two grid metals of tungsten.
4. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the titanium
All it is to be deposited using the method for magnetron sputtering, and molding is etched using the method for ICP etchings with tungsten grid metal.
5. a kind of production method of autoregistration GaAs PMOS device described in claim 1, it is characterised in that the titanium
The source and drain spacing of GaAs PMOS device is determined with the width of tungsten metal.
6. a kind of production method of autoregistration GaAs PMOS device described in claim 1, it is characterised in that the titanium
End is located at close to the source side of PMOS device.
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| CN102569399A (en) * | 2011-11-29 | 2012-07-11 | 中国科学院微电子研究所 | Source-drain self-aligned MOS (Metal Oxide Semiconductor) device and fabricating method thereof |
| CN105655256A (en) * | 2015-12-30 | 2016-06-08 | 东莞市青麦田数码科技有限公司 | Production method of self-alignment MOSFET device |
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Application publication date: 20161012 Assignee: Dongguan chain core semiconductor technology Co.,Ltd. Assignor: DONGGUAN SOUTH CHINA DESIGN INNOVATION INSTITUTE Contract record no.: X2022980013285 Denomination of invention: A kind of manufacturing method of self-aligned gallium arsenide PMOS device Granted publication date: 20180921 License type: Common License Record date: 20220824 |
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