CN109690786A - Hetero-junctions tunnel field effect transistor and preparation method thereof - Google Patents
Hetero-junctions tunnel field effect transistor and preparation method thereof Download PDFInfo
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- 238000002353 field-effect transistor method Methods 0.000 title abstract description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The embodiment of the present application provides a kind of hetero-junctions tunnel field effect transistor and preparation method thereof, it include: the upper surface that the first insulating layer is covered on substrate, first heterojunction material layer is covered on the upper surface of the first insulating layer for one end of source electrode to be arranged, one end of the first heterojunction material layer is arranged in source electrode, second insulating layer is provided with around the first heterojunction material layer other end, separation layer is arranged on hetero junction layer, and separation layer is covered on the inside of source electrode；Second heterojunction material layer is covered in the other end, second insulating layer and the second insulating layer of the first heterojunction material layer, forms hetero-junctions with the first heterojunction material layer, the other end opposite with source electrode on the second hetero junction layer is arranged in drain electrode；Gate dielectric layer is covered on the position on the second heterojunction material layer between source electrode and drain electrode, and grid is arranged on gate dielectric layer.It is isolated by the way that second insulating layer is arranged, is substantially reduced Leakage Current caused by marginality, and form hetero-junctions using two-dimensional material, avoids boundary defect caused by mismatching because of lattice.
Description
The invention relates to semiconductor technologies more particularly to a kind of hetero-junctions tunnel field effect transistor (Tunnel Field-Effect Transistors, referred to as: TFET) and preparation method thereof.
Integrated circuit constantly reduces according to Moore's Law, but after the size of transistor enters 14nm, 10nm node, further to reduce transistor size, leakage current caused by short-channel effect is continuously increased, and the power consumption of integrated circuit is caused to become increasingly severe problem.With conventional metals-oxide semiconductor field effect transistor, (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as: MOSFET) working mechanism is different, tunneling field-effect transistor TFET uses inter-band tunneling mechanism, its sub-threshold slope (Subthreshold Slope, the room temperature that can referred to as: SS) be lower than 60mV/dec limits, so as to which operating voltage is effectively reduced, and dynamic power consumption and operating voltage is square directly proportional, therefore power consumption can be significantly reduced using the integrated circuit of TFET device preparation.
Common TFET framework is mainly using silicon as the homojunction TFET of channel material and using III-V material as the hetero-junctions TFET of channel.Due to the big band gap of silicon materials and indirect band-gap semiconductor characteristic, inter-band tunneling probability is very low, causes silicon substrate TFET on-state current too low, is not able to satisfy application requirement.III-V material has the characteristic that band gap is smaller, effective mass is small, enables the hetero-junctions TFET based on III-V material to obtain very big on-state current, but the presence of the interfacial state of higher density causes it to be difficult to obtain the SS less than 60mV/dec.Two-dimensional material has that atom level is thin, surface is without excellent characteristics such as dangling bonds, and based on the hetero-junctions of two-dimensional material without boundary defect caused by lattice mismatch.Therefore the hetero-junctions TFET based on two-dimensional material has more advantage compared to traditional TFET.
However, two-dimensional material surface is without dangling bonds, but the boundary of material, there are still dangling bonds, which will increase the leakage current of two-dimensional material hetero-junctions TFET.
Summary of the invention
The embodiment of the present application provides a kind of hetero-junctions tunnel field effect transistor and preparation method thereof, for solving in aforementioned schemes two-dimensional material surface without dangling bonds, but the problem of boundary of material is there are still dangling bonds, which will increase the leakage current of two-dimensional material hetero-junctions TFET.
The application first aspect provides a kind of hetero-junctions tunnel field effect transistor, comprising:
Substrate；
First insulating layer；First insulating layer is covered on the upper surface of the substrate；
First heterojunction material layer, the first heterojunction material layer are covered on the upper surface of first insulating layer for one end of source electrode to be arranged；
One end of the first heterojunction material layer, the first heterojunction material layer other end is arranged in source electrode, the source electrode
Surrounding is provided with second insulating layer；
Separation layer, the separation layer are arranged on the hetero junction layer, and the separation layer is covered on the inside of the source electrode；
Second heterojunction material layer, the second heterojunction material layer are covered in the other end, second insulating layer and the second insulating layer of the first heterojunction material layer, form hetero-junctions with the first heterojunction material layer；
The other end opposite with the source electrode on second hetero junction layer is arranged in drain electrode, the drain electrode；
Gate dielectric layer, the gate dielectric layer are covered on the position on the second heterojunction material layer between source electrode and drain electrode；
Grid, the grid are arranged on the gate dielectric layer.
In the present solution, being isolated by the way that second insulating layer is arranged, it is substantially reduced Leakage Current caused by marginality.
Optionally, the material of the first heterojunction material layer is two stannic selenide SnSe2, the material of the second heterojunction material layer is two tungsten selenide WSe2；Alternatively,
The material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is selenizing molybdenum MoSe2；Alternatively,
The material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is telluride molybdenum MoTe2。
Optionally, first insulating layer and the second insulating layer are oxide insulating layer.
Optionally, the material of first insulating layer is silicon oxide sio2；The material of the second insulating layer is yttrium oxide Y2O3Or aluminium oxide Al2O3。
In above scheme, hetero-junctions is formed using two-dimensional material, avoids boundary defect caused by mismatching because of lattice.
The application second aspect provides a kind of hetero-junctions tunnel field effect transistor, comprising:
Substrate；
The one end on surface over the substrate is arranged in source electrode, the source electrode；
First insulating layer；The first insulating layer insertion setting is over the substrate for being arranged the position of drain electrode；
Heterojunction material layer, the first heterojunction material layer are covered on the upper surface of the part substrate of part first insulating layer and the not set source electrode, are provided with second insulating layer around the other end of heterojunction material layer first insulating layer；
Drain electrode, the drain electrode are arranged on the first insulating layer, and the outer side contacts of the drain electrode and the heterojunction material layer；
Gate dielectric layer, position of the gate dielectric layer between source electrode and drain electrode, and the gate dielectric layer are covered on the substrate, the second insulating layer and the heterojunction material layer；
Grid, the grid are arranged on the gate dielectric layer.
In the present solution, being isolated by second insulating layer, it is substantially reduced Leakage Current caused by marginality.
Optionally, the heterojunction material layer is two tungsten selenide WSe2Layer.
Optionally, first insulating layer and the second insulating layer are oxide insulating layer.
Optionally, the material of the second insulating layer is yttrium oxide Y2O3。
In above-mentioned several specific implementations, hetero-junctions is formed using two-dimensional material, avoid boundary defect caused by mismatching because of lattice, line tunneling structure is used simultaneously, increases tunnelling area, using the stagger-gap type hetero-junctions of low potential barrier, increase tunnelling probability, tunnelling current is improved, using hetero-junctions, tunneling barrier width is narrow.
The application third aspect provides a kind of preparation method of hetero-junctions tunnel field effect transistor, comprising:
The substrate for being covered with the first insulating layer is provided, and the source region contacted with the first heterojunction material is defined by optical exposure over the substrate；
Source electrode is made by evaporation metal on the active region；
The fringe region of the first heterojunction material layer is defined by exposure development, and is aoxidized in the fringe region evaporation metal, and second insulating layer is formed；
Separation layer form is defined by optical exposure, oxide is deposited on the inside of the source electrode and forms separation layer；
Second heterojunction material is transferred to the first heterojunction material layer, defines form and perform etching to form the second heterojunction material layer by optical exposure, forms hetero-junctions with the first heterojunction material layer；
On the second heterojunction material layer, by lithographic definition drain region, and evaporation metal forms drain electrode；
On the second heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
In one kind in the specific implementation, when the first heterojunction material layer is SnSe2Layer, second insulating layer are yttrium oxide Y2O3, then it is described that the fringe region of the first heterojunction material layer is defined by exposure development, and aoxidized in the fringe region evaporation metal, form second insulating layer, comprising:
SnSe is defined by exposure development2The fringe region of layer, in the SnSe2The fringe region evaporation metal yttrium of layer, and oxidation processes are carried out, form Y2O3Insulating layer.
In one kind in the specific implementation, the second heterojunction material layer is WSe2Layer, it is described that second heterojunction material is transferred to the first heterojunction material layer, it defines form and performs etching to form the second heterojunction material layer by optical exposure, form hetero-junctions with the first heterojunction material layer, comprising:
By WSe2It is transferred to SnSe2On layer, WSe is defined by optical exposure2Form, the WSe of dry etching removal exposure region is carried out using RIE or ICP2, photoresist is removed, WSe is formed2Layer, with the SnSe2Layer forms hetero-junctions.
In a kind of specific implementation, on the second heterojunction material layer, by lithographic definition drain region, and evaporation metal forms drain electrode, comprising:
In WSe2Lithographic definition drain region, the evaporation metal Cr/Pt/Au or MoO on the drain region are used on layer3/ Pt, formation and WSe2The drain electrode that layer is connected.
In one kind in the specific implementation, on the second heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer, comprising:
In WSe2Lithographic definition area of grid is used on layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
The application fourth aspect provides a kind of preparation method of hetero-junctions tunnel field effect transistor, comprising:
The substrate of n-type doping is provided；
A groove is etched over the substrate by reactive ion etching RIE, oxide-isolation layer is generated in the groove, forms the first insulating layer；
The fringe region of heterojunction material layer Yu the substrate contact is defined by exposure development, and is aoxidized in the fringe region evaporation metal, and second insulating layer is formed；
Heterojunction material is transferred on the substrate, and performs etching and to form heterojunction material layer；
Over the substrate by lithographic definition source region, and source electrode is made by evaporation metal on the source region；
It is raw using lithographic definition drain region in first insulating layer, and formed and drained in the drain region evaporation metal；
On the substrate, the second insulating layer and the heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
In one kind in the specific implementation, described etch a groove by reactive ion etching RIE over the substrate, oxide-isolation layer is generated in the groove, forms the first insulating layer, comprising:
Lithographic definition oxide-isolation layer is used over the substrate, reactive ion etching RIE is recycled to etch a groove over the substrate, and oxide-isolation layer is generated in the groove using vapor deposition or ALD, forms first insulating layer.
In one kind in the specific implementation, the heterojunction material layer is two tungsten selenide WSe2Layer, the material of the second insulating layer are yttrium oxide Y2O3, then the fringe region of heterojunction material layer Yu the substrate contact is defined by exposure development, and aoxidized in the fringe region evaporation metal, form second insulating layer, comprising:
The fringe region of WSe2 and substrate contact is defined using exposure development over the substrate, evaporation metal yttrium is simultaneously aoxidized, and Y is formed2O3Layer.
In one kind in the specific implementation, described be transferred to heterojunction material on the substrate, and performs etching and to form heterojunction material layer, comprising:
The WSe2 of CVD growth is transferred on the substrate, and removes the WSe2 of exposure using dry etching, forms WSe2 layers.
It is in one kind in the specific implementation, described over the substrate by lithographic definition source region, and source electrode is made by evaporation metal on the source region, comprising:
One section in the substrate uses lithographic definition source region, forms source electrode in the source region evaporation metal Ti/Pt/Au.
It is in one kind in the specific implementation, described raw using lithographic definition drain region in first insulating layer, and formed and drained in the drain region evaporation metal, comprising:
Lithographic definition drain region, the evaporation metal Cr/Pt/Au or MoO on the drain region are used on the first insulating layer3/ Pt, formation and WSe2The drain electrode that layer is connected.
It is in one kind in the specific implementation, described on the substrate, the second insulating layer and the heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer, comprising:
In WSe2Layer and Y2O3Lithographic definition area of grid is used on layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
Hetero-junctions tunnel field effect transistor provided by the present application and preparation method, the tunnel field-effect tube includes: the upper surface that the first insulating layer is covered on substrate, first heterojunction material layer is covered on the upper surface of the first insulating layer for one end of source electrode to be arranged, one end of the first heterojunction material layer is arranged in source electrode, second insulating layer is provided with around the first heterojunction material layer other end, separation layer is arranged on hetero junction layer, and separation layer is covered on the inside of source electrode；Second heterojunction material layer is covered in the other end, second insulating layer and the second insulating layer of the first heterojunction material layer, forms hetero-junctions with the first heterojunction material layer, the other end opposite with source electrode on the second hetero junction layer is arranged in drain electrode；Gate dielectric layer is covered on the position on the second heterojunction material layer between source electrode and drain electrode, and grid is arranged on gate dielectric layer.It is isolated by the way that second insulating layer is arranged, is substantially reduced Leakage Current caused by marginality, and form hetero-junctions using two-dimensional material, avoids boundary defect caused by mismatching because of lattice.
Fig. 1 is the structural schematic diagram of the application hetero-junctions tunnel field effect transistor embodiment one；
Fig. 2 is the structural schematic diagram of the application hetero-junctions tunnel field effect transistor embodiment two；
Fig. 3 a is the structural schematic diagram of one example of the application hetero-junctions tunnel field effect transistor；
Fig. 3 b is the structural schematic diagram of another example of the application hetero-junctions tunnel field effect transistor；
Fig. 4 is the flow chart of the preparation method embodiment one of the application hetero-junctions tunnel field effect transistor；
Fig. 5 a-5g is the procedure structure schematic diagram of one example of preparation method of the application hetero-junctions tunnel field effect transistor；
Fig. 6 is the flow chart of the preparation method embodiment two of the application hetero-junctions tunnel field effect transistor；
Fig. 7 a-7i is the procedure structure schematic diagram of another example of preparation method of the application hetero-junctions tunnel field effect transistor.
In order to overcome the two-dimensional material surface in common TFET without dangling bonds, but there are still dangling bonds on the boundary of material, the dangling bonds will increase the problem of leakage current of two-dimensional material hetero-junctions TFET, the application proposes a kind of by the way that two-dimensional material is transferred to block materials formation hetero-junctions or stacks to form hetero-junctions by two kinds of two-dimensional materials, oxide layer is grown in edge of materials at hetero-junctions interface (i.e. the overlapping regions of two materials), edge is kept apart, increase the tunneling distance of edge carrier, to reduce the scheme of Tunneling leakage current.The structure and preparation method of hetero-junctions tunnel field effect transistor provided by the present application are described in detail below.
The heterojunction regions of hetero-junctions TFET in this programme are made of 2D material and 2D material or 2D material and 3D material.For 2D-3D type hetero-junctions TFET, heterojunction material group becomes InAs-WSe2, SnSe2-Si, MoTe2-InAs etc..For 2D-2D type hetero-junctions TFET, heterojunction material group becomes WSe2-SnSe2, SnSe2-MoSe2, SnSe2-MoTe2 etc..
Fig. 1 is the structural schematic diagram of the application hetero-junctions tunnel field effect transistor embodiment one, as shown in Figure 1, a kind of structure of hetero-junctions tunnel field effect transistor provided by the present application includes:
Substrate, the first insulating layer, the first heterojunction material layer, source electrode, separation layer, the second heterojunction material layer, drain electrode, gate dielectric layer and grid；
Wherein, first insulating layer is covered on the upper surface of the substrate, the first heterojunction material layer is covered on the upper surface of first insulating layer for one end of source electrode to be arranged, one end of the first heterojunction material layer is arranged in the source electrode, is provided with second insulating layer around the first heterojunction material layer other end；The separation layer is arranged on the hetero junction layer, and the separation layer is covered on the inside of the source electrode；The second heterojunction material layer is covered in the other end, second insulating layer and the second insulating layer of the first heterojunction material layer, hetero-junctions is formed with the first heterojunction material layer, the other end opposite with the source electrode on second hetero junction layer is arranged in the drain electrode；Gate dielectric layer, the gate dielectric layer are covered on the position on the second heterojunction material layer between source electrode and drain electrode；Grid, the grid are arranged on the gate dielectric layer.
Fig. 3 a is the structural schematic diagram of one example of the application hetero-junctions tunnel field effect transistor, as shown in Figure 3a, in the structure in the specific implementation, oxide material, which can be used, in insulating layer realizes that i.e. the first insulating layer and second insulating layer all can be oxide insulating layers.
First heterojunction material layer and the second heterojunction material layer constitute the hetero-junctions of the TFET, include at least following several implementations:
The material of the first heterojunction material layer is two stannic selenide SnSe2, the material of the second heterojunction material layer is two
Tungsten selenide WSe2(as shown in Figure 3a)；Alternatively, the material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is selenizing molybdenum MoSe2；Alternatively, the material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is telluride molybdenum MoTe2.It can also be other heterojunction regions materials, with no restrictions to this this programme.
Optionally, in one kind in the specific implementation, the material of first insulating layer can be silicon oxide sio2；The material of the second insulating layer can be yttrium oxide Y2O3Or aluminium oxide Al2O3Equal insulating materials.
In this scenario, this has tunnelling interface, the TFET device of source electrode, drain and gate.Tunnelling interface is made of two kinds of two-dimensional materials, and one of material is located at the top of another material, and the edge of two kinds of material crossover regions has oxide to be located at two kinds of storerooms.Source electrode and drain electrode is contacted with two kinds of 2D material formation respectively, and gate medium is located on the two-dimensional material of interface, and grid metal is located above gate medium, and source metal has insulating materials to be electrically isolated with another kind 2D material.
Hetero-junctions tunnel field effect transistor provided in this embodiment, it is isolated using the oxide of high quality as boundary of the second insulating layer to two-dimensional material, effectively reduce Leakage Current caused by marginality, channel is done using the thin two-dimensional material of local grid structure and atom level simultaneously, grid-control can be enhanced, so that the SS value of the hetero-junctions tunnel field effect transistor is smaller, tunnel barrier width can be made narrow by this heterojunction structure, simultaneously, the edge growth in two-dimensional material tunnelling interface has oxide thin layer layer, two two-dimensional materials are kept apart, to increase the tunneling distance of marginality.
Fig. 2 is the structural schematic diagram of the application hetero-junctions tunnel field effect transistor embodiment two, as shown in Fig. 2, hetero-junctions tunnel field effect transistor provided in this embodiment includes:
Substrate, source electrode, the first insulating layer, heterojunction material layer, drain electrode, gate dielectric layer and grid.
Wherein, the one end on surface over the substrate is arranged in source electrode；First insulating layer insertion setting is over the substrate for being arranged the position of drain electrode, the first heterojunction material layer is covered on the upper surface of the part substrate of part first insulating layer and the not set source electrode, second insulating layer is provided with around the other end of heterojunction material layer first insulating layer, the drain electrode setting is on the first insulating layer, and the outer side contacts of the drain electrode and the heterojunction material layer, position of the gate dielectric layer between source electrode and drain electrode, and the gate dielectric layer is covered on the substrate, the second insulating layer, on the heterojunction material layer, the grid is arranged on the gate dielectric layer.
One kind of the program is in the specific implementation, substrate is the substrate of n-type doping.
In the present solution, being isolated by second insulating layer, it is substantially reduced Leakage Current caused by marginality.
Fig. 3 b is the structural schematic diagram of another example of the application hetero-junctions tunnel field effect transistor；As shown in Figure 3b, for one kind of the program in the specific implementation, substrate is the InAs substrate of n-type doping, the heterojunction material layer is two tungsten selenide WSe2Layer.
First insulating layer and the second insulating layer can realize that i.e. the first insulating layer and second insulating layer can be the oxide skin(coating) of insulation by oxide.Optionally, the material of the second insulating layer is yttrium oxide Y2O3。
Hetero-junctions tunnel field effect transistor provided in this embodiment, it is isolated using the oxide of high quality as boundary of the second insulating layer to two-dimensional material, effectively reduce Leakage Current caused by marginality, channel is done using the thin two-dimensional material of local grid structure and atom level simultaneously, grid-control can be enhanced, so that the SS value of the hetero-junctions tunnel field effect transistor is smaller, tunnel barrier width can be made narrow by this heterojunction structure, avoid boundary defect caused by mismatching because of lattice, line tunneling structure is used simultaneously, increase tunnelling area, using the stagger-gap type hetero-junctions of low potential barrier, increase tunnelling probability, improve tunnelling current.
Fig. 4 is the flow chart of the preparation method embodiment one of the application hetero-junctions tunnel field effect transistor, as shown in figure 4, the preparation method of above-mentioned hetero-junctions tunnel field effect transistor shown in FIG. 1 provided in this embodiment, specifically includes following step
It is rapid:
S101: the substrate for being covered with the first insulating layer is provided, and the source region contacted with the first heterojunction material is defined by optical exposure over the substrate.
S102: source electrode is made by evaporation metal on the active region.
In above-mentioned steps, to prepare the field effect transistor, it is desirable to provide one is covered with the substrate of insulating layer as target substrate, which can be realized by oxide, such as silica etc..In order to realize hetero-junctions, need to be formed the first heterojunction material layer over the substrate using two-dimensional material, and the first heterojunction material layer etching is become into ribbon, and source region is defined on the first heterojunction material layer by optical exposure.
After the source region that the device has been determined, source metal (can be Cr/Pt) is deposited in the source region, forms the source electrode of the hetero-junctions tunnel field effect transistor.
S103: being defined the fringe region of the first heterojunction material layer by exposure development, and aoxidized in the fringe region evaporation metal, and second insulating layer is formed.
In this step, photoresist is coated on the first heterojunction material layer, development is exposed to define the fringe region of the first heterojunction material layer to come, the metal of high quality is deposited in the fringe region of the first heterojunction material layer for this, sample after vapor deposition is subjected to oxidation and forms the second insulating layer, in the present solution, second insulating layer is not contacted with source electrode.
S104: defining separation layer form by optical exposure, and oxide is deposited on the inside of the source electrode and forms separation layer.
In this step, position and the form of separation layer are similarly defined by optical exposure, and forms separation layer in corresponding position vapor deposition thick-oxide, which attaches on the inside of source electrode, and the position between source electrode and second insulating layer, it is not contacted with second insulating layer.Finally photoresist is removed.
S105: being transferred to the first heterojunction material layer for the second heterojunction material, defines form and perform etching to form the second heterojunction material layer by optical exposure, forms hetero-junctions with the first heterojunction material layer.
In this step, the first heterojunction material layer, second insulating layer and around the first insulating layer on shift the second heterojunction material, and the form of second heterojunction material is defined by optical exposure, second heterojunction material of exposure area is etched away, and remove photoresist, the second heterojunction material layer is obtained, which does not contact with source electrode.
In the program in the specific implementation, the realization of the first heterojunction material layer and the second heterojunction material layer includes at least following several schemes:
The first implementation: the material of the first heterojunction material layer is two stannic selenide SnSe2, the material of the second heterojunction material layer is two tungsten selenide WSe2。
Second of implementation: the material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is selenizing molybdenum MoSe2。
The third implementation: the material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is telluride molybdenum MoTe2。
S106: on the second heterojunction material layer, by lithographic definition drain region, and evaporation metal forms drain electrode.
In this step, drain region is defined on the second heterojunction material layer, and the metal that can be used as drain electrode is deposited, and forms the drain electrode contacted with the second heterojunction material layer.
S107: on the second heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
On the basis of the sample that above-mentioned steps obtain, using lithographic definition area of grid, and the deposition growing high-K gate dielectric oxide on the area of grid, gate dielectric layer is formed, and gate metal is deposited on gate dielectric layer and forms grid.
It is SiO by silicon Si, SnSe2-WSe2 hetero-junctions, the first insulating layer of substrate on the basis of the above process2, second insulating layer be yttrium oxide Y2O3For, preparation method provided in this embodiment is described in detail.Fig. 5 a-5g is the procedure structure schematic diagram of one example of preparation method of the application hetero-junctions tunnel field effect transistor.As shown in Fig. 5 a-5g, the preparation method concrete implementation step of the hetero-junctions tunnel field effect transistor are as follows:
Step 1: the target substrate (silicon substrate for having silica (the first insulating layer) as grown) with SnSe2 being provided, two stannic selenide SnSe2 of heterojunction material is etched into band structure as shown in figure Fig. 5 a.Optical exposure defines the source region contacted with SnSe2, then evaporation metal (such as Cr/Pt=2/60nm), obtains structure as shown in Figure 5 b (sectional view) using lift off technique.
Step 2: SnSe is defined by exposure development2The fringe region of layer, in the SnSe2The fringe region evaporation metal yttrium of layer, and oxidation processes are carried out, form Y2O3Insulating layer (second insulating layer).
Specifically, photoresist is spun on the sample in step 1, it is exposed development to it and defines SnSe2 fringe region, 2-3nm metallic yttrium is deposited, then carries out lift off technique.So that sample is aoxidized about 15min 180-200C (being put on hot plate or in baking oven), forms Y2O3.As shown in Figure 5 c.
Step 3: forming separation layer.Optical exposure defines separation layer, is deposited about 100nm thick-oxide (such as silica), removes photoresist using lift off technique, forms separation layer, as fig 5d.
Step 4: forming hetero-junctions.By WSe2It is transferred to SnSe2On layer, WSe is defined by optical exposure2Form, the WSe of dry etching removal exposure region is carried out using reactive ion etching (Reactive Ion Etching, RIE) or sense coupling (Inductively Couple Plasma Etch, ICP)2, photoresist is removed, WSe is formed2Layer, with the SnSe2Layer forms hetero-junctions, obtains structure as depicted in fig. 5e.
Step 5: in WSe2Lithographic definition drain region, the evaporation metal Cr/Pt/Au or MoO on the drain region are used on layer3/ Pt, formation and WSe2The drain electrode that layer is connected, preparation drain electrode.
Specifically, photoresist is applied on the sample through step 4, using lithographic definition drain region, then evaporation metal Cr/Pt/Au (about 2/60nm) or MoO3/Pt (about 3/60nm) forms the drain contact being connected with WSe2, photoresist is removed using lift off technique, obtains sample as shown in figure 5f.
Step 6: in WSe2Lithographic definition area of grid is used on layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
Specifically, photoresist is applied on the sample through step 5, using lithographic definition area of grid, high-k gate dielectric hafnium oxide (or the high-g values such as aluminium oxide, zirconium oxide) are grown using atomic layer deposition, it is deposited gate metal (such as Ti/Au:5/50nm), obtains sample as shown in fig. 5g using lift off technique removal photoresist.In this scenario, it should be understood that high-g value includes but is not limited to HfO2、Al2O3、ZrO2、Y2O3。
The atomic layer deposition can be low temperature ald technology, be also possible to the technique for atomic layer deposition of other modes, with no restrictions to this this programme.
Other similar techniques can be used also to realize in the structure that above step is realized, corresponding structural form also has a little difference, gate medium and grid metal are first grown as the formation of gate medium and gate electrode can be used, the method that exposure mask carries out wet etching is then done with photoresist and obtains；Other metals or semiconductor material with good conductivity also can be used in the metal electrode of source and drain and grid；The covering in edge of materials region also can be used other oxides and use other techniques, for example grow aluminium oxide using atomic layer deposition, then carries out corrosion again and obtains similar structure.
Fig. 6 is the flow chart of the preparation method embodiment two of the application hetero-junctions tunnel field effect transistor, as shown in fig. 6, the preparation method of above-mentioned hetero-junctions tunnel field effect transistor shown in Fig. 2 provided in this embodiment, specifically includes following step
It is rapid:
S201: the substrate of n-type doping is provided.
S202: etching a groove by RIE over the substrate, and oxide-isolation layer is generated in the groove, forms the first insulating layer.
In above-mentioned steps, lithographic definition oxide-isolation layer is used on the substrate of n-type doping, RIE is recycled to etch a groove over the substrate, using vapor deposition or atomic layer deposition (Atomic layer deposition, ALD oxide-isolation layer) is generated in a groove, forms first insulating layer.First insulating layer can be used oxide and be formed.
S203: being defined the fringe region of heterojunction material layer Yu the substrate contact by exposure development, and aoxidized in the fringe region evaporation metal, and second insulating layer is formed.
In this step, before heterojunction material layer, the fringe region of heterojunction material layer on substrate is defined by exposure development first, the metal of high quality is then deposited in the fringe region and carries out oxidation processes, forms second insulating layer.
S204: heterojunction material is transferred on the substrate, and is performed etching and to be formed heterojunction material layer.
In this step, which is coated in the range of second insulating layer.
S205: over the substrate by lithographic definition source region, and source electrode is made by evaporation metal on the source region.
In this step, lithographic definition source region is used at one section of the substrate, vapor deposition source metal Ti/Pt/Au forms source electrode in the source region.Source electrode is located on substrate, and does not contact with second insulating layer and heterojunction material layer.
S206: it is raw using lithographic definition drain region in first insulating layer, and formed and drained in the drain region evaporation metal.
In this step, lithographic definition drain region is used on the first insulating layer, vapor deposition can be used as the metal of drain electrode on the drain region, such as: Cr/Pt/Au or MoO3/ Pt, forms the drain electrode being connected with heterojunction material layer, and drain electrode is not contacted with second insulating layer.
S207: on the substrate, the second insulating layer and the heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
Lithographic definition area of grid is used on heterojunction material layer and second insulating layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
On the basis of the above process, using substrate be InAs, WSe2 hetero-junctions, second insulating layer is yttrium oxide Y2O3For, preparation method provided in this embodiment is described in detail.Fig. 7 a-7i is the procedure structure schematic diagram of another example of preparation method of the application hetero-junctions tunnel field effect transistor.As shown in Fig. 7 a-7i, the preparation method concrete implementation step of the hetero-junctions tunnel field effect transistor are as follows:
Step 1: forming separation layer.The InAs substrate of n-type doping is provided, photoresist is applied on InAs sample, using lithographic definition Oxide separation layer, then etches a groove (such as Fig. 7 a) in InAs substrate using RIE.Oxide-isolation layer is grown using vapor deposition or atomic layer deposition (Atomic layer deposition, ALD), separation layer can be the insulating materials such as silica, aluminium oxide, remove photoresist using lift off technique.Then surface rubbing is obtained by the structure such as Fig. 7 b using CMP process.
Step 2: photoresist being spun on the sample in step 1, development is exposed to it and defines the fringe region that WSe2 is contacted with substrate, 2-3nm metallic yttrium is deposited, then carries out lift off technique.Sample is set to aoxidize about 15min 180-200C (being put on hot plate or in baking oven).As Fig. 7 c is (left: sectional view；It is right: top view) shown in.
Step 3: transfer two-dimensional material layer.Substrate is placed in 35%HF:35%HCl=1:1 about 2 minutes removal InAs base oxides, chemical vapor deposition (Chemical Vapor Deposition, CVD) WSe2 grown is transferred in InAs substrate.It obtains as Fig. 7 d is (left: sectional view；It is right: top view) shown in structure.
Step 4: photoresist being spun on the sample in step 3, development is exposed to it, exposure mask is done with photoresist, the WSe2 of exposure is removed using dry etching, WSe2 is patterned, removes photoresist exposure mask.As Fig. 7 e is (left: sectional view；It is right: top view) shown in.
Step 5: forming source electrode.Photoresist is applied on the sample through step 4, using lithographic definition source region, then evaporation metal Ti/Pt/Au (about 5/20/30nm) forms source electrode (electrode contacted with InAs) contact, removes photoresist using lift off technique.As Fig. 7 f is (left: sectional view；It is right: top view).
Step 6: forming drain electrode.Photoresist is applied on the sample through step 5, using lithographic definition drain region, then evaporation metal Cr/Pt/Au (about 2/60nm) or MoO3/Pt (about 3/60nm) forms drain electrode (electrode contacted with WSe2) contact, removes photoresist using lift off technique.As Fig. 7 g is (left: sectional view；It is right: top view).
Step 7: forming high-k gate dielectric.Photoresist is applied on the sample through step 6, using lithographic definition area of grid.It is (left: sectional view using atomic layer deposition growth high-k gate dielectric hafnium oxide (or the high-g values such as aluminium oxide, zirconium oxide) (such as figure Fig. 7 h)；It is right: top view), it is deposited gate metal (such as Ti/Au:5/50nm), is obtained using lift off technique removal photoresist as Fig. 7 i is (left: sectional view；It is right: top view) shown in sample.
It is similar with above-described embodiment one, other similar techniques can be used also to realize in the structure that step in the preparation method is realized, gate medium and grid metal are first grown as the formation of gate medium and gate electrode can be used, the method that exposure mask carries out wet etching is then done with photoresist and obtains.
The hetero-junctions TFET based on two-dimensional material mentioned in the application is also applied for thickness and the hetero-junctions TFET that the block materials of (nanoscale) are formed is thinned.
The preparation method of hetero-junctions tunnel field effect transistor provided by the above embodiment uses the oxide such as Y of high quality during the preparation process2O3It does and is isolated, be substantially reduced leakage current caused by marginality, and grid-control is enhanced using local grid structure, be easier to realize the SS for being less than 60mV/dec, channel is done using the thin two-dimensional material of atom level, grid-control can be further enhanced.Hetero-junctions is formed using two-dimensional material, avoids boundary defect caused by mismatching because of lattice；Using line tunneling structure, increase tunnelling area.Using the stagger-gap type hetero-junctions of low potential barrier, increase tunnelling probability, improves tunnelling current, while making tunneling barrier width narrow.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the application, rather than its limitations.
Claims (20)
- A kind of hetero-junctions tunnel field effect transistor characterized by comprisingSubstrate；First insulating layer；First insulating layer is covered on the upper surface of the substrate；First heterojunction material layer, the first heterojunction material layer are covered on the upper surface of first insulating layer for one end of source electrode to be arranged；Source electrode, the source electrode are arranged in one end of the first heterojunction material layer, are provided with second insulating layer around the first heterojunction material layer other end；Separation layer, the separation layer are arranged on the hetero junction layer, and the separation layer is covered on the inside of the source electrode；Second heterojunction material layer, the second heterojunction material layer are covered in the other end, second insulating layer and the second insulating layer of the first heterojunction material layer, form hetero-junctions with the first heterojunction material layer；The other end opposite with the source electrode on second hetero junction layer is arranged in drain electrode, the drain electrode；Gate dielectric layer, the gate dielectric layer are covered on the position on the second heterojunction material layer between source electrode and drain electrode；Grid, the grid are arranged on the gate dielectric layer.
- Hetero-junctions tunnel field effect transistor according to claim 1, which is characterized in that the material of the first heterojunction material layer is two stannic selenide SnSe2, the material of the second heterojunction material layer is two tungsten selenide WSe2；Alternatively,The material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is selenizing molybdenum MoSe2；Alternatively,The material of the first heterojunction material layer is SnSe2, the material of the second heterojunction material layer is telluride molybdenum MoTe2。
- Hetero-junctions tunnel field effect transistor according to claim 1 or 2, which is characterized in that first insulating layer and the second insulating layer are oxide insulating layer.
- Hetero-junctions tunnel field effect transistor according to claim 3, which is characterized in that the material of first insulating layer is silicon oxide sio2；The material of the second insulating layer is yttrium oxide Y2O3Or aluminium oxide Al2O3。
- A kind of hetero-junctions tunnel field effect transistor characterized by comprisingSubstrate；The one end on surface over the substrate is arranged in source electrode, the source electrode；First insulating layer；The first insulating layer insertion setting is over the substrate for being arranged the position of drain electrode；Heterojunction material layer, the first heterojunction material layer are covered on the upper surface of the part substrate of part first insulating layer and the not set source electrode, are provided with second insulating layer around the other end of heterojunction material layer first insulating layer；Drain electrode, the drain electrode are arranged on the first insulating layer, and the outer side contacts of the drain electrode and the heterojunction material layer；Gate dielectric layer, position of the gate dielectric layer between source electrode and drain electrode, and the gate dielectric layer are covered on the substrate, the second insulating layer and the heterojunction material layer；Grid, the grid are arranged on the gate dielectric layer.
- Hetero-junctions tunnel field effect transistor according to claim 5, which is characterized in that the heterojunction material Layer is two tungsten selenide WSe2Layer.
- Hetero-junctions tunnel field effect transistor according to claim 5 or 6, which is characterized in that first insulating layer and the second insulating layer are oxide insulating layer.
- Hetero-junctions tunnel field effect transistor according to claim 7, which is characterized in that the material of the second insulating layer is yttrium oxide Y2O3。
- A kind of preparation method of hetero-junctions tunnel field effect transistor characterized by comprisingThe substrate for being covered with the first insulating layer is provided, and the source region contacted with the first heterojunction material is defined by optical exposure over the substrate；Source electrode is made by evaporation metal on the active region；The fringe region of the first heterojunction material layer is defined by exposure development, and is aoxidized in the fringe region evaporation metal, and second insulating layer is formed；Separation layer form is defined by optical exposure, oxide is deposited on the inside of the source electrode and forms separation layer；Second heterojunction material is transferred to the first heterojunction material layer, defines form and perform etching to form the second heterojunction material layer by optical exposure, forms hetero-junctions with the first heterojunction material layer；On the second heterojunction material layer, by lithographic definition drain region, and evaporation metal forms drain electrode；On the second heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
- According to the method described in claim 9, it is characterized in that, when the first heterojunction material layer is SnSe2Layer, second insulating layer are yttrium oxide Y2O3, then it is described that the fringe region of the first heterojunction material layer is defined by exposure development, and aoxidized in the fringe region evaporation metal, form second insulating layer, comprising:SnSe is defined by exposure development2The fringe region of layer, in the SnSe2The fringe region evaporation metal yttrium of layer, and oxidation processes are carried out, form Y2O3Insulating layer.
- According to the method described in claim 10, it is characterized in that, the second heterojunction material layer is WSe2Layer, it is described that second heterojunction material is transferred to the first heterojunction material layer, it defines form and performs etching to form the second heterojunction material layer by optical exposure, form hetero-junctions with the first heterojunction material layer, comprising:By WSe2It is transferred to SnSe2On layer, WSe is defined by optical exposure2Form, the WSe of dry etching removal exposure region is carried out using reactive ion etching RIE or sense coupling ICP2, photoresist is removed, WSe is formed2Layer, with the SnSe2Layer forms hetero-junctions.
- According to the method for claim 11, which is characterized in that on the second heterojunction material layer, by lithographic definition drain region, and evaporation metal forms drain electrode, comprising:In WSe2Lithographic definition drain region, the evaporation metal Cr/Pt/Au or MoO on the drain region are used on layer3/ Pt, formation and WSe2The drain electrode that layer is connected.
- According to the method for claim 12, which is characterized in that on the second heterojunction material layer, form gate dielectric layer by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer, comprising:In WSe2Lithographic definition area of grid is used on layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
- A kind of preparation method of hetero-junctions tunnel field effect transistor characterized by comprisingThe substrate of n-type doping is provided；A groove is etched over the substrate by reactive ion etching RIE, oxide-isolation layer is generated in the groove, forms the first insulating layer；The fringe region of heterojunction material layer Yu the substrate contact is defined by exposure development, and is aoxidized in the fringe region evaporation metal, and second insulating layer is formed；Heterojunction material is transferred on the substrate, and performs etching and to form heterojunction material layer；Over the substrate by lithographic definition source region, and source electrode is made by evaporation metal on the source region；It is raw using lithographic definition drain region in first insulating layer, and formed and drained in the drain region evaporation metal；On the substrate, the second insulating layer and the heterojunction material layer, gate dielectric layer is formed by lithographic definition area of grid, and using atomic layer deposition mode, and grid is set on the gate dielectric layer.
- According to the method for claim 14, which is characterized in that it is described that a groove is etched by reactive ion etching RIE over the substrate, oxide-isolation layer is generated in the groove, forms the first insulating layer, comprising:Lithographic definition oxide-isolation layer is used over the substrate, reactive ion etching RIE is recycled to etch a groove over the substrate, and oxide-isolation layer is generated in the groove using vapor deposition or atomic layer deposition ALD, forms first insulating layer.
- Method according to claim 14 or 15, which is characterized in that the heterojunction material layer is two tungsten selenide WSe2Layer, the material of the second insulating layer are yttrium oxide Y2O3, then the fringe region of heterojunction material layer Yu the substrate contact is defined by exposure development, and aoxidized in the fringe region evaporation metal, form second insulating layer, comprising:The fringe region of WSe2 and substrate contact is defined using exposure development over the substrate, evaporation metal yttrium is simultaneously aoxidized, and Y is formed2O3Layer.
- According to the method for claim 16, which is characterized in that it is described that heterojunction material is transferred on the substrate, and perform etching and to form heterojunction material layer, comprising:The WSe2 of chemical vapor deposition CVD growth is transferred on the substrate, and removes the WSe2 of exposure using dry etching, forms WSe2 layers.
- According to the method for claim 17, which is characterized in that it is described over the substrate by lithographic definition source region, and source electrode is made by evaporation metal on the source region, comprising:One section in the substrate uses lithographic definition source region, forms source electrode in the source region evaporation metal Ti/Pt/Au.
- According to the method for claim 18, which is characterized in that it is described raw using lithographic definition drain region in first insulating layer, and formed and drained in the drain region evaporation metal, comprising:Lithographic definition drain region, the evaporation metal Cr/Pt/Au or MoO on the drain region are used on the first insulating layer3/ Pt, formation and WSe2The drain electrode that layer is connected.
- Method described in 9 according to claim 1, which is characterized in that described on the substrate, the second insulating layer and the heterojunction material layer, pass through lithographic definition area of grid, and gate dielectric layer is formed using atomic layer deposition mode, and grid is set on the gate dielectric layer, comprising:In WSe2Layer and Y2O3Lithographic definition area of grid is used on layer, using atomic layer deposition growth high-k gate dielectric hafnium oxide, aluminium oxide or zirconium oxide, is formed gate dielectric layer, and gate metal is deposited on the gate dielectric layer, is formed grid.
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