WO2021227296A1

WO2021227296A1 - Transistor and method for fabricating the same

Info

Publication number: WO2021227296A1
Application number: PCT/CN2020/110885
Authority: WO
Inventors: Haitao Xu; Ningfei GAO; Xiaodong Du
Original assignee: Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd.
Priority date: 2020-05-11
Filing date: 2020-08-24
Publication date: 2021-11-18
Also published as: CN113644112B; CN113644112A

Abstract

Disclosed are a transistor and a method for fabricating a transistor. The transistor includes a base; a narrow-gap material layer provided on the base and having a channel region; a source and a drain provided on and in contact with a surface of the narrow-gap material layer away from the base; a sidewall covering each of sides of the drain and the source and extending along the channel region to at least form a boss close to the drain; a gate dielectric layer covering the boss and the narrow-gap material layer between the source and the drain; and a gate covering the gate dielectric layer.

Description

TRANSISTOR AND METHOD FOR FABRICATING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefits of Chinese Patent Application Serial No. 202010393413.6, filed with the National Intellectual Property Administration of P. R. China on May 11, 2010, the entire content of which is incorporated herein by reference.

FIELD

The present disclosure relates to a field of semiconductor technology, in particularly to a transistor and a method for fabricating a transistor.

BACKGROUND

Carbon nanotubes are ideal channel materials for transistors, with excellent physical and chemical characteristics such as one-dimensional nanostructure, ultra-thin thickness, high mobility, perfect lattice, high physical and chemical stability, and high thermal conductivity. Transistors with channels made of carbon nanotubes have significant advantages in extreme performance and energy utilization efficiency over traditional transistors. In a transistor, a gate controls distribution of carriers in a channel between a source and a drain, and thus controls, in combination with the applied source-drain voltage, the channel to be switched on or switched off.

However, a transistor with a channel made of carbon nanotubes and a method for fabricating the transistor still need to be improved.

SUMMARY

The present disclosure is based on discoveries and recognitions of the following facts and issues.

Existing transistors using carbon nanotubes as channel materials have problems such as large off-state leakage current, short lifetime, and low reliability. It is found by the inventors of the present disclosure that these problems of the existing transistors are caused due to a relatively drastic change in energy band near the drain (refer to a schematic diagram showing an energy band of a CNT-PMOS device in an off state as shown in Fig. 2) under an operating voltage between the source and the drain and a gate voltage. Specifically, for the existing transistors, high-K dielectric materials are usually used for a gate dielectric layer to improve gate control. However, it also brings about the problem that the energy band near the drain changes drastically, that is, when the transistor is turned on, the energy band near the drain side is bended, in favor of carriers in the channel to have higher energy when they approach the drain. High-speed carriers collide with the gate dielectric layer and the base near the drain side, resulting in charge injection, or the carriers collide with the drain to generate a large amount of heat. With accumulation of running time, the gate dielectric layer and the base near the drain side are damaged, and migration happens to metal materials of the drain, thus deteriorating drain structure and reducing the lifetime of the device. Since carbon nanotubes are used as narrow-gap materials, dramatic change in the energy band makes Schottky barrier at the drain side thinner when the transistor is in the off state. At a high bias voltage, reverse tunneling may easily happen to the carriers at the drain side, resulting in a larger off-state leakage current and increasing power consumption of the transistor.

Embodiments of the present disclosure seek to solve at least one of the problems existing in the related art to at least some extent.

In an aspect, the present disclosure provides in embodiments a transistor. The transistor includes a base; a narrow-gap material layer provided on the base and having a channel region; a source and a drain provided on and in contact with a surface of the narrow-gap material layer away from the base; a sidewall covering each of sides of the drain and the source and extending along the channel region to at least form a boss close to the drain; a gate dielectric layer covering the boss and the narrow-gap material layer between the source and the drain; and a gate covering the gate dielectric layer. When the transistor is in an on state, the energy band at the drain side changes gently, which avoids significant acceleration of the carriers caused by excessive band bending, thus reducing impact of the carriers on the gate dielectric layer, the base at the drain side and on the drain, and reducing thermal migration of the drain and damage to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In some embodiments, a ratio of a length of the boss to a length of the gate is in a range of 0.01 to 0.5. Therefore, the energy band at the drain side may be well-adjusted without significantly reducing transconductance of the transistor.

In some embodiments, a material for the narrow-gap material layer comprises at least one of carbon nanotubes, nanowires, and two-dimensional materials. Therefore, the above-mentioned material is suitable for the channel material of the transistor, and thus provides the transistor with excellent performance.

In some embodiments, the gate dielectric layer is made of a high-K dielectric material comprising at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8. Therefore, the transistor can have improved gate control, and based on the improved gate control, the energy band can be adjusted by using the structure described above to alleviate excessive bending of the energy band at the drain side.

In some embodiments, the sidewall is made of an insulating dielectric material. In this way, insulation between the source/drain and the gate can be achieved.

In some embodiments, the sidewall is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. Therefore, a thickness of an equivalent gate dielectric of a region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side.

In some embodiments, the sidewall is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride. That is, the boss of the sidewall is also made of the low-K dielectric material, which can further increase the thickness of the equivalent gate dielectric of the region where the boss is located, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. Moreover, the sidewall can reduce parasitic capacitance between the gate and the source/drain.

In some embodiments, the sidewall further covers surfaces of the source and the drain away from the base. In this way, the source and the drain can be isolated from the air to realize passivation protection for the source and the drain. The sidewall covering the source and the drain and extending along the channel region can be synchronously formed by a self-alignment process.

In some embodiments, the boss of the sidewall has a fixed charge or a dipole, or an interface between the boss of the sidewall and the gate dielectric layer has a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole to adjust the energy band and further alleviate excessive bending of the energy band at the drain side.

In some embodiments, the base includes a substrate and an electrically-insulating layer disposed on the substrate.

In some embodiments, the gate dielectric layer includes a first sub-layer covering the narrow-gap material layer between the source and the drain, and a second sub-layer covering the boss and the first sub-layer.

In another aspect, the present disclosure provides in embodiments a method for fabricating a transistor, comprising: providing a narrow-gap material layer on a base wherein the narrow-gap material layer has a channel region; providing a source and a drain on and in contact with a surface of the narrow-gap material layer away from the base; providing a sidewall covering each of sides of the drain and the source and extending along the channel region to at least form a boss close to the drain; providing a gate dielectric layer covering the boss and the narrow-gap material layer between the source and the drain; providing a gate covering the gate dielectric layer. When the transistor fabricated by the above method is in an on state, the energy band at the drain side changes gently, which avoids significant acceleration of the carriers caused by excessive band bending, thus reducing impact of the carriers on the drain, the gate dielectric layer and the base at the drain, and reducing thermal migration of the drain and damage such as charge injection to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor fabricated by the above method is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In some embodiments, provisions of the source, the drain and the sidewall comprise: depositing a first photoresist layer and a second photoresist layer in sequence on the surface of the narrow-gap material layer away from the base; exposing and developing the second photoresist layer and the first photoresist layer to expose a portion of the narrow-gap material layer in such a way that a length of an opening of the first photoresist layer is greater than a length of an opening of the second photoresist layer in an extension direction of the first photoresist layer; providing the source and the drain on the portion of the narrow-gap material layer that is exposed, respectively, wherein an orthographic projection of the source and an orthographic projection of the drain on the base are within a range of an orthographic projection of the opening of the second photoresist layer on the base, respectively, a length of the source and a length of the drain are the same as the length of the opening of the second photoresist layer in an extension direction of the second photoresist layer, respectively, and a height of the first photoresist layer is greater than that of each of the source and the drain; depositing a sidewall material layer on a surface and a side of the second photoresist layer, a side of the first photoresist layer, the surface of the narrow-gap material layer away from the base, and surfaces and sides of the source and the drain, wherein a first part of the sidewall material layer covering the side of the first photoresist layer is spaced apart by a clearance from each of a second part of the sidewall material layer covering the side of the source and the third part of the sidewall material layer covering the side of the drain; and peeling the first photoresist layer and the second photoresist layer off to form the sidewall in such a way that a part of the sidewall material layer covering the surface of the narrow-gap material layer below the clearance remains and forms the boss on the channel region. Therefore, the sidewall covering the source and the drain and extending along the channel region can be synchronously formed by the self-alignment process, thus simplifying the operations and reducing the cost. The boss is formed by the extension part of the sidewall, and thus a thickness of an equivalent gate dielectric of a region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. In this way, the source/drain can be insulated from the gate, and the source and the drain can be isolated from the air to realize passivation protection for the source and the drain. Moreover, the gate may be formed by the self-alignment process, so as to achieve the improved gate control.

In some embodiments, before depositing the first photoresist layer and the second photoresist layer in sequence on the surface of the narrow-gap material layer away from the base, the method further includes: providing a protective material layer on the surface of the narrow-gap material layer away from the base, to allow the first photoresist layer and the second photoresist layer to be deposited in sequence on a surface of the protective material layer away from the base. In some embodiments, exposing and developing the second photoresist layer and the first photoresist layer to expose the portion of the narrow-gap material layer comprises: exposing and developing the second photoresist layer and the first photoresist layer to expose a portion of the protective material layer, and removing the portion of the protective material layer to expose the portion of the narrow-gap material layer. Therefore, the protective material layer can prevent the narrow-gap material layer from being damaged and polluted when the first and second photoresist layers are exposed and developed. When the protective material layer is etched, a lattice structure of the narrow-gap material will not be damaged, the narrow-gap material layer will not be damaged or polluted, and impurities and molecules adsorbed on the surface of the narrow-gap material layer can be removed to improve a performance of the narrow-gap material layer.

In some embodiments, removing the portion of the protective material layer comprises: chemically etching the protective material layer with a reaction solution or a reaction gas, and washing with water. Therefore, when the protective material layer is etched, the lattice structure of the narrow-gap material will not be destroyed and the narrow-gap material layer will not be damaged or polluted.

In some embodiments, the reactive solution includes an acidic solution or an alkaline solution. Therefore, the protective material layer can be patterned by the reaction of the protective material with the acidic solution or the alkaline solution. Moreover, the lattice structure of the narrow-gap material will not be destroyed and the narrow-gap material layer will not be damaged or polluted in the reaction.

In some embodiments, the acidic solution includes at least one selected from hydrochloric acid, acetic acid, nitric acid, phosphoric acid and sulphuric acid. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above acidic solution. Moreover, the lattice structure of the narrow-gap material will not be destroyed and the narrow-gap material layer will not be damaged or polluted.

In some embodiments, the alkaline solution includes at least one selected from potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above alkaline solution. Moreover, the lattice structure of the narrow-gap material will not be destroyed and the narrow-gap material layer will not be damaged or polluted.

In some embodiments, the reactive gas includes at least one selected from hydrogen chloride and hydrogen fluoride. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above reactive gas, and the lattice structure of the narrow-gap material will not be destroyed.

In some embodiments, a material for the protective material layer includes at least one selected from yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. Therefore, the protective material layer can prevent the narrow-gap material layer from being damaged and polluted when the first and second photoresist layers are exposed and developed. When the protective material layer is etched, the lattice structure of the narrow-gap material will not be damaged, the narrow-gap material layer will not be damaged or polluted, and impurities and molecules adsorbed on the surface of the narrow-gap material layer can be removed to improve the performance of the narrow-gap material layer.

In some embodiments, provision of the gate dielectric layer includes: providing the gate dielectric layer on a surface of the boss and the surface of the narrow-gap material layer between the source and the drain away from the base. Therefore, impurities and molecules adsorbed on the surface of the narrow-gap material layer can be removed to improve the performance of the narrow-gap material layer.

In some embodiments, the sidewall is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. Therefore, the thickness of the equivalent gate dielectric of the region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and advantages of embodiments of the present disclosure will become apparent and more readily appreciated from the following descriptions made with reference to the drawings, in which:

Fig. 1 is a schematic cross-sectional view of a transistor according to an embodiment of the present disclosure;

Fig. 2 is a schematic diagram showing an energy band of a traditional transistor in an off state;

Fig. 3 is a schematic diagram showing an energy band of a transistor in an off state according to an embodiment of the present disclosure;

Fig. 4 is a flow chart of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 5 is a flow chart of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 6 is a flow chart of other operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 7 is a flow chart of operations of a method for fabricating a transistor according to another embodiment of the present disclosure;

Fig. 8 is a flow chart of other operations of a method for fabricating a transistor according to another embodiment of the present disclosure;

Fig. 9 is a schematic cross-sectional view of a transistor of Comparative Example 1;

Fig. 10 is a graph showing a transfer characteristic curve of a transistor of Example 1; and

Fig. 11 is a graph showing a transfer characteristic curve of a transistor of Comparative Example 1.

Reference numerals:

base 100, narrow-gap material layer 200, drain 300, source 400, sidewall 500, sidewall material layer 510, gate dielectric layer 600, first sub-layer 610, second sub-layer 620, gate 700, protective material layer 810, boss 10, first photoresist layer 30, second photoresist layer 40.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail in the following descriptions, examples of which are shown in the accompanying drawings, in which the same or similar elements and elements having same or similar functions are denoted by like reference numerals throughout the descriptions. The embodiments described herein with reference to the accompanying drawings are explanatory and illustrative, which are used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.

In an aspect, the present disclosure provides in embodiments a transistor. As shown in Fig. 1, the transistor includes a base 100, a narrow-gap material layer 200, a drain 300, a source 400, a sidewall 500, a gate dielectric layer 600 and gate 700. Specifically, the narrow-gap material layer 200 is provided on the base 100 and has a channel region. The source 400 and the drain 300 are provided on and in contact with a surface of the narrow-gap material layer 200 away from the base 100. The sidewall 500 covers sides of the drain 300 and the source 400 and extends along the channel region to at least form a boss 10 close to the drain. The gate dielectric layer 600 covers the boss 10 and the narrow-gap material layer 200 between the source 400 and the drain 300. The gate 700 covers the gate dielectric layer 600. When the transistor is in the on state, the energy band at the drain side changes gently, which avoids significant acceleration of carriers caused by excessive band bending, thus reducing impact of the carriers on the gate dielectric layer 600, the base 100 at the drain side and on the drain 300, and reducing thermal migration of the drain 300 and damage to the gate dielectric layer 600 and the base 100. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

With the transistor according to the embodiments of the present disclosure, the sidewall 500 extends along the channel region to form the boss 10, which can increase a thickness of an equivalent gate dielectric of a region where the boss 10 is located, so as to reduce gate control of the channel region below the boss 10, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, significant acceleration of the carriers caused by excessive band bending can be alleviated, thus reducing impact of the carriers on the gate dielectric layer 600, the base 100 at the drain side and on the drain 300, and reducing thermal migration of the drain 300 and damage to the gate dielectric layer 600 and the base 100. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state the energy band at the drain side changes gently (indicated by a dotted line in Fig. 3) , such that the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In an embodiment of the present disclosure, in the present transistor, the sidewall 500 has a boss 10 extending along the channel region at the drain side. Alternatively, besides the boss at the drain side, the sidewall 500 also has a boss 10 extending along the channel region at the source side. In this way, the transistor may have a symmetric structure, and maintain the high performance in the on state, thus facilitating subsequent circuit design.

Each structure of the transistor according to embodiments of the present disclosure will be described in details below.

In some embodiments of the present disclosure, a ratio of a length (L ₁ as shown in Fig. 1) of the boss 10 to a length (L ₂ as shown in Fig. 1) of the gate 700 is in a range of 0.01 to 0.5, e.g., 0.01, 0.05, 0.1, 0.3 and 0.5. It has been found that when the length of the boss 10 meets the above requirement, a good control of the energy band at the drain side may be realized, the excessive bending of the energy band can be effectively alleviated, and the length of the boss 10 will not be too long such that the transconductance of the transistor will not be significantly reduced. It should be noted that when the sidewall extends along the channel region to form another boss 10 at the source side, a ratio of a length of the boss 10 to the length of the gate 700 is also in the range of 0.01 to 0.5.

In some embodiments of the present disclosure, a material for the narrow-gap material layer 200 includes at least one of carbon nanotubes, nanowires, and two-dimensional materials. Specifically, the carbon nanotube may be a single carbon nanotube, a network carbon nanotube array or an oriented carbon nanotube array, and the two-dimensional materials may include layered narrow-gap materials, e.g., black phosphorus or molybdenum disulfide. Therefore, the transistor with the channel made of the above materials has excellent performances. The material for the narrow-gap material layer may be single-walled carbon nanotubes. The transistors with channels made of the single-walled carbon nanotubes have better performance since the single-walled carbon nanotubes have higher mobility and fewer surface dangling bonds than other narrow-gap materials.

In some embodiments, the sidewall 500 is made of an insulating dielectric material. Therefore, the source 400 and the drain 300 may be isolated from the gate 700.

In some embodiments, the sidewall 500 is made of a high-K dielectric material or a low-K dielectric material. The high-K dielectric material includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. The low-K dielectric material includes at least one of silicon oxide, silicon nitride and silicon oxynitride. Therefore, a thickness of an equivalent gate dielectric of a region where the boss 10 is located can be increased, so as to reduce the gate control of the channel region below the boss 10, and further alleviate excessive bending of the energy band at the drain side. In an alternative embodiment of the present disclosure, the sidewall 500 is made of the low-K dielectric material having a small dielectric constant. When the sidewall 500 is made of the low-K dielectric material, the boss 10 of the sidewall 500 is also made of the low-K dielectric material, which can further increase the thickness of the equivalent gate dielectric of the region where the boss is located, so as to reduce the gate control of the channel region below the boss 10, and further alleviate excessive bending of the energy band at the drain side. Moreover, the sidewall 500 can reduce parasitic capacitance between the gate 700 and the source 400/drain 300.

In some embodiments of the present disclosure, the boss 10 of the sidewall 500 has a fixed charge or a dipole, or an interface between the boss 10 of the sidewall 500 and the gate dielectric layer 600 has a dipole. Therefore, the channel region below the boss 10 can be electrostatically controlled by the fixed charge or the dipole to adjust the energy band and further alleviate excessive bending of the energy band at the drain side. The boss 10 of the sidewall 500 has the fixed charge, particularly, is made of a material having the fixed charge. Alternatively, all the sidewall 500 is made of the material having the fixed charge, thus facilitating the fabrication of the transistor. For example, process parameters can be adjusted so that the material forming the sidewall 500 has the fixed charge. The boss 10 of the sidewall 500 has the dipole, particularly, is made of two kinds of materials and the dipole is formed at the interface of the two materials. Alternatively, all the sidewall 500 is made of the two materials and the dipole is formed at the interface of the two materials, thus facilitating the fabrication of the transistor. For example, a first sidewall material and a second sidewall material are deposited sequentially (for example, by atomic layer deposition) , and the dipole is formed at the interface of the first sidewall material and the second sidewall material. By adjusting the specific materials of the first and second sidewall materials, the boss 10 of the sidewall 500 can have the dipole. Alternatively, by adjusting specific materials of the boss 10 of the sidewall 500 and the gate dielectric layer 600, the dipole is formed at the interface between the boss 10 of the sidewall 500 and the gate dielectric layer 600. The transistor may be a P-type transistor or an N-type transistor. The channel region of the P-type transistor below the boss 10 can be doped with holes by the fixed charge or the dipole, and the channel region of the N-type transistor below the boss 10 can be doped with electrons by the fixed charge or the dipole.

It should be noted that specific component (such as aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide) , structure and morphology of the sidewall 500 are not particularly limited herein as long as it has the fixed charge or the dipole or the interface between the boss 10 of the sidewall 500 and the gate dielectric layer 600 has the dipole.

In some embodiments, the gate dielectric layer 600 is made of a high-K dielectric material. The high-K dielectric material includes metal oxides which may be incorporated with Si or N. The high-K dielectric material may include at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8. Therefore, the transistor can have improved gate control, and based on the improved gate control, the energy band can be adjusted by using the structure described above to alleviate excessive bending of the energy band at the drain side.

In some embodiments of the present disclosure, as shown in Fig. 1, the sidewall 500 further covers each of surfaces of the source 400 and the drain 300 away from the base 100. In this way, the source 400 and the drain 300 can be isolated from the air to realize passivation protection for the source 400 and the drain 300. The sidewall 500 covering the sides and the surfaces of the source 400 and the drain 300 and extending along the channel region can be synchronously formed by a self-alignment process.

In some embodiments of the present disclosure, the source 400 and the drain 300 may be made of any metal material that is suitable for forming the source 400 and the drain 300. For example, palladium (Pd) or scandium (Sc) may be used, to allow the source 400 and the drain 300 to be in a P-type or N-type ohmic contact with the narrow-gap material layer 200.

The base 100 of the transistor may be made of any suitable composition or material, which can be selected by those skilled in the art. For example, the base 100 may include a silicon substrate and a silicon oxide layer, a glass layer, a polymer layer or other electrically-insulating layer disposed on the silicon substrate.

In another aspect, the present application provides in embodiments a method for fabricating a transistor. In some embodiments, the transistor prepared the present method may be the transistor described above. Therefore, features and advantages of the transistor described in the above embodiments may also applicable to the transistor prepared by the present method, which are not described in detail again here.

As shown in Fig. 4, the method of the present disclosure includes the following operations.

In S100, a narrow-gap material layer having a channel region is provided on a base.

In this operation, the narrow-gap material layer is formed on the base, and the narrow-gap material layer has the channel region. Details of the base and the narrow-gap material layer may refer to the features of the base and the narrow-gap material layer described in the above transistor embodiments, which are not described again here.

The narrow-gap material layer may be provided in any suitable manner, for example, by physical transfer or solution deposition.

In S200, a source, a drain and a sidewall are provided on a surface of the narrow-gap material layer away from the base.

In some embodiments, the source and the drain are provided on and in contact with the surface of the narrow-gap material layer away from the base. The sidewall covers sides of the drain and the source and extends along the channel region to at least form a boss close to the drain, which can increase a thickness of an equivalent gate dielectric of a region where the boss is located, so as to reduce gate control of the channel region below the boss, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, significant acceleration of the carriers caused by excessive band bending can be alleviated, thus reducing impact of the carriers on the gate dielectric layer, the base at the drain side and on the drain, and reducing thermal migration of the drain and damage to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the energy band at the drain side changes gently, such that the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In some embodiments, as shown in Figs. 5 and 6, provisions of the source, the drain and the sidewall include the following operations.

A first photoresist layer 30 and a second photoresist layer 40 are deposited in sequence on the surface of the narrow-gap material layer 200 away from the base 100 (as shown in Fig. 5 (a) ) .

The second photoresist layer 40 and the first photoresist layer 30 are exposed and developed to expose a portion of the narrow-gap material layer 200 in such a way that a length of an opening of the first photoresist layer 30 is greater than a length of an opening of the second photoresist layer 40 in an extension direction of the first photoresist layer 30 (as shown in Fig. 5 (b) ) . Specific materials and formation methods of the first photoresist layer 30 and the second photoresist layer 40 are not particularly limited, as long as the length of the opening of the first photoresist layer 30 is greater than the length of the opening of the second photoresist layer 40. For example, under an illumination condition, the second photoresist layer 40 changes, but the first photoresist layer 30 basically does not change. In this case, the properties of the second photoresist layer 40 are changed by the exposure, and the second photoresist layer 40 is developed by a corresponding developer to form the opening in the layer. Then, a developer that reacts with the first photoresist layer 30 is selected and used to form the opening in the first photoresist layer to allow the length of the opening of the first photoresist layer 30 to be greater than the length of the opening in the second photoresist layer 40. Alternatively, both the first photoresist layer 30 and the second photoresist layer 40 are changed by the illumination condition, and are respectively developed with different developers, to allow the length of the opening of the first photoresist layer 30 to be greater than the length of the opening of the second photoresist layer 40. Alternatively, both the first photoresist layer 30 and the second photoresist layer 40 are changed by the illumination condition. The same developer is used for both layers, and development periods of the first photoresist layer 30 and the second photoresist layer 40 are controlled so that the length of the opening of the first photoresist layer 30 is greater than that of the second photoresist layer 40. Alternatively, electron beam lithography is applied. The first photoresist layer 30 is made of a material that is more sensitive to electron beam lithography, so that the length of the opening of the first photoresist layer 30 is greater than the length of the opening of the second photoresist layer 40.

The source 400 and the drain 300 are formed on the portion of the narrow-gap material layer 200 that is exposed, respectively. An orthographic projection of the source 400 and an orthographic projection of the drain 300 on the base 100 are within a range of an orthographic projection of the opening of the second photoresist layer 40 on the base, respectively. A length of the source 400 and a length of the drain 300 are the same as the length of the opening of the second photoresist layer 40 in an extension direction of the second photoresist layer 40, respectively, and a height of the first photoresist layer 30 is greater than that of each of the source 400 and the drain 300 (as shown in Fig. 5 (c) ) . Although Fig. 5 (c) shows the drain 300 only, the source 400 and the drain 300 can be formed simultaneously. A method for forming the source and drain may be electron beam evaporation coating or magnetic sputtering. These methods may provide a high collimation and is convenient for forming the source and the drain on the exposed part of the narrow-gap material layer. The orthographic projections of the source and the drain on the base are respectively located within the range of the orthographic projection of the opening of the second photoresist layer on the base, the lengths of the source or the drain are the same with the length of the opening of the second photoresist layer, and the height of the first photoresist layer is greater than the height of the source and drain, such that sufficient space can be reserved for the subsequent provision of the sidewall. The specific size of the opening of the first photoresist layer or the second photoresist layer is not particularly limited, as long as it is suitable for forming a boss of a desired length.

A sidewall material layer 510 is deposited on a surface and a side of the second photoresist layer 40, a side of the first photoresist layer 30, the surface of the narrow-gap material layer 200, and surfaces and sides of the source 400 and the drain 300. Specifically, a first part of the sidewall material layer 510 covering the side of the first photoresist layer 30 is spaced apart by a clearance from each of a second part of the sidewall material layer 510 covering the side of the source 400 and a third part of the sidewall material layer 510 covering the side of the drain 300 (as shown in Fig. 6 (d) , Fig. 6 (d) shows the drain 300 only since the source 400 and the drain 300 can be formed simultaneously) . The sidewall material layer 510 may be formed by atomic layer deposition.

The first photoresist layer 30 and the second photoresist layer 40 are peeled off to form the sidewall 500 in such a way that a part of the sidewall material layer 510 covering the surface of the narrow-gap material layer 200 below the clearance remains and forms the boss 10 on the channel region (as shown in Fig. 6 (e) ) . Therefore, the sidewall covering the source and the drain and extending along the channel region can be synchronously formed by the self-alignment process, thus simplifying the operations and reducing the cost. The boss is formed by the extension part of the sidewall, and thus a thickness of an equivalent gate dielectric of a region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. In this way, the source/drain can be insulated from the gate, and the source and the drain can be isolated from the air to realize passivation protection for the source and the drain. Moreover, the gate may be formed by the self-alignment process, so as to achieve the improved gate control.

In some embodiments, as shown in Figs. 7 and 8, the provision of the source, the drain and the sidewall includes the following operations.

A protective material layer 810 is deposited on the surface of the narrow-gap material layer 200 away from the base 100 (as shown in Fig. 7 (a) ) . Material for the protective material layer is not particularly limited, as long as it can be patterned by a non-destructive etching method (such as wet etching or vapor etching) . For example, the material for the protective material layer may include at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. Therefore, the protective material layer can prevent the narrow-gap material layer from being damaged and polluted when the first and second photoresist layers are exposed and developed. When the protective material layer is etched, a lattice structure of the narrow-gap material will not be damaged, the narrow-gap material layer will not be damaged or polluted, and impurities and molecules adsorbed on the surface of the narrow-gap material layer can be removed to improve a performance of the narrow-gap material layer.

The protective material layer may be provided by any suitable method, e.g., physical vapor deposition (PVD) , chemical vapor deposition (CVD) , atomic layer deposition (ALD) and spin coating. When the protective material layer is made of silicon oxide, the silicon oxide may be formed on the narrow-gap material layer by the spin coating, which is easy to operate. Alternatively, the silicon oxide can be formed on the narrow-gap material layer by the thermal deposition without negatively affecting the performance of the narrow-gap material layer.

The first photoresist layer 30 and the second photoresist layer 40 are deposited in sequence on a surface of the protective material layer 810 away from the base 100. The second photoresist layer 40 and the first photoresist layer 30 are exposed and developed to expose a portion of the protective material layer 810 in such a way that the length of the opening of the first photoresist layer 30 is greater than the length of the opening of the second photoresist layer 40. The portion of the protective material layer 810 is removed to expose the portion of the narrow-gap material layer 200 (as shown in Fig. 7 (b) ) .

In some embodiments, removing the portion of the protective material layer 810 includes: chemically etching the protective material layer with a reactive solution or a reactive gas, and washing with water. Therefore, when the protective material layer is chemically etched, the lattice structure of the narrow-gap material will not be destroyed, and the narrow-gap material layer will not be damaged or polluted.

In some embodiments, the reactive solution may include an acidic solution or an alkaline solution. Therefore, the protective material layer may be patterned by the reaction of the protective material with the acidic solution or the alkaline solution without destroying the lattice structure of the narrow-gap material and damaging or polluting the narrow-gap material layer in the reaction.

The specific components of the acidic solution and the alkaline solution are not particularly limited. For example, the acidic solution may include at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid, and the alkaline solution may include at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. Therefore, the portion of the protective material layer is removed by the reaction of the protective material with the acidic solution or the alkaline solution described above without destroying the lattice structure of the narrow-gap material and damaging or polluting the narrow-gap material layer in the reaction. For example, hydrochloric acid is used as an acidic solution and an yttrium oxide layer is used as a protective material layer, hydrochloric acid can react with yttrium oxide to form liquid yttrium chloride, and water can be used to wash away excess hydrochloric acid and yttrium chloride to make the protective material patterned. Hydrochloric acid can clean the surface of the narrow-gap material layer without sacrificing the properties of the narrow-gap material layer, and can remove impurities introduced in the process to make the exposed part of the narrow-gap material layer have a good surface for performing a good electrostatic control after the subsequent deposition of the sidewall. When the protective material layer is made of aluminum oxide, phosphoric acid can be used to chemically etch the protective material layer; and when the protective material layer is made of silicon oxide, potassium hydroxide can be used to chemically etch the protective material layer without damaging the lattice structure of the narrow-gap material.

The specific composition of the reactive gas is not particularly limited. For example, the reactive gas may include at least one of hydrogen chloride and hydrogen fluoride. Therefore, the reactive gas described above can react with the protective material layer to remove the portion of the protective material layer without destroying the lattice structure of the narrow-gap material.

The source 400 and the drain 300 are formed on the portion of the narrow-gap material layer 200 that is exposed, respectively. An orthographic projection of the source 400 and an orthographic projection of the drain 300 on the base 100 are within a range of an orthographic projection of the opening of the second photoresist layer 40 on the base, respectively. A length of the source 400 and a length of the drain 300 are the same as the length of the opening of the second photoresist layer 40 in an extension direction of the second photoresist layer 40, respectively, and a height of the first photoresist layer 30 is greater than that of each of the source 400 and the drain 300 (as shown in Fig. 7 (c) ) . Although Fig. 7 (c) shows the drain 300 only, the source 400 and the drain 300 can be formed simultaneously.

A sidewall material layer 510 is deposited on a surface and a side of the second photoresist layer 40, a side of the first photoresist layer 30, a side of the protective material layer 810, the surface of the narrow-gap material layer 200, and surfaces and sides of the source 400 and the drain 300. Specifically, a first part of the sidewall material layer 510 covering the side of the first photoresist layer 30 is spaced apart by a clearance from each of a second part of the sidewall material layer 510 covering the side of the source 400 and a third part of the sidewall material layer 510 covering the side of the drain 300 (as shown in Fig. 8 (d) , Fig. 8 (d) shows the drain 300 only since the source 400 and the drain 300 can be formed simultaneously) .

The first photoresist layer 30 and the second photoresist layer 40 are peeled off to form the sidewall 500 in such a way that a part of the sidewall material layer 510 covering the surface of the narrow-gap material layer 200 below the clearance remains and forms the boss 10 on the channel region (as shown in Fig. 8 (e) ) . Therefore, the sidewall covering the source and the drain and extending along the channel region can be synchronously formed by the self-alignment process, thus simplifying the operations and reducing the cost. The boss is formed by the extension part of the sidewall, and thus a thickness of an equivalent gate dielectric of a region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. In this way, the source/drain can be insulated from the gate, and the source and the drain can be isolated from the air to realize passivation protection for the source and the drain. Moreover, the gate may be formed by the self-alignment process, so as to achieve the improved gate control. It should be noted that relationship between the protective material layer and the sidewall material layer in the thickness is not particularly limited. For example, the thickness of the protective material layer may be less than the thickness of the sidewall material layer, or the thickness of the protective material layer may be equal to the sidewall material layer, or the thickness of the protective material layer may be greater than the sidewall material layer. It is noted that the thickness of the sidewall is generally thin. Therefore, when the first photoresist layer and the second photoresist layer are peeled off, the sidewall material layer along the side of the first photoresist layer to the surface of the narrow-gap material layer may be simultaneously peeled off, but the sidewall material layer remains at the clearance to form the boss on the channel region.

In some embodiments, the sidewall is made of an insulating dielectric material. In this way, insulation between the source/drain and the gate can be achieved. In some embodiments, the sidewall is made of any suitable high-K dielectric material or low-K dielectric material. For example, the high-K dielectric material for the sidewall includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. For another example, the low-K dielectric material for the sidewall includes at least one of silicon oxide, silicon nitride and silicon oxynitride. Therefore, a thickness of an equivalent gate dielectric of a region where the boss is located can be increased, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. In a preferable embodiment, the sidewall is made of the low-K dielectric material which has a small dielectric constant. When the sidewall is made of the low-K dielectric material, the boss of the sidewall is also made of the low-K dielectric material, which can further increase the thickness of the equivalent gate dielectric of the region where the boss is located, so as to reduce the gate control of the channel region below the boss, and further alleviate excessive bending of the energy band at the drain side. Moreover, the sidewall can reduce parasitic capacitance between the gate and the source/drain.

In some embodiments, when the sidewall is made of the high-K dielectric material, the high-K dielectric material can be deposited by thermal atomic layer deposition, and when the sidewall is made of the low-K dielectric material, the low-K dielectric material can be deposited by atomic layer deposition.

In some embodiments, the boss of the sidewall has a fixed charge or a dipole, or an interface between the boss of the sidewall and the gate dielectric layer has a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole to adjust the energy band and further alleviate excessive bending of the energy band at the drain side. The boss of the sidewall has the fixed charge, particularly, is made of a material having the fixed charge. Alternatively, all the sidewall is made of the material having the fixed charge, thus facilitating the fabrication of the transistor. The boss of the sidewall has the dipole, particularly, is made of two kinds of materials and the dipole is formed at the interface of the two materials. Alternatively, all the sidewall is made of the two materials and the dipole is formed at the interface of the two materials, thus facilitating the fabrication of the transistor. For example, a first sidewall material and a second sidewall material are deposited sequentially (for example, by atomic layer deposition) , and the dipole is formed at the interface of the first sidewall material and the second sidewall material. By adjusting the specific materials of the first and second sidewall materials, the boss of the sidewall can have the dipole. Alternatively, by adjusting specific materials of the boss of the sidewall and the gate dielectric layer, the dipole is formed at the interface between the boss of the sidewall and the gate dielectric layer.

In S300, a gate dielectric layer is provided.

In some embodiments, the gate dielectric layer 600 covers the boss 10 and the narrow-gap material layer 200 between the source 400 and the drain 300 (as shown in Fig. 6 (f) ) .

As shown in Fig. 6 (f) , after the first and second photoresist layers are peeled off, the gate dielectric layer 600 covers the boss 10 and the narrow-gap material layer 200 which is not covered by the sidewall 500 between the source 400 and the drain 300. The gate dielectric layer 600 may be formed by atomic layer deposition.

Alternatively, after the first and second photoresist layers are peeled off, the portion of the protective material between the source 400 and the drain 300 is removed to expose the portion of the narrow-gap material layer 200. The gate dielectric layer 600 is formed on the surface of the boss 10 away from the base 100 and the portion of the narrow-gap material layer 200 which is exposed (as shown in Fig. 6 (f) ) . Therefore, impurities and molecules adsorbed on the surface of the narrow-gap material layer can be removed to improve the performance of the narrow-gap material layer. Moreover, the number of materials suitable for the gate dielectric layer may be increased.

Alternative, as shown in Fig. 8 (f) , the gate dielectric layer includes a first sub-layer 610 and a second sub-layer 620. The first sub-layer 610 is a portion of the protective material layer 810 between the source 400 and the drain 300. After the first and second photoresist layers are peeled off, the second sub-layer is formed on a surface of the first sub-layer 610 away from the base 100. Therefore, when the first and second photoresist layers are exposed and developed, the protective material layer may prevent the narrow-gap material layer from being damaged or polluted, and the portion of the protective material layer between the source 400 and the source 300 may be applied as part of the gate dielectric layer. In this case, a material for the first sub-layer may include yttrium oxide, lanthanum oxide and aluminum oxide.

It should be noted that, when the first and second photoresist layers are peeled off, a portion of the sidewall along the side of the first photoresist layer to the surface of the narrow-gap material layer is peeled off simultaneously. Usually, there will be a clearance between the boss of the sidewall and the first sub-layer (as shown in Fig. 8 (e) ) . When the second sub-layer is provided, the clearance will be filled with the second sub-layer (as shown in Fig. 8 (f) ) . In a preferable embodiment, the portion of the protective material layer between the source and the drain is removed, and the gate dielectric layer is deposited with the high-K dielectric material, so as to alleviate excessive bending of the energy band at the drain side.

In S400, a gate is provided.

The gate may be formed in any suitable manner, e.g., by electron beam evaporation coating or magnetic sputtering.

With the method for fabricating a transistor according to the embodiments of the present disclosure, when the fabricated transistor is in the on state, the energy band at the drain side changes gently, which avoids significant acceleration of the carriers caused by excessive band bending, thus reducing impact of the carriers on the gate dielectric layer, the base at the drain side and on the drain, and reducing thermal migration of the drain and damage (such as charge injection) to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

The present disclosure is further described with the following examples.

Example 1

As shown in Fig. 1, a transistor includes a base 100, a narrow-gap material layer 200, a source 400, a drain 300, a sidewall 500, a gate dielectric layer 600 and a gate 700. The narrow-gap material layer 200 has a channel region. The sidewall 500 covers a surface and sides of the drain 300 and extends along the channel region to form a boss, and the sidewall 500 covers a surface and sides of the source 400 and extends along the channel region to form a boss. The sidewall 500 is made of hafnium oxide. The gate dielectric layer 600 is made of yttrium oxide and hafnium oxide. The narrow-gap material layer 200 is carbon nanotubes.

The source 400 and the drain 300 are made of Pd to constitute a P-type transistor (PMOS) . The source 400 and the drain 300 are made of Sc to constitute an N-type transistor (NMOS) . The transistor is fabricated with the method of the present disclosure as described above.

Comparative Example 1

As shown in Fig. 9, a transistor includes a base 100, a narrow-gap material layer 200 disposed on the base 100, a source 400 and a drain 300 disposed on a surface of the narrow-gap material layer 200 away from the base 100, a gate dielectric layer 600 covering a portion of the source 400, a portion of the narrow-gap material layer 200 between the source 400 and the drain 300 and a portion of the drain 300, and a gate 700 covering the gate dielectric layer 600. The gate dielectric layer 600 is made of HfO ₂, and the narrow-gap material layer 200 is made of carbon nanotubes.

The source 400 and the drain 300 are made of Pd to constitute a P-type transistor (PMOS) . The source 400 and the drain 300 are made of Sc to constitute an N-type transistor (NMOS) .

The transistor is fabricated as follows.

First, a layer of carbon nanotubes is formed on the base. Subsequently, a polymethyl methacrylate (PMMA) layer is provided on a surface of the layer of carbon nanotubes away from the base, and the PMMA layer is patterned to form grooves arranged at clearances. Subsequently, source and drain metals are deposited in the grooves, and the source and drain metals are patterned to form the source and the drain in the grooves, and the PMMA layer is removed. After this, a PMMA structure is formed at a side of the source away from the drain and at a side of the drain away from the source. The PMMA structure at the source side covers a part of the source and the PMMA structure at the drain side covers a part of the drain. Subsequently, HfO ₂ is deposited on the PMMA structure, the source, the drain and the layer of carbon nanotubes at a surface away from the base to form a continuous layer of gate dielectric material, and the gate metal is deposited on a surface of the HfO ₂ layer away from the base. Finally, the PMMA structure is removed, and the HfO ₂ layer along the side of the PMMA structure is simultaneously removed, thus fabricating the transistor.

Performance tests are performed on the transistors of Example 1 and Comparative Example 1, respectively. Figs. 10 and 11 show transfer characteristic curves of the two transistors to indicate switching characteristics of the two transistors under the gate voltage. Fig. 10 is a graph showing the transfer characteristic curve of the transistor of Example 1, and Fig. 11 is a graph showing the transfer characteristic curve of the transistor of Comparative Example 1.

It can be seen from Figs. 10 and 11 that compared with the transistor of Comparative Example 1 (i.e., a traditional high-K gate dielectric self-aligned carbon nanotube transistor) , the transistor of Example 1 has a significantly lower off-state current and a higher switch ratio, and at the same time has a more suitable threshold voltage.

It should be noted that in Figs. 10 and 11, I _ds represents a current between the source and the drain, V _ds represents a voltage between the source and the drain, V _gs represents a voltage between the gate and the source, and L/W represents a ratio of a length of the gate to a width of the channel region.

In the present invention, unless specified or limited otherwise, a structure in which a first feature is “on” or “below” a second feature may include an embodiment in which the first feature is in direct contact with the second feature, and may also include an embodiment in which the first feature and the second feature are not in direct contact with each other, but are contacted via an additional feature formed therebetween. Furthermore, a first feature “on, ” “above, ” or “on top of” a second feature may include an embodiment in which the first feature is right or obliquely “on, ” “above, ” or “on top of” the second feature, or just means that the first feature is at a height higher than that of the second feature; while a first feature “below, ” “under, ” or “on bottom of” a second feature may include an embodiment in which the first feature is right or obliquely “below, ” “under, ” or “on bottom of” the second feature, or just means that the first feature is at a height lower than that of the second feature.

Reference throughout this specification to “an embodiment, ” “some embodiments, ” “one embodiment” , “another example, ” “an example, ” “a specific example, ” or “some examples, ” means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. Thus, the appearances of the phrases such as “in some embodiments, ” “in one embodiment” , “in an embodiment” , “in another example, ” “in an example, ” “in a specific example, ” or “in some examples, ” in various places throughout this specification are not necessarily referring to the same embodiment or example of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications may be made in the embodiments without departing from spirit and principles of the disclosure. In addition, it should be noted that terms such as “first” and “second” are used herein for purposes of description and are not intended to indicate or imply relative importance or significance.

Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that the above embodiments cannot be construed to limit the present disclosure, and changes, alternatives, and modifications can be made in the embodiments without departing from spirit, principles and scope of the present disclosure.

Claims

A transistor, comprising:

a base;

a narrow-gap material layer provided on the base and having a channel region;

a source and a drain provided on and in contact with a surface of the narrow-gap material layer away from the base;

a sidewall covering each of sides of the drain and the source and extending along the channel region to at least form a boss close to the drain;

a gate dielectric layer covering the boss and the narrow-gap material layer between the source and the drain; and

a gate covering the gate dielectric layer.
The transistor according to claim 1, wherein a ratio of a length of the boss to a length of the gate is in a range of 0.01 to 0.5;

optionally, a material for the narrow-gap material layer comprises at least one of carbon nanotubes, nanowires, and two-dimensional materials;

optionally, the gate dielectric layer is made of a high-K dielectric material comprising at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8.
The transistor according to claim 1 or 2, wherein the sidewall is made of an insulating dielectric material;

optionally, the sidewall is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide;

optionally, the sidewall is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride;

optionally, the sidewall further covers surfaces of the source and the drain away from the base.
The transistor according to any one of claims 1 to 3, wherein the boss of the sidewall has a fixed charge or a dipole, or an interface between the boss of the sidewall and the gate dielectric layer has a dipole.
The transistor according to any one of claims 1 to 4, wherein the base comprises a substrate and an electrically-insulating layer disposed on the substrate.
The transistor according to any one of claims 1 to 5, wherein the gate dielectric layer comprises:

a first sub-layer covering the narrow-gap material layer between the source and the drain, and a second sub-layer covering the boss and the first sub-layer.
A method for fabricating a transistor, comprising:

providing a narrow-gap material layer on a base wherein the narrow-gap material layer has a channel region;

providing a source and a drain on and in contact with a surface of the narrow-gap material layer away from the base;

providing a sidewall covering each of sides of the drain and the source and extending along the channel region to at least form a boss close to the drain;

providing a gate dielectric layer covering the boss and the narrow-gap material layer between the source and the drain;

providing a gate covering the gate dielectric layer.
The method according to claim 7, wherein provisions of the source, the drain and the sidewall comprise:

depositing a first photoresist layer and a second photoresist layer in sequence on the surface of the narrow-gap material layer away from the base;

exposing and developing the second photoresist layer and the first photoresist layer to expose a portion of the narrow-gap material layer in such a way that a length of an opening of the first photoresist layer is greater than a length of an opening of the second photoresist layer in an extension direction of the first photoresist layer;

providing the source and the drain on the portion of the narrow-gap material layer that is exposed, respectively, wherein an orthographic projection of the source and an orthographic projection of the drain on the base are within a range of an orthographic projection of the opening of the second photoresist layer on the base, respectively, a length of the source and a length of the drain are the same as the length of the opening of the second photoresist layer in an extension direction of the second photoresist layer, respectively, and a height of the first photoresist layer is greater than that of each of the source and the drain;

depositing a sidewall material layer on a surface and a side of the second photoresist layer, a side of the first photoresist layer, the surface of the narrow-gap material layer away from the base, and surfaces and sides of the source and the drain, wherein a first part of the sidewall material layer covering the side of the first photoresist layer is spaced apart by a clearance from each of a second part of the sidewall material layer covering the side of the source and a third part of the sidewall material layer covering the side of the drain; and

peeling the first photoresist layer and the second photoresist layer off to form the sidewall in such a way that a part of the sidewall material layer covering the surface of the narrow-gap material layer below the clearance remains and forms the boss on the channel region.
The method according to claim 7, wherein before depositing the first photoresist layer and the second photoresist layer in sequence on the surface of the narrow-gap material layer away from the base, the method further comprises:

providing a protective material layer on the surface of the narrow-gap material layer away from the base, to allow the first photoresist layer and the second photoresist layer to be deposited in sequence on a surface of the protective material layer away from the base.
The method according to claim 9, wherein exposing and developing the second photoresist layer and the first photoresist layer to expose the portion of the narrow-gap material layer comprises:

exposing and developing the second photoresist layer and the first photoresist layer to expose a portion of the protective material layer, and

removing the portion of the protective material layer to expose the portion of the narrow-gap material layer.
The method according to claim 10, wherein removing the portion of the protective material layer comprises: chemically etching the protective material layer with a reactive solution or a reactive gas, and washing with water;

optionally, the reactive solution comprises an acidic solution or an alkaline solution;

optionally, the acidic solution comprises at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid;

optionally, the alkaline solution comprises at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide;

optionally, the reactive gas comprises at least one of hydrogen chloride and hydrogen fluoride;

optionally, a material for the protective material layer comprises at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide and aluminum oxide.
The method according to any one of claims 7 to 11, wherein provision of the gate dielectric layer comprises:

providing the gate dielectric layer on a surface of the boss and the surface of the narrow-gap material layer between the source and the drain away from the base.
The method according to any one of claims 7 to 12, wherein the base comprises a substrate and an electrically-insulating layer disposed on the substrate.
The method according to any one of claims 7 to 13, wherein the gate dielectric layer comprises:

a first sub-layer covering the narrow-gap material layer between the source and the drain, and a second sub-layer covering the boss and the first sub-layer.
The method according to any one of claims 7 to 14, wherein a ratio of a length of the boss to a length of the gate is in a range of 0.01 to 0.5;

optionally, the sidewall is made of an insulating dielectric material;

optionally, the sidewall is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide;

optionally, the sidewall is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride;

optionally, the boss of the sidewall has a fixed charge or a dipole, or an interface between the boss of the sidewall and the gate dielectric layer has a dipole.