CN113644112B - Transistor and manufacturing method - Google Patents
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- CN113644112B CN113644112B CN202010393413.6A CN202010393413A CN113644112B CN 113644112 B CN113644112 B CN 113644112B CN 202010393413 A CN202010393413 A CN 202010393413A CN 113644112 B CN113644112 B CN 113644112B
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H10K10/40—Organic transistors
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- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- H10K10/40—Organic transistors
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- H10K10/40—Organic transistors
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Abstract
The invention discloses a transistor and a manufacturing method thereof. The transistor includes: a substrate and a layer of narrow bandgap material disposed on the substrate, the layer of narrow bandgap material having a channel region; a source and a drain, the source and drain being located on a side of the layer of narrow bandgap material remote from the substrate, the source and drain both being in contact with the layer of narrow bandgap material; the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form a step, and the side wall at least has a step at one side close to the drain electrode; a gate dielectric layer covering the step and the narrow bandgap material layer between the source and drain; and the grid electrode covers the grid medium layer. When the transistor is in an off state, the energy band of the drain side changes smoothly, potential barrier thinning caused by excessive bending of the energy band of the drain side is relieved, reverse tunneling of drain current carriers is inhibited, and off-state leakage current is reduced; when the transistor is in a conducting state, the energy band of the drain side is gently changed, so that the impact of a current carrier on the drain is reduced, the structure of the transistor is more reliable, and the service life of the transistor is prolonged.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a transistor and a manufacturing method thereof.
Background
The carbon nano tube is an ideal transistor channel material and has excellent physical and chemical characteristics such as one-dimensional ultrathin, high mobility, perfect crystal lattice, high physical and chemical stability, high thermal conductivity and the like. The ultimate performance and energy utilization efficiency of a transistor using carbon nanotubes as a channel material are significantly superior to those of a conventional transistor. In the transistor, the carrier distribution in a channel between a source electrode and a drain electrode is controlled through a grid electrode, and the channel between the source electrode and the drain electrode is switched on or off by combining applied source-drain voltage.
However, the transistor using carbon nanotube as channel material and the manufacturing method thereof still need to be improved.
Disclosure of Invention
The present invention is made based on the discovery and recognition by the inventors of the following facts and problems:
at present, transistors using carbon nanotubes as channel materials have the problems of large off-state leakage current, short device life, low reliability and the like. The inventor finds that this is mainly caused by the fact that in the existing transistor, under the action of the voltage between the source and the drain and the gate voltage, the energy band close to the drain has a relatively drastic change (refer to fig. 2, which is a schematic diagram of the energy band corresponding to the off state of the carbon nanotube PMOS device). Specifically, a high-K dielectric material is usually selected as a gate dielectric layer of an existing transistor to improve gate control, but the problem that an energy band close to a drain changes severely is also caused, that is, in an on state of the transistor, an energy band at a drain side is bent, so that a carrier in a channel has high energy when approaching the drain, and the high-speed carrier collides with the gate dielectric layer and a substrate at the drain side to generate charge injection or collides with the drain to generate a large amount of heat, so that the gate dielectric layer and the substrate at the drain side are damaged along with accumulation of operation time, and a metal material forming the drain migrates, so that a drain structure deteriorates, and a service life of the device is reduced. And because the carbon nano tube is a narrow-band gap material, the schottky barrier thickness on the drain side is thinned due to the drastic change of an energy band in the off state of the transistor, and under high bias voltage, reverse tunneling is easily generated on carriers on the drain side, so that large off-state leakage current is caused, and the power consumption of the transistor is increased.
The present invention aims to alleviate or solve at least to some extent at least one of the above mentioned problems.
In one aspect of the invention, a transistor is provided. The transistor includes: a substrate and a layer of narrow bandgap material disposed on the substrate, the layer of narrow bandgap material having a channel region; a source and a drain located on a side of the narrow bandgap material layer remote from the substrate, the source and drain both being in contact with the narrow bandgap material layer; the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form a step, and the step is arranged on at least one side of the side wall close to the drain electrode; a gate dielectric layer covering the step and the narrow bandgap material layer between the source and the drain; and the grid electrode covers the grid dielectric layer. When the transistor is in a conducting state, the energy band change of the drain electrode side is relatively smooth, the great acceleration of current carriers caused by the excessive bending of the energy band is relieved, the impact of the current carriers on a grid dielectric layer, a substrate and a drain electrode on the drain electrode side is reduced, the heat migration of the drain electrode and the damage to the grid dielectric layer and the substrate are reduced, the structure of the transistor is more reliable, the service life is prolonged, the Schottky barrier on the drain electrode side becomes thicker when the transistor is in a turn-off state, the reverse tunneling of the current carriers is relieved, the off-state leakage current is effectively reduced, and the power consumption of the transistor is reduced.
According to the embodiment of the invention, the ratio of the length of the step on one side of the side wall to the length of the grid is 0.01-0.5. Thereby, a good tuning of the drain side energy band can be achieved, while the transconductance of the transistor is not significantly reduced.
According to an embodiment of the invention, the material forming the layer of narrow bandgap material comprises at least one of carbon nanotubes, nanowires, two dimensional materials. Therefore, the transistor has excellent performance by using the material as a channel material of the transistor.
According to the embodiment of the invention, the gate dielectric layer is formed by a high-K dielectric material, and the high-K dielectric material comprises Al2O3、HfO2、ZrO2、TiO2、HfOxNy、LaOxNy、Y2O3、La2O3At least one of (a). Therefore, the transistor has good grid control, and on the basis of ensuring the transistor to have good grid control, the energy band is adjusted by using the structure described above to relieve leakageExcessive bending of the polar bands.
According to the embodiment of the invention, the side wall is made of an insulating medium material. Therefore, the source and drain electrodes can be insulated from the grid electrode.
According to an embodiment of the invention, the sidewall is formed of a high-K dielectric material, and the high-K dielectric material includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, and lanthanum oxide. Therefore, the equivalent gate dielectric thickness of the region where the step is located can be increased, the gate control capability of the gate to the channel region below the step is reduced, and the excessive bending of the energy band at the drain side is further relieved.
According to the embodiment of the invention, the side wall is formed by a low-K dielectric material, and the low-K dielectric material comprises at least one of silicon oxide, silicon nitride and silicon oxynitride. Namely, the step part of the side wall is also made of low-K dielectric materials, so that the equivalent gate dielectric thickness of the region where the step is located can be further increased, the gate control capability of the gate to a channel region below the step is reduced, the excessive bending of an energy band on the drain electrode side is further relieved, and the parasitic capacitance between the source electrode and the drain electrode and the gate electrode can be reduced by the side wall.
According to the embodiment of the invention, the side wall further covers the surface of one side of the source electrode and the drain electrode, which is far away from the substrate. Therefore, the source and the drain can be isolated from the air, passivation protection of the source and the drain is realized, and the side wall which covers the source and the drain and extends to the channel region can be synchronously formed through the self-alignment process.
According to the embodiment of the invention, the steps of the side wall have fixed charges or dipoles, or the interface between the steps of the side wall and the gate dielectric layer has dipoles. Therefore, the channel region below the step can be electrostatically regulated through fixed charges or dipoles so as to adjust the energy band, and the excessive bending of the energy band at the drain side is further relieved.
In another aspect of the invention, a method of fabricating a transistor is provided. The method comprises the following steps: forming a layer of narrow bandgap material on a substrate, the layer of narrow bandgap material having a channel region; forming a source and a drain on a side of the narrow bandgap material layer remote from the substrate, the source and drain both being in contact with the narrow bandgap material layer; forming a side wall, wherein the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form a step, and the step is arranged on at least one side of the side wall close to the drain electrode; forming a gate dielectric layer covering the step and the narrow bandgap material layer between the source and the drain; and forming a grid electrode, wherein the grid electrode covers the grid dielectric layer. Therefore, when the transistor obtained by the method is in a conducting state, the energy band change of the drain electrode side is relatively smooth, the great acceleration of current carriers caused by the excessive bending of the energy band is relieved, the impact of the current carriers on the drain electrode, the gate dielectric layer on the drain electrode side and the substrate is reduced, the thermal migration of the drain electrode and the damage to the charge injection and the like of the gate dielectric layer on the drain electrode side and the substrate are reduced, the structure of the transistor is more reliable, and the service life of the transistor is prolonged; when the transistor obtained by the method is in an off state, the Schottky barrier on the drain side becomes thick, reverse tunneling of carriers is relieved, off-state leakage current is effectively reduced, and power consumption of the transistor is reduced.
According to an embodiment of the present invention, forming the source electrode, the drain electrode, and the sidewall spacers includes: sequentially depositing a first glue layer and a second glue layer on one side of the narrow bandgap material layer away from the substrate; exposing and developing the second adhesive layer and the first adhesive layer to expose a part of the narrow bandgap material layer, and enabling the length of the opening in the first adhesive layer to be larger than that of the opening in the second adhesive layer in the extending direction of the first adhesive layer; forming the source electrode and the drain electrode on the exposed part of the narrow bandgap material layer respectively, wherein orthographic projections of the source electrode and the drain electrode on the substrate are respectively located in the orthographic projection range of the opening in the second glue layer on the substrate, and in the extending direction of the second glue layer, the lengths of the source electrode and the drain electrode are respectively consistent with the length of the opening in the second glue layer, and the height of the first glue layer is greater than the heights of the source electrode and the drain electrode; depositing a side wall material layer along the surface and the side wall of the second adhesive layer, the side wall of the first adhesive layer, the surface of the narrow band gap material layer, the side wall and the surface of the source electrode, and the side wall and the surface of the drain electrode, wherein the side wall material layer covers the part of the side wall of the first adhesive layer, and gaps are respectively reserved between the part of the side wall material layer covering the side wall of the source electrode and the part of the side wall material layer covering the side wall of the drain electrode; and stripping the first adhesive layer and the second adhesive layer to form a side wall, wherein the part of the side wall, which is positioned in the gap and in the channel region, forms the step. Therefore, the side wall which covers the source and drain electrodes and extends towards the channel region can be synchronously formed by adopting a self-alignment process, the process steps are simplified, the process cost is reduced, the extending part of the side wall forms a step, the equivalent gate dielectric thickness of the region where the step is located is increased, the gate control capability of the grid electrode on the channel region below the step is reduced, the excessive bending of the energy band of the drain electrode side is relieved, the side wall can realize the insulation between the source and drain electrodes and the grid electrode, the source and drain electrodes are isolated from air, the passivation protection of the source and drain electrodes is realized, and the subsequent grid electrode can be formed under the self-alignment process, so that the grid control is good.
According to an embodiment of the invention, before forming the first glue layer and the second glue layer on the side of the narrow bandgap material layer away from the substrate, further comprising: forming a layer of protective material on a side of the layer of narrow bandgap material remote from the substrate; and exposing a part of the protective material layer after exposing and developing the second adhesive layer and the first adhesive layer, removing the exposed part of the protective material layer, and exposing a part of the narrow bandgap material layer. From this, when exposing, developing first glue film, second glue film, the protective material layer can protect the narrow band gap material layer to avoid damage and pollution to when carrying out chemical etching to the protective material layer that forms by above-mentioned material, can not destroy the lattice structure of narrow band gap material, not only can not lead to the fact damage and pollution to the narrow band gap material layer, can also get rid of narrow band gap material layer surface adsorption's impurity and molecule etc. for the performance of narrow band gap material layer obtains better performance.
According to the embodiment of the invention, after the first glue layer and the second glue layer are stripped, the part of the protective material layer between the source electrode and the drain electrode is removed, a part of the narrow bandgap material layer is exposed, and the gate dielectric layer is formed on the side of the step far away from the substrate and the part of the narrow bandgap material layer exposed. Therefore, impurities, molecules and the like adsorbed on the surface of the narrow band gap material layer in the channel region can be removed, the performance of the narrow band gap material layer is better exerted, and the material selection range of the gate dielectric layer can be larger.
According to an embodiment of the invention, removing a portion of the layer of protective material comprises: and chemically etching the protective material layer by using a reaction solution or a reaction gas, and cleaning by using water. Thus, the lattice structure of the narrow bandgap material is not destroyed and the narrow bandgap material layer is not damaged or contaminated when the protective material layer is chemically etched.
According to an embodiment of the present invention, the reaction solution includes an acidic solution or a basic solution. From this, react through acid solution or alkaline solution and protective material layer, can realize the patterning to the protective material layer, and the process of acid solution or alkaline solution and protective material layer reaction can not destroy the lattice structure of narrow band gap material, can not cause damage and pollution to the narrow band gap material layer.
According to an embodiment of the invention, the acidic solution comprises at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid and sulfuric acid. Therefore, the acid solution can be utilized to react with the protective material layer to remove part of the protective material layer, the lattice structure of the narrow band gap material cannot be damaged, and the narrow band gap material layer cannot be damaged or polluted.
According to an embodiment of the invention, the alkaline solution comprises at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide. Thus, the alkaline solution can be used to react with the protective material layer to remove a portion of the protective material layer without destroying the lattice structure of the narrow bandgap material.
According to an embodiment of the present invention, the reaction gas includes at least one of hydrogen chloride and hydrogen fluoride. Thus, the reactive gas may react with the protective material layer to remove portions of the protective material layer without destroying the lattice structure of the narrow bandgap material.
According to an embodiment of the present invention, a material constituting the protective material layer includes at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. From this, when exposing, developing first glue film, second glue film, the protective material layer can protect the narrow band gap material layer to avoid damage and pollution to when carrying out the sculpture to the protective material layer that is formed by above-mentioned material, can not destroy the lattice structure of narrow band gap material, not only can not lead to the fact damage and pollution to the narrow band gap material layer, can also get rid of the impurity and the molecule etc. of narrow band gap material layer surface adsorption, make the performance of narrow band gap material layer obtain better performance.
According to the embodiment of the invention, the ratio of the length of the step on one side of the side wall to the length of the grid is 0.01-0.5. Thereby, a good tuning of the drain side energy band can be achieved, while the transconductance of the transistor is not significantly reduced.
According to the embodiment of the invention, the side wall is formed by an insulating medium material. Therefore, the source and drain electrodes can be insulated from the grid electrode.
According to an embodiment of the invention, the sidewall is formed of a high-K dielectric material, and the high-K dielectric material includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, and lanthanum oxide. Therefore, the equivalent gate dielectric thickness of the region where the step is located can be increased, the gate control capability of the gate to the channel region below the step is reduced, and the excessive bending of the energy band at the drain side is further relieved.
According to the embodiment of the invention, the side wall is formed by a low-K dielectric material, and the low-K dielectric material comprises at least one of silicon oxide, silicon nitride and silicon oxynitride. Namely, the step part of the side wall is also made of low-K dielectric materials, so that the equivalent gate dielectric thickness of the region where the step is located can be further increased, the gate control capability of the gate to a channel region below the step is reduced, the excessive bending of an energy band on the drain electrode side is further relieved, and the parasitic capacitance between the source electrode and the drain electrode and the gate electrode can be reduced by the side wall.
According to the embodiment of the invention, the step of the side wall has fixed charges or dipoles, or the interface between the step of the side wall and the gate dielectric layer has dipoles. Therefore, the channel region below the step can be subjected to electrostatic regulation through fixed charges or dipoles so as to regulate the energy band, and the excessive bending of the energy band on the drain side is further relieved.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 shows a schematic diagram of a transistor according to an embodiment of the present invention;
FIG. 2 shows a schematic energy band diagram of a conventional transistor in an off state;
FIG. 3 shows a schematic energy band diagram of a transistor in an off state according to one embodiment of the invention;
FIG. 4 shows a schematic flow diagram of a method of fabricating a transistor according to one embodiment of the invention;
FIG. 5 shows a partial flow diagram of a method of fabricating a transistor according to one embodiment of the invention;
FIG. 6 shows a partial flow diagram of a method of fabricating a transistor according to one embodiment of the invention;
FIG. 7 is a schematic partial flow chart diagram illustrating a method of fabricating a transistor according to another embodiment of the present invention;
FIG. 8 shows a partial flow diagram of a method of fabricating a transistor according to another embodiment of the invention;
fig. 9 shows a schematic view of the structure of the transistor in comparative example 1;
FIG. 10 is a graph showing the transfer characteristics of the transistor in example 1;
fig. 11 shows a transfer characteristic curve of the transistor in comparative example 1.
Description of the reference numerals:
100: a substrate; 200: a layer of narrow bandgap material; 300: a drain electrode; 400: a source electrode; 500: a side wall; 510: a side wall material layer; 600: a gate dielectric layer; 610: a first sublayer; 620: a second sublayer; 700: a gate electrode; 810: a layer of protective material; 10: a step; 30: a first adhesive layer; 40: and a second adhesive layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In one aspect of the invention, a transistor is provided. According to an embodiment of the present invention, referring to fig. 1, the transistor includes: the transistor comprises a substrate 100, a narrow bandgap material layer 200, a drain 300, a source 400, a sidewall spacer 500, a gate dielectric layer 600 and a gate 700, wherein the narrow bandgap material layer 200 is disposed on the substrate 100, the narrow bandgap material layer 200 has a channel region, the source 400 and the drain 300 are located on a side of the narrow bandgap material layer 200 away from the substrate 100, both the source 400 and the drain 300 are in contact with the narrow bandgap material layer 200, the sidewall spacer 500 covers a sidewall of the drain 300 and a sidewall of the source 400 and extends into the channel region to form a step 10, the sidewall spacer 500 has the step 10 at least on a side close to the drain 300, the gate dielectric layer 600 covers the step 10 and the narrow bandgap material layer 200 located between the source 400 and the drain 300, and the gate 700 covers the gate dielectric layer 600. When the transistor is in a conducting state, the energy band change of the drain electrode side is relatively smooth, the great acceleration of current carriers caused by the excessive bending of the energy band is relieved, the impact of the current carriers on a grid dielectric layer, a substrate and a drain electrode on the drain electrode side is reduced, the heat migration of the drain electrode and the damage to the grid dielectric layer and the substrate are reduced, the structure of the transistor is more reliable, the service life is prolonged, the Schottky barrier on the drain electrode side becomes thicker when the transistor is in a turn-off state, the reverse tunneling of the current carriers is relieved, the off-state leakage current is effectively reduced, and the power consumption of the transistor is reduced.
According to the embodiment of the invention, in the transistor, the side wall at the drain electrode side is provided with the step extending into the channel region, so that the equivalent gate dielectric thickness of the region where the step is located is increased, the gate control capability of the gate on the channel region below the step can be reduced, the adjustment of the energy band at the drain electrode side can be realized, when the transistor is in a conducting state, the great acceleration of a current carrier caused by the excessive bending of the energy band can be relieved, the impact of the current carrier on the drain electrode, the gate dielectric layer at the drain electrode side and the substrate can be reduced, the thermal migration of the drain electrode and the damage to the charge injection and the like of the gate dielectric layer at the drain electrode side and the substrate can be reduced, the structure of the transistor is more reliable, and the service life of the transistor can be prolonged; when the transistor is in an off state, the change of an energy band at the drain electrode side is relatively smooth (refer to a part in a dotted coil in fig. 3), the schottky barrier at the drain electrode side becomes thick, reverse tunneling of carriers is relieved, off-state leakage current is effectively reduced, and power consumption of the transistor is reduced.
According to the embodiment of the present invention, in the transistor, only the sidewall on the drain 300 side may have the step 10 extending into the channel region, or the sidewall on the source 400 side may have the step 10 extending into the channel region while the sidewall on the drain 300 side has the step 10 extending into the channel region. Therefore, the transistor has a symmetrical structure, keeps high performance in an on state and is convenient for subsequent circuit design.
The following describes in detail the respective structures of the transistor according to specific embodiments of the present invention:
according to the embodiment of the present invention, the length (L shown in fig. 1) of the step 10 at one side of the sidewall 5001) And the length of gate 700 (L as shown in fig. 1)2) The ratio may be 0.01-0.5, such as 0.01, 0.05, 0.1, 0.3, 0.5. The inventor finds that when the length of the step satisfies the above condition, good adjustment of the energy band on the drain side can be achieved, the excessive bending of the energy band can be effectively relieved, and the length of the step is not too long so as to remarkably reduce the transconductance of the transistor. Note that, when the source side spacer also has a step extending into the channel region, the ratio of the length of the step of the source side spacer to the length of the gate is also 0.01 to 0.5.
According to embodiments of the present invention, the material forming the layer of narrow bandgap material 200 may comprise at least one of carbon nanotubes, nanowires, two-dimensional materials. The carbon nanotube can be a single carbon nanotube, a network carbon nanotube array or an oriented carbon nanotube array. The two-dimensional material may comprise a layered low-dimensional material such as black phosphorus or molybdenum disulfide. Therefore, the transistor has excellent performance by using the material as a channel material of the transistor. According to the preferred embodiment of the invention, the material constituting the narrow bandgap material layer can be single-walled carbon nanotubes, which have higher mobility and fewer surface dangling bonds compared with other narrow bandgap material materials, so that the transistor has better performance.
According to an embodiment of the present invention, the sidewall spacers 500 may be formed of an insulating dielectric material. Therefore, the source and drain electrodes can be insulated from the gate electrode.
According to the embodiment of the present invention, the sidewall spacers 500 may be formed of a high-K dielectric material or a low-K dielectric material. The specific composition of the high-K dielectric material and the low-K dielectric material for forming the sidewall is not particularly limited, for example, the high-K dielectric material for forming the sidewall may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, and lanthanum oxide, and the low-K dielectric material for forming the sidewall may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Therefore, the equivalent gate dielectric thickness of the region where the step is located can be increased, the gate control capability of the gate to the channel region below the step is reduced, and the excessive bending of the energy band at the drain side is further relieved. According to the preferred embodiment of the present invention, the side wall 500 is formed of a low-K dielectric material, the dielectric constant of the low-K dielectric material is small, and when the side wall 500 is formed of the low-K dielectric material, the step portion of the side wall is also formed of the low-K dielectric material, which can further increase the equivalent gate dielectric thickness of the region where the step is located, so as to reduce the gate control capability of the gate to the channel region below the step, further relieve the excessive bending of the drain side energy band, and reduce the parasitic capacitance between the source and drain and the gate.
According to the embodiment of the present invention, the step 10 of the sidewall 500 may have a fixed charge or dipole, or the interface between the step 10 of the sidewall 500 and the gate dielectric layer 600 may have a dipole. Therefore, the channel region below the step can be electrostatically regulated through fixed charges or dipoles so as to adjust the energy band, and the excessive bending of the energy band at the drain side is further relieved. The step portion of the side wall has fixed charges, and specifically, the step portion of the side wall may be made of a material having fixed charges, or all regions of the side wall are made of a material having fixed charges, so that the preparation is facilitated. For example, the material forming the sidewall has a fixed charge by adjusting the process parameters. The side wall is provided with a step portion, the step portion is formed by two materials, or the whole area of the side wall is formed by two materials, the step portion is formed by two materials, and the step portion is convenient to prepare. For example, a first sidewall material and a second sidewall material are deposited (e.g., atomic layer deposition) sequentially, and a dipole is formed at an interface of the first sidewall material and the second sidewall material. The specific materials of the first side wall material and the second side wall material can be adjusted, so that dipoles are arranged in the step parts of the side walls. Or, a dipole is formed at the interface of the step part of the side wall and the gate dielectric layer by adjusting the material of the step part of the side wall and the material of the gate dielectric layer. The transistor can be a P-type transistor and can also be an N-type transistor, a channel region under the step in the P-type transistor can be subjected to hole doping through fixed charges or dipoles, and a channel region under the step in the N-type transistor can be subjected to electron doping through the fixed charges or dipoles.
The specific composition, structure or form of the aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide or lanthanum oxide forming the sidewall is not particularly limited, and a composition, structure or form having a fixed charge or dipole or capable of forming a dipole with the interface of the gate dielectric layer is preferable.
In the crystal described above, the gate dielectric layer 600 is formed of a high-K dielectric material including a metal oxide, which may be doped with silicon or nitrogen, according to an embodiment of the present invention. The specific composition of the high-K dielectric material for forming the gate dielectric layer is not particularly limited, e.g., forming the gate dielectricThe high-K dielectric material of the layer may comprise Al2O3、HfO2、ZrO2、TiO2、HfOxNy、LaOxNy、Y2O3、La2O3At least one of (1). Therefore, the transistor can have good grid control, and on the basis of ensuring that the transistor has good grid control, the energy band can be adjusted by using the structure, so that the excessive bending of the energy band is relieved.
According to an embodiment of the present invention, referring to fig. 1, the sidewall spacers 500 further cover the surfaces of the source electrode 400 and the drain electrode 300 on the side away from the substrate 100. Therefore, the source and the drain can be isolated from the air, passivation protection of the source and the drain is realized, and the side wall which covers the side wall and the surface of the source and the drain and extends to the channel region can be synchronously formed through the self-alignment process.
According to an embodiment of the present invention, the source electrode 400 and the drain electrode 300 may be formed of a metal material, and the specific metal material for forming the source electrode and the drain electrode is not particularly limited, and for example, palladium (Pd) or scandium (Sc) may be used to form the source electrode and the drain electrode to form a P-type or N-type ohmic contact with the narrow bandgap material layer.
The specific composition and material of the substrate are not particularly limited, and those skilled in the art can design according to a substrate commonly used in a transistor. For example, the base 100 may include a silicon substrate and a silicon oxide layer, glass, polymer, and other insulating bases disposed on the silicon substrate.
In another aspect of the invention, a method of fabricating a transistor is provided. According to an embodiment of the present invention, the transistor fabricated by the method may be the transistor described above, and thus, the transistor fabricated by the method has the same features and advantages as the transistor described above, and will not be described herein again.
According to an embodiment of the invention, referring to fig. 4, the method comprises:
s100: forming a layer of narrow bandgap material on a substrate, the layer of narrow bandgap material having a channel region
In this step, a layer of narrow bandgap material is formed on the substrate, the layer of narrow bandgap material having a channel region. The materials for the substrate, the narrow bandgap material layer, have been described in detail above and will not be described further herein.
The formation of the narrow bandgap material layer is not particularly limited, and for example, the narrow bandgap material layer may be formed by physical transfer or solution deposition.
S200: forming a source electrode, a drain electrode and a side wall on one side of the narrow band gap material layer far away from the substrate
In this step, source, drain and sidewall spacers are formed on the narrow bandgap material layer on a side away from the substrate.
According to the embodiment of the invention, the source electrode and the drain electrode are both contacted with the narrow band gap material layer, the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form the step, and the side wall at least has the step at one side close to the drain electrode. Therefore, the thickness of the equivalent gate dielectric in the region where the step of the side wall of the drain electrode side is located is increased, the gate control capability of the gate to a channel region below the step can be reduced, the energy band of the drain electrode side can be adjusted, when the transistor is in a conducting state, the great acceleration of current carriers caused by the excessive bending of the energy band can be relieved, the impact of the current carriers on the drain electrode, the gate dielectric layer and the substrate on the drain electrode side can be reduced, the thermal migration of the drain electrode and the damage to the charge injection and the like of the gate dielectric layer and the substrate on the drain electrode side can be reduced, the structure of the transistor is more reliable, and the service life of the transistor can be prolonged; when the transistor is in a turn-off state, the change of an energy band at the drain electrode side is smooth, the Schottky barrier at the drain electrode side becomes thick, the reverse tunneling of current carriers is relieved, the off-state leakage current is effectively reduced, and the power consumption of the transistor is reduced.
According to an embodiment of the present invention, referring to fig. 5 and 6, forming the source, the drain, and the sidewall spacers may include:
first, a first glue layer 30 and a second glue layer 40 are deposited in sequence on the side of the narrow bandgap material layer 200 remote from the substrate 100 (see (a) in fig. 5).
Subsequently, the second adhesive layer 40 and the first adhesive layer 30 are exposed and developed to expose a portion of the narrow bandgap material layer 200, and the length of the opening in the first adhesive layer 30 is made larger than the length of the opening in the second adhesive layer 40 in the direction in which the first adhesive layer extends (refer to (b) in fig. 5). The specific materials and formation manners of the first adhesive layer and the second adhesive layer are not particularly limited, as long as the length of the opening in the first adhesive layer is greater than the length of the opening in the second adhesive layer. For example, the second adhesive layer may be changed by light, the first adhesive layer may be substantially unchanged by light, first, the property of the second adhesive layer is changed by exposure, and is developed by a corresponding developing solution to form an opening in the second adhesive layer, then, the developing solution directly reacting with the first adhesive layer is selected for development to form an opening in the first adhesive layer, and the length of the opening in the first adhesive layer is made greater than the length of the opening in the second adhesive layer. Or the first adhesive layer and the second adhesive layer are changed under the action of illumination, and different developing solutions are respectively adopted for developing, so that the length of the opening in the first adhesive layer is larger than that of the opening in the second adhesive layer. Or the first adhesive layer and the second adhesive layer are changed under the action of light, the same developing solution is adopted for developing, the developing time of the first adhesive layer and the second adhesive layer is controlled, and the length of the opening in the first adhesive layer is larger than that of the opening in the second adhesive layer. Or, electron beam lithography is adopted, and the first adhesive layer is made of a material which is more sensitive to the electron beam lithography, so that the length of the opening in the first adhesive layer is larger than that of the opening in the second adhesive layer.
Subsequently, the source electrode 400 and the drain electrode 300 are respectively formed on the exposed portions of the narrow bandgap material layer 200, the orthographic projections of the source electrode 400 and the drain electrode 600 on the substrate 100 are respectively located within the orthographic projection range of the opening in the second glue layer 40 on the substrate 100, and in the extending direction of the second glue layer 40, the lengths of the source electrode 400 and the drain electrode 300 are respectively consistent with the length of the opening in the second glue layer 40, and the height of the first glue layer 30 is greater than the heights of the source electrode 400 and the drain electrode 300 (refer to (c) in fig. 5, since the source electrode and the drain electrode are simultaneously formed, fig. 5 (c) only shows a schematic diagram of forming the drain electrode). The source and drain electrodes may be formed by e-beam evaporation or magnetic sputtering, which is highly collimated to facilitate the formation of the source and drain electrodes, respectively, on the exposed portions of the narrow bandgap material layer. Orthographic projections of the source electrode and the drain electrode on the substrate are respectively located in orthographic projection ranges of the opening of the second adhesive layer on the substrate, the length of the source electrode and the length of the drain electrode are respectively consistent with the length of the opening of the second adhesive layer, and the height of the first adhesive layer is larger than the height of the source electrode and the height of the drain electrode, so that enough space can be reserved for forming a subsequent side wall. Specific dimensions regarding the opening of the first rubber layer and the opening of the second rubber layer are not particularly limited as long as they are suitable for forming a step of a desired length.
Subsequently, a sidewall spacer material layer 510 is deposited along the surface and sidewall of the second glue layer 40, the sidewall of the first glue layer 30, the surface of the narrow bandgap material layer 200, the sidewall and surface of the source 400, and the sidewall and surface of the drain 300, and the sidewall spacer material layer 510 covers the portion of the sidewall of the first glue layer 30, and there is a gap between the portion of the sidewall spacer material layer 510 covering the sidewall of the source 400 and the portion of the sidewall of the drain 300, respectively (refer to (d) in fig. 6, since the source and the drain are formed simultaneously, fig. 6 (d) only shows a schematic diagram of forming the drain). The side wall material layer can be formed by adopting atomic layer deposition.
Finally, the first adhesive layer 30 and the second adhesive layer 40 are peeled off to form a sidewall 500, and the step 10 is formed in the portion of the sidewall 500 located in the gap and located in the channel region (see (e) in fig. 6). Therefore, the side wall which covers the source and drain electrodes and extends towards the channel region can be synchronously formed by adopting a self-alignment process, the process steps are simplified, the process cost is reduced, the extending part of the side wall forms a step, the equivalent gate dielectric thickness of the region where the step is located is increased, the gate control capability of the grid electrode on the channel region below the step is reduced, the excessive bending of the energy band of the drain electrode side is relieved, the side wall can realize the insulation between the source and drain electrodes and the grid electrode, the source and drain electrodes are isolated from air, the passivation protection of the source and drain electrodes is realized, and the subsequent grid electrode can be formed under the self-alignment process, so that the grid control is good.
According to further embodiments of the present invention, referring to fig. 7 and 8, forming the source, the drain, and the sidewall spacers may include:
first, a protective material layer 810 is deposited on the side of the narrow bandgap material layer 200 remote from the substrate 100 (see (a) in fig. 7). The material forming the protective material layer is not particularly limited as long as patterning can be performed by non-destructive etching (such as wet etching or vapor etching), and for example, according to an embodiment of the present invention, the material forming the protective material layer may include at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. From this, when exposing first glue film, second glue film, developing, the protective material layer can protect the narrow band gap material layer to avoid damage and pollution to when carrying out chemical etching to the protective material layer that is formed by above-mentioned material, can not destroy the lattice structure of narrow band gap material, not only can not cause damage and pollution to the narrow band gap material layer, can also get rid of narrow band gap material layer surface adsorption's impurity and molecule etc. make the performance of narrow band gap material layer obtain better performance.
The formation method of the protective material layer is not particularly limited, and for example, the protective material layer may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), spin coating, or the like. When the protective material layer is formed of silicon oxide, the silicon oxide can be formed on the narrow bandgap material layer by spin coating, which is simple to operate, or the silicon oxide can be formed on the narrow bandgap material layer by thermal deposition, and the performance of the narrow bandgap material layer is not affected.
Subsequently, the first glue layer 30 and the second glue layer 40 are sequentially deposited on the side of the protective material layer 810 away from the substrate 100, the second glue layer 40 and the first glue layer 30 are exposed and developed, so as to expose a portion of the protective material layer 810, the length of the opening in the first glue layer 30 is made larger than that of the opening in the second glue layer 40, and the exposed portion of the protective material layer 810 is removed, so as to expose a portion of the narrow bandgap material layer 200 (refer to (b) in fig. 7).
According to an embodiment of the present invention, removing a portion of the protective material layer may include: the protective material layer is chemically etched using a reaction solution or a reaction gas, and is cleaned with water. Thus, the lattice structure of the narrow bandgap material is not destroyed and the narrow bandgap material layer is not damaged or contaminated when the protective material layer is chemically etched.
According to an embodiment of the present invention, the reaction solution may include an acidic solution or a basic solution. From this, react with the protective material layer through acid solution or alkaline solution, can realize the patterning to the protective material layer, and the process of acid solution or alkaline solution and protective material layer reaction can not destroy the lattice structure of narrow band gap material, can not cause damage and pollution to the narrow band gap material layer.
Specific components regarding the acidic solution and the alkaline solution are not particularly limited, and for example, the acidic solution may include at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid. The alkaline solution may include at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. Therefore, the acid solution or the alkaline solution can be utilized to react with the protective material layer to remove part of the protective material layer, the lattice structure of the narrow-bandgap material cannot be damaged, and the narrow-bandgap material layer cannot be damaged and polluted. For example, the acidic solution is hydrochloric acid, and the protective material layer is an yttrium oxide layer, the hydrochloric acid can react with the yttrium oxide to form liquid yttrium chloride, and excess hydrochloric acid and yttrium chloride can be washed away with water, so as to implement patterning of the protective material layer. The hydrochloric acid can well clean the surface of the narrow band gap material layer without damaging the property of the narrow band gap material layer, and takes away impurities introduced in the process, so that the exposed narrow band gap material layer has a good surface, and a foundation is laid for subsequent deposition of a side wall to form good electrostatic regulation and control. When the protective material layer is formed of aluminum oxide, the protective material layer may be chemically etched using phosphoric acid, and when the protective material layer is formed of silicon oxide, the protective material layer may be chemically etched using potassium hydroxide without destroying the lattice structure of the narrow bandgap material layer.
The specific composition of the reaction gas is not particularly limited, and for example, the reaction gas may include at least one of hydrogen chloride and hydrogen fluoride. Thus, the reactive gas may react with the protective material layer to remove portions of the protective material layer without destroying the lattice structure of the narrow bandgap material.
Subsequently, the source electrode 400 and the drain electrode 300 are respectively formed on the exposed portions of the narrow bandgap material layer 200, the orthographic projections of the source electrode 400 and the drain electrode 600 on the substrate 100 are respectively located within the orthographic projection range of the opening in the second glue layer 40 on the substrate 100, and in the extending direction of the second glue layer 40, the lengths of the source electrode 400 and the drain electrode 300 are respectively consistent with the length of the opening in the second glue layer 40, and the height of the first glue layer 30 is greater than the heights of the source electrode 400 and the drain electrode 300 (refer to (c) in fig. 7, since the source electrode and the drain electrode are simultaneously formed, fig. 7 (c) only shows a schematic diagram of forming the drain electrode).
Subsequently, a sidewall spacer material layer 510 is deposited along the surface and sidewall of the second glue layer 40, the sidewall of the first glue layer 30, the sidewall of the protection material layer 810, the surface of the narrow bandgap material layer 200, the sidewall and surface of the source 400, and the sidewall and surface of the drain 300, and the sidewall spacer material layer 510 covers the portion of the sidewall of the first glue layer 30, and there is a gap between the portion of the sidewall spacer material layer 510 covering the sidewall of the source 400 and the portion of the sidewall of the drain 300, respectively (refer to (d) in fig. 8, since the source and the drain are formed simultaneously, therefore, (d) in fig. 8 only shows a schematic diagram of forming the drain).
Finally, the first glue layer 30 and the second glue layer 40 are peeled off to form the sidewall 500, and the step 10 is formed at the part of the sidewall 500, which is located in the gap and located in the channel region (refer to (e) in fig. 8). Therefore, the side wall which covers the source and drain electrodes and extends towards the channel region can be synchronously formed by adopting a self-alignment process, the process steps are simplified, the process cost is reduced, the extending part of the side wall forms a step, the equivalent gate dielectric thickness of the region where the step is located is increased, the gate control capability of the grid electrode on the channel region below the step is reduced, the excessive bending of the energy band of the drain electrode side is relieved, the side wall can realize the insulation between the source and drain electrodes and the grid electrode, the source and drain electrodes are isolated from air, the passivation protection of the source and drain electrodes is realized, and the subsequent grid electrode can be formed under the self-alignment process, so that the grid control is good. It should be noted that, the thickness relationship between the protection material layer and the sidewall spacer material layer is not particularly limited, for example, the thickness of the protection material layer may be smaller than the thickness of the sidewall spacer material layer, or the thickness of the protection material layer may be equal to the thickness of the sidewall spacer material layer, or the thickness of the protection material layer may be greater than the thickness of the sidewall spacer material layer. As is well known to those skilled in the art, the thickness of the sidewall is generally thin, so that when the first adhesive layer and the second adhesive layer are peeled off, under the peeling action, the portion of the sidewall material layer extending from the sidewall of the first adhesive layer to the surface of the narrow bandgap material layer is simultaneously peeled off, and the portion of the sidewall material layer remaining in the gap and located in the channel region forms a step.
The constituent materials of the source and drain electrodes have been described in detail above, and are not described in detail here.
According to the embodiment of the invention, the side wall can be formed by an insulating medium material. Therefore, the source and drain electrodes can be insulated from the gate electrode. According to the embodiment of the invention, the side wall can be formed by a high-K dielectric material or a low-K dielectric material. The specific composition of the high-K dielectric material and the low-K dielectric material for forming the sidewall is not particularly limited, for example, the high-K dielectric material for forming the sidewall may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, and lanthanum oxide, and the low-K dielectric material for forming the sidewall may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Therefore, the equivalent gate dielectric thickness of the region where the step is located can be increased, the gate control capability of the gate to the channel region below the step is reduced, and the excessive bending of the drain side energy band is further relieved. According to the preferred embodiment of the invention, the side wall is made of the low-K dielectric material, the dielectric constant of the low-K dielectric material is smaller, when the side wall is made of the low-K dielectric material, the step part of the side wall is also made of the low-K dielectric material, the equivalent gate dielectric thickness of the region where the step is located can be further increased, the gate control capability of the gate to a channel region below the step is reduced, the excessive bending of an energy band at the side of the drain electrode is further relieved, and the parasitic capacitance between the source electrode and the drain electrode and the gate electrode can be reduced by the side wall.
According to the embodiment of the invention, when the side wall is formed by the high-K dielectric material, the high-K dielectric material can be deposited by adopting a thermal atomic layer deposition mode, and when the side wall is formed by the low-K dielectric material, the low-K dielectric material can be deposited by adopting an atomic layer deposition mode.
According to the embodiment of the invention, the step of the side wall can have fixed charges or dipoles, or the interface between the step of the side wall and the gate dielectric layer has dipoles. Therefore, the channel region below the step can be electrostatically regulated through fixed charges or dipoles so as to adjust the energy band, and the excessive bending of the energy band at the drain side is further relieved. The step portion of the side wall has fixed charges, and specifically, the step portion of the side wall may be made of a material having fixed charges, or all regions of the side wall are made of a material having fixed charges, so that the preparation is facilitated. The side wall is provided with a side wall, and the side wall is provided with a plurality of side walls, wherein the side wall is provided with a plurality of side walls, the side walls are made of two materials, the side walls are formed with dipoles at interfaces, or all areas of the side walls are made of two materials, and the dipoles are formed at the interfaces of the two materials, so that the preparation is convenient. For example, a first sidewall material and a second sidewall material are deposited (e.g., atomic layer deposition) sequentially, and a dipole is formed at an interface of the first sidewall material and the second sidewall material. The specific materials of the first side wall material and the second side wall material can be adjusted, so that dipoles are arranged in the step portions of the side walls. Or, a dipole is formed at the interface of the step part of the side wall and the gate dielectric layer by adjusting the material of the step part of the side wall and the material of the gate dielectric layer.
According to the embodiment of the invention, the ratio of the length of the step at one side of the side wall to the length of the gate can be 0.01-0.5. Thereby, a good tuning of the drain side energy band can be achieved, while the transconductance of the transistor is not significantly reduced.
S300: forming a gate dielectric layer
In this step, a gate dielectric layer is formed.
According to an embodiment of the present invention, a gate dielectric layer 600 covers the step 10 and the narrow bandgap material layer 200 between the source 400 and drain 300 (see (f) in fig. 6). The constituent materials of the gate dielectric layer have been described in detail above, and are not described again.
According to an embodiment of the present invention, referring to (f) in fig. 6, after the first glue layer and the second glue layer are stripped, a gate dielectric layer 600 is formed on the side of the step away from the substrate 100 and the portion of the narrow bandgap material layer 200 located between the source electrode 400 and the drain electrode 300 and not covered by the sidewall spacers 500. The gate dielectric layer may be formed using atomic layer deposition.
Alternatively, in accordance with further embodiments of the present invention, after stripping the first glue layer and the second glue layer, the portion of the protection material layer 810 between the source electrode 400 and the drain electrode 300 is removed to expose a portion of the narrow bandgap material layer 200, and a gate dielectric layer 600 is formed on the side of the step away from the substrate 100 and the portion of the narrow bandgap material layer 200 exposed (refer to (f) in fig. 6). Therefore, impurities, molecules and the like adsorbed on the surface of the narrow band gap material layer in the channel region can be removed, the performance of the narrow band gap material layer is better exerted, and the material selection range of the gate dielectric layer can be larger.
Alternatively, according to other embodiments of the present invention, referring to (f) in fig. 8, the gate dielectric layer includes a first sub-layer 610 and a second sub-layer 620, the first sub-layer 610 is a portion of the protective material layer 810 between the source electrode 400 and the drain electrode 300, and after the first glue layer and the second glue layer are stripped, the second sub-layer 620 is formed on the step and a side of the first sub-layer 610 away from the substrate 100. Therefore, when the first adhesive layer and the second adhesive layer are exposed and developed, the protective material layer can protect the narrow bandgap material layer from being damaged and polluted, and the part of the protective material layer, which is positioned between the source electrode and the drain electrode, can be used as a part of the gate dielectric layer. In this embodiment, the material constituting the first sublayer may include yttria, lanthana, and alumina.
It should be noted that, because the thickness of the side wall is relatively thin, when the first glue layer and the second glue layer are stripped, the part of the side wall material layer extending from the side wall of the first glue layer to the surface of the narrow bandgap material layer is also stripped off simultaneously, so that a certain gap is usually left between the step of the side wall and the first sub-layer (refer to (e) in fig. 8), and when the second sub-layer is formed, a part of the second sub-layer fills the gap (refer to (f) in fig. 8). According to the embodiment of the invention, the process of removing the protective material layer between the source and the drain and then depositing the high-K dielectric material again to form the gate dielectric layer is preferred, so that the excessive bending of the energy band at the drain side is obviously relieved.
S400: forming a gate electrode
In this step, a gate electrode is formed.
The formation method of the gate electrode is not particularly limited, and for example, the gate electrode may be formed by electron beam evaporation plating or magnetic sputtering.
In conclusion, when the transistor obtained by the method is in a conducting state, the energy band change of the drain electrode side is relatively smooth, the great acceleration of a current carrier caused by the excessive bending of the energy band is relieved, the impact of the current carrier on the drain electrode, the gate dielectric layer on the drain electrode side and the substrate is reduced, the thermal migration of the drain electrode and the damage to the charge injection and the like of the gate dielectric layer on the drain electrode side and the substrate are reduced, the structure of the transistor is more reliable, and the service life is prolonged; when the transistor obtained by the method is in a turn-off state, the Schottky barrier on the drain side becomes thick, reverse tunneling of carriers is relieved, off-state leakage current is effectively reduced, and power consumption of the transistor is reduced.
The following description will be given with reference to specific examples.
Example 1
Referring to fig. 1, the transistor includes a substrate 100, a narrow bandgap material layer 200, a source 400, a drain 300, a sidewall 500, a gate dielectric layer 600 and a gate 700, the narrow bandgap material layer 200 has a channel region, the sidewall 500 covers a surface and a sidewall of the drain 300 and extends into the channel region to form a step, the sidewall 500 covers a surface and a sidewall of the source 400 and extends into the channel region to form a step, the sidewall 500 is formed of hafnium oxide, the gate dielectric layer 300 is formed of yttrium oxide and hafnium oxide, and the narrow bandgap material layer 200 is a carbon nanotube.
The source 400 and the drain 300 are formed of Pd to constitute a P-type transistor (PMOS). The source 400 and the drain 300 are formed of Sc, and constitute an N-type transistor (NMOS).
Comparative example 1
Referring to fig. 9, a transistor includes a substrate 100, a narrow bandgap material layer 200 disposed on the substrate 100, a source 400 and a drain 300 disposed on a side of the narrow bandgap material layer 200 away from the substrate 100, a gate dielectric layer 600 covering a portion of the source 400, the narrow bandgap material layer 200 between the source 400 and the drain 300, and a portion of the drain 300, a gate 700 covering the gate dielectric layer 600, the gate dielectric layer 600 being formed of HfO2The narrow bandgap material layer 200 is formed of carbon nanotubes.
The source 400 and the drain 300 are formed of Pd to constitute a P-type transistor (PMOS). The source 400 and the drain 300 are formed of Sc, and constitute an N-type transistor (NMOS).
The manufacturing process of the transistor is as follows:
first, carbon nanotubes are formed on a substrate. And then, forming a polymethyl methacrylate (PMMA) layer on one side of the carbon nano tube, which is far away from the substrate, and patterning the PMMA layer to form grooves arranged at intervals. And then depositing source and drain metal in the groove, patterning the source and drain metal, respectively forming a source electrode and a drain electrode in the groove, and removing the PMMA layer. And then, respectively forming a PMMA structure on one side of the source electrode far away from the drain electrode and one side of the drain electrode far away from the source electrode, wherein the PMMA structure on the source electrode side covers a part of the source electrode, and the PMMA structure on the drain electrode side covers a part of the drain electrode. And depositing HfO on the PMMA structure and the side of the source electrode, the drain electrode and the carbon nano tube far away from the substrate2Forming a continuous gate dielectric material layer on the HfO2And depositing the grid metal on the side far away from the substrate. Finally, the PMMA structure is removed, and HfO positioned at the side wall of the PMMA structure is synchronously removed when the PMMA structure is removed2To form a transistor.
The transistors of example 1 and comparative example 1 were subjected to performance tests, respectively, to obtain transfer characteristic curves (refer to fig. 10 and fig. 11) of the transistors, which characterize the switching characteristics of the transistors under the gate voltage. Fig. 10 is a transfer characteristic curve of the transistor of example 1, and fig. 11 is a transfer characteristic curve of the transistor of comparative example 1.
As can be seen from fig. 10 and 11, the off-state current of the carbon nanotube transistor of example 1 is significantly reduced, and the carbon nanotube transistor has a higher on-off ratio and a more suitable threshold voltage, compared to the conventional high-k gate dielectric self-aligned carbon nanotube transistor (i.e., the transistor of comparative example 1).
In fig. 10 and 11, Ids is a current between the source and the drain, Vds is a voltage between the source and the drain, Vgs is a voltage between the gate and the source, and L/W is a ratio of the gate length to the channel width.
In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, which are merely for convenience of describing the present invention and do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent. In addition, it should be noted that the terms "first" and "second" in this specification are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of indicated technical features is high.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (19)
1. A transistor, comprising:
a substrate and a layer of narrow bandgap material disposed on the substrate, the layer of narrow bandgap material having a channel region;
a source and a drain on a side of the narrow bandgap material layer remote from the substrate, the source and drain both in contact with the narrow bandgap material layer;
the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form a step, and the step is arranged on at least one side of the side wall close to the drain electrode;
all the side walls or the step parts are made of a first side wall material and a second side wall material, and dipoles are arranged at the interfaces of the first side wall material and the second side wall material;
a gate dielectric layer covering the step and the narrow bandgap material layer between the source and the drain;
and the grid electrode covers the grid medium layer.
2. The transistor according to claim 1, wherein a ratio of a length of the step on the side of the sidewall to a length of the gate is 0.01 to 0.5.
3. The transistor of claim 1 wherein the material forming said layer of narrow bandgap material comprises at least one of carbon nanotubes, nanowires, two dimensional materials.
4. The transistor of claim 1, wherein the gate dielectric layer is formed of a high-K dielectric material comprising Al2O3、HfO2、ZrO2、TiO2、HfOxNy、 LaOxNy、Y2O3、La2O3At least one of (1).
5. The transistor of claim 1, wherein the sidewall spacers are formed of an insulating dielectric material.
6. The transistor of claim 5, wherein the first sidewall material or the second sidewall material is formed of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, lanthanum oxide.
7. The transistor of claim 5, wherein the sidewall spacers are formed of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride.
8. The transistor of claim 1, wherein the spacers further cover surfaces of the source and drain electrodes on a side away from the substrate.
9. The transistor of claim 1, wherein the step of the sidewall has a fixed charge or dipole, or wherein an interface of the step of the sidewall and the gate dielectric layer has a dipole.
10. A method of fabricating a transistor, comprising:
forming a layer of narrow bandgap material on a substrate, the layer of narrow bandgap material having a channel region;
forming a source and a drain on a side of the narrow bandgap material layer remote from the substrate, the source and drain both being in contact with the narrow bandgap material layer;
sequentially depositing a first side wall material and a second side wall material to form a side wall, wherein a dipole is arranged at the interface of the first side wall material and the second side wall material; the side wall covers the side wall of the drain electrode and the side wall of the source electrode and extends into the channel region to form a step, and the step is arranged on at least one side of the side wall close to the drain electrode;
forming a gate dielectric layer covering the step and the narrow bandgap material layer between the source and the drain;
and forming a grid electrode, wherein the grid electrode covers the grid dielectric layer.
11. The method of claim 10, wherein forming the source, the drain and the sidewalls comprises:
sequentially depositing a first glue layer and a second glue layer on one side of the narrow bandgap material layer away from the substrate;
exposing and developing the second adhesive layer and the first adhesive layer to expose a part of the narrow bandgap material layer, and enabling the length of the opening in the first adhesive layer to be larger than that of the opening in the second adhesive layer in the extending direction of the first adhesive layer;
forming the source electrode and the drain electrode on the exposed part of the narrow bandgap material layer respectively, wherein orthographic projections of the source electrode and the drain electrode on the substrate are respectively located in the orthographic projection range of the opening in the second glue layer on the substrate, and in the extending direction of the second glue layer, the lengths of the source electrode and the drain electrode are respectively consistent with the length of the opening in the second glue layer, and the height of the first glue layer is greater than the heights of the source electrode and the drain electrode;
depositing a side wall material layer along the surface and the side wall of the second adhesive layer, the side wall of the first adhesive layer, the surface of the narrow band gap material layer, the side wall and the surface of the source electrode, and the side wall and the surface of the drain electrode, wherein the side wall material layer covers the part of the side wall of the first adhesive layer, and gaps are respectively reserved between the part of the side wall material layer covering the side wall of the source electrode and the part of the side wall material layer covering the side wall of the drain electrode;
and stripping the first adhesive layer and the second adhesive layer to form a side wall, wherein the side wall is positioned in the gap, and the step is formed at the part of the side wall positioned in the channel region.
12. The method of claim 11, further comprising, prior to forming the first glue layer and the second glue layer on the side of the narrow bandgap material layer away from the substrate:
forming a layer of protective material on a side of the layer of narrow bandgap material remote from the substrate; and
and exposing a part of the protective material layer after exposing and developing the second adhesive layer and the first adhesive layer, removing the exposed part of the protective material layer, and exposing a part of the narrow bandgap material layer.
13. The method of claim 12, in which after the stripping of the first glue layer and the second glue layer, a portion of the protective material layer between the source and drain is removed exposing a portion of the narrow bandgap material layer, and the gate dielectric layer is formed on a side of the step away from the substrate and on the exposed portion of the narrow bandgap material layer.
14. The method of claim 13, wherein removing portions of the protective material layer comprises: chemically etching the protective material layer by using a reaction solution or a reaction gas, and cleaning by using water;
the reaction solution comprises an acidic solution or an alkaline solution;
the acidic solution comprises at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid and sulfuric acid;
the alkaline solution comprises at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide;
the reaction gas includes at least one of hydrogen chloride and hydrogen fluoride;
the material forming the protective material layer includes at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide.
15. The method of claim 10, wherein a ratio of a length of the step on the side wall to a length of the gate is 0.01-0.5.
16. The method of claim 10, wherein the sidewalls are formed of an insulating dielectric material.
17. The method of claim 16, wherein the first sidewall material or the second sidewall material is formed of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide, lanthanum oxide.
18. The method of claim 16, wherein the first sidewall material or the second sidewall material is formed of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride.
19. The method of claim 10, wherein the step of the sidewall has a fixed charge or dipole, or wherein an interface of the step of the sidewall and the gate dielectric layer has a dipole.
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