WO2018094619A1

WO2018094619A1 - Tunneling transistor and preparation method therefor

Info

Publication number: WO2018094619A1
Application number: PCT/CN2016/106986
Authority: WO
Inventors: 李伟; 徐慧龙; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2016-11-23
Filing date: 2016-11-23
Publication date: 2018-05-31
Also published as: CN109155333B; CN109155333A

Abstract

A tunneling transistor and a preparation method therefor. The transistor comprises a source, a drain, and a heterojunction. The heterojunction comprises a first conducting material layer and a second conducting material layer that are stacked. One of the two conducting material layers is made of a two-dimensional material, and the other of the two conducting material layers is a material layer prepared by using a two-dimensional or three-dimensional material. The source is electrically connected to the first conducting material layer and is insulated from the second conducting material layer, and the drain is electrically connected to the second conducting material layer and is insulated from the first conducting material layer. In the technical solution, a trench material is a two-dimensional material, and an interface barrier of the heterojunction is small (smaller than 0.3eV), thereby increasing the tunneling probability, and increasing a tunnel current. A local gate structure is used, and the gate just controls a tunneling region of the heterojunction. The forming of the heterojunction is simple, and the heterojunction does not have a fault caused by lattice mismatch, and accordingly, the leakage of a current can be effectively restricted.

Description

Tunneling transistor and preparation method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a tunneling transistor and a method of fabricating the same.

Background technique

As transistor sizes continue to shrink, the leakage current caused by short channel effects continues to increase, making the power consumption of integrated circuits an increasingly important issue. Unlike conventional MOSFETs, TFETs (tunneling transistors) use inter-band tunneling, and their SS can be used at room temperature limits below 60mV/dec, which effectively reduces operating voltage and significantly reduces power consumption.

The existing TFET technology is mainly a homojunction TFET with silicon as a channel material and a heterojunction TFET with a III-V material as a channel. Since the silicon material has a large band gap and is an indirect bandgap semiconductor, the silicon-based TFET can obtain an SS of less than 60 mV/dec, but its on-state current is mostly less than 1 μA/μm, which cannot meet the application requirements. Although the III-V material has a small band gap and a small effective mass, a heterojunction TFET based on a III-V material can obtain a large on-state current, but a heterojunction interface defect due to lattice mismatch. Etc. caused it to fail to obtain SS less than 60mV/dec.

Summary of the invention

Embodiments of the present invention provide a tunneling transistor and a method of fabricating the same to improve the conduction performance of a tunneling transistor.

Embodiments of the present invention provide a tunneling transistor including: a source, a drain, and a heterojunction; wherein the heterojunction includes a stacked first conductive material layer and a second conductive material layer, the first In the conductive material layer and the second conductive material layer, one conductive material layer is a material layer made of a two-dimensional material, and the other conductive material layer is a two-dimensional material or a three-dimensional material material layer; the source and the A first conductive material layer is electrically connected and insulated from the second conductive material layer, and the drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.

In the embodiment of the invention, the channel material is a two-dimensional material with a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current. In addition, two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current. With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.

In a specific arrangement, the tunneling transistor further includes a gate dielectric layer and a gate metal layer, wherein the gate dielectric layer is disposed on the heterojunction, and the gate metal layer is disposed on the On the gate dielectric layer.

In a specific arrangement, the gate dielectric layer covers the second conductive material layer, and the gate dielectric layer partially covers the first conductive material layer, and the gate dielectric layer covers A portion of the first conductive material layer is interposed between the source and the second conductive material layer. That is, the insulation between the source and the second conductive material layer is achieved by the gate dielectric layer.

In the above embodiment, the tunneling transistor further includes a substrate, and the first conductive material layer is a substrate of the tunneling transistor. The use of a two-dimensional material as a substrate simplifies the structure of the tunneling transistor.

In a specific embodiment, the method further includes an insulating layer disposed on the first conductive material layer, and the insulating layer covers a portion of the second conductive material layer, and the drain passes through the insulating layer and the first layer The conductive material layer is insulated.

In another specific embodiment, the method further includes an insulating layer, the first conductive material layer is provided with a groove, the insulating layer is disposed in the groove, and the drain is disposed on the insulating layer And partially covering the second conductive material layer.

In a specific arrangement, the drain portion is covered on the insulating layer, and the edge of the insulating layer is exposed uncovered, thereby ensuring an insulating effect between the first conductive material layer and the drain.

In a specific embodiment, the first conductive material layer and the second conductive material layer are stacked and partially staggered, and the second conductive material layer partially covers the first material layer; the first conductive layer An insulating layer is disposed on the material layer, and the source is insulated from the second conductive material layer by the insulating layer.

In a specific embodiment, further including a substrate, the source, the drain, the first conductive material layer, and the portion of the second conductive material layer and the first conductive material layer not interlaced are disposed on the lining The bottom is insulated from the substrate.

In a specific embodiment, the substrate is provided with an isolation layer, and the source, the drain, the first conductive material layer, and the second conductive material layer and the first conductive material layer are not interlaced portions. Set in the isolation layer.

When a specific material is selected, the two-dimensional material may be tungsten diselenide, tin diselenide or molybdenum telluride; the three-dimensional material may be: indium arsenide or silicon.

The embodiment of the invention further provides a method for fabricating the above tunneling transistor, the method comprising the following steps:

Forming a first conductive material layer;

Forming a second conductive material layer on the first conductive material layer, wherein one of the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material. Material layer

Forming a source, and forming a source electrically connected to the first conductive material layer and insulated from the second conductive material layer;

A drain is formed, and the formed drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.

In the above embodiment, the channel material is a two-dimensional material of a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current. In addition, two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current. With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.

In a specific setting manner, the method further includes:

Forming an insulating layer on the first conductive material layer, and forming an insulating layer covering a portion of the second conductive material layer; when forming a drain, forming a drain on the second conductive material layer and covering the portion Divided into insulation layers.

In a specific setting manner, the method further includes:

Forming a groove on the first conductive material layer, providing an insulating layer in the groove; and forming a second conductive material layer covering a portion of the insulating layer; when forming a drain, forming a drain at the second conductive The material layer is covered with a portion of the insulating layer.

In a specific arrangement, the method further includes forming an insulating layer on the first conductive material layer, and the insulating layer covers a portion of the source.

In a specific arrangement, before forming the first conductive material layer, the method further includes:

Making a substrate;

An isolation layer is formed on the substrate.

In a specific arrangement, the method further includes: forming a gate dielectric layer on the second conductive material layer; and forming a gate metal layer on the gate dielectric layer.

In a specific arrangement, the method further includes: when forming the gate dielectric layer, the gate dielectric layer partially covers the first conductive material layer, and the gate dielectric layer covers the first conductive layer A portion between the material layers is between the source and the second layer of conductive material.

DRAWINGS

1 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention;

2a to 2f are flowcharts showing the preparation of the tunneling transistor shown in FIG. 1 according to an embodiment of the present invention;

3 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention;

4a to 4g are flowcharts showing the preparation of the tunneling transistor shown in FIG. 1 according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a tunneling transistor according to another embodiment of the present invention; FIG.

6a-6f are flowcharts showing the preparation of the tunneling transistor shown in FIG. 5 according to an embodiment of the present invention.

Reference mark:

1-first conductive material layer 11-groove 2-source 3-second conductive material layer

4-gate metal layer 5-gate dielectric layer 6-insulation layer

7-drain 8-isolator 9-substrate

detailed description

The present invention will be further described in detail with reference to the accompanying drawings, in which FIG.

As shown in FIG. 1 and FIG. 3, FIG. 1 and FIG. 3 show tunneling transistors of different structures according to embodiments of the present invention.

In the tunneling transistors provided in FIG. 1 and FIG. 3, each includes: a source 2, a drain 7 and a heterojunction; wherein the heterojunction comprises a stacked first conductive material layer 1 and a second conductive material layer 3, In the first conductive material layer 1 and the second conductive material layer 3, one conductive material layer is a material layer made of a two-dimensional material, and the other conductive material layer is a material layer made of a two-dimensional material or a three-dimensional material;

The source 2 is electrically connected to the first conductive material layer 1 and insulated from the second conductive material layer 3, and the drain 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.

In the above implementation, a heterojunction is used as a channel, and the channel material is a two-dimensional material or a three-dimensional material, and the surface of the two-dimensional material has an atomic-scale thin, no dangling bond, and the like, and is formed based on a two-dimensional material. The heterojunction has no interface defects caused by lattice mismatch. Two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3eV), which increases the tunneling probability and increases the tunneling current.

Compared with traditional tunneling transistors, tunneling transistors based on two-dimensional materials have stronger gate control, fewer interface defects, can effectively suppress leakage current, have larger tunneling area, and the formation of heterojunction. Simple, which facilitates the fabrication of tunneling transistors.

In the above embodiment, the tunneling transistor has a gate dielectric layer 5 and a gate metal layer 4, wherein the gate dielectric layer 5 is disposed on the heterojunction, and the gate metal layer 4 is disposed on the gate dielectric layer 5. The gate-to-channel control can be enhanced, and the line tunneling structure is adopted, and the tunneling area is large, which can effectively increase the tunneling current. With a local gate structure, the gate only controls the heterojunction tunneling region. In the above embodiment, the tunneling transistor has a substrate, and the first conductive material layer 1 is a substrate of a tunneling transistor. The use of a two-dimensional material as a substrate simplifies the structure of the tunneling transistor.

In order to facilitate the understanding of the tunneling transistor provided by this embodiment, a detailed description will be given below in conjunction with a specific embodiment.

Example 1

As shown in FIG. 1, in the present embodiment, the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction. Wherein, the heterojunction acts as a channel structure. In a specific arrangement, the first conductive material layer 1 in the heterojunction acts as a substrate for the entire tunneling transistor.

In a specific arrangement, in order to prevent the drain 7 from coming into contact with the first conductive material layer 1, the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is disposed, the insulating layer 6 is disposed at The first conductive material layer 1 is covered, and the insulating layer 6 covers a portion of the second conductive material layer 3 to form a step structure. When the drain electrode 7 is formed on the second conductive material layer 3, the drain electrode 7 partially covers the insulating layer 6. By the isolation of the insulating layer 6, the occurrence of the conductive connection between the drain electrode 7 and the first conductive material layer 1 during processing is avoided, and the separation between the drain electrode 7 and the first conductive material layer 1 is ensured.

In the specific setting, the two-dimensional material (2D material) is tungsten diselenide (WSe _2), two tin selenide (SnSe ₂₎ or molybdenum telluride (MoTe _2); three-dimensional material (3D material) to: arsenic Indium (InAs) or silicon (Si). When the heterojunction is made by using a two-dimensional material, the two-dimensional material is a layered material having a thickness of 0.5-10 nm, such as: 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm. Any thickness between 10 nm, such as 10 nm.

Referring to FIG. 2a to FIG. 2f, in the specific preparation, the tunneling transistor is prepared as follows:

Step 1: Taking the InAs-WSe ₂ heterojunction TFET preparation as an example, an n-doped InAs substrate is provided, which is the first conductive material layer 1, and the substrate is placed at 35% HF: 35% HCl. The oxide layer was removed in about 1:1 at 1:1, and the CVD-grown WSe _{2 was} transferred onto the InAs substrate to obtain a structure as shown in Fig. 2a.

Step 2: spin-coating the photoresist on the sample in step 1, exposing and developing the photoresist, using a photoresist as a mask, removing the exposed WSe ₂ by dry etching, patterning the WSe ₂ , and removing the light. Engraved mask. As shown in FIG. 2b, the patterned WSe _{2 is} the second conductive material layer 3.

Step 3: Form source 2. Applying a photoresist to the sample of step 2, defining the source 2 region by photolithography, then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form the source 2 contact, and removing the light using a liftoff process. Engraved. Figure 2c.

Step 4: Forming the insulating layer 6. Applying photoresist to the sample from step 3, using lithography definition The Oxide insulating layer 6 is then evaporated or ALD grown with an oxide insulating layer 6. The insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide, and the photoresist is removed using a liftoff process. As shown in Fig. 2d, as shown in Fig. 2d, the insulating layer 6 is partially covered on the second conductive material layer 3.

Step 5: Prepare the drain 7. A photoresist is applied to the sample of step 4, the drain 7 region is defined by photolithography, and then the metal Ti/Pt/Au (about 5/20/30 nm) is evaporated to form a drain 7 contact connected to WSe ₂ . The photoresist is removed using a liftoff process. A sample as shown in Figure 2e was obtained.

Step 6: Forming a gate dielectric layer 5 which, when specifically disposed, is a high K material. The specific steps are as follows: applying a photoresist to the sample in step 5, defining a gate region by photolithography, and growing a high-k material yttrium oxide (or high-k material such as alumina or zirconia) by low-temperature atomic layer deposition, and steaming A gate metal (for example, Ti/Au: 5/50 nm) is plated, and the photoresist is removed using a liftoff process to obtain a sample as shown in FIG. 2f, thereby forming a gate metal layer 4 on the gate dielectric layer 5.

The structure realized by the above steps can also be implemented by other similar processes. For example, the gate dielectric layer 5 and the gate metal layer 4 can be formed by using a long gate dielectric layer 5 and a gate metal layer 4, and then masked by photoresist. The film is obtained by a wet etching method. In addition, oxide deposition methods include, but are not limited to, ALD deposition, evaporation coating deposition.

Example 2

As shown in FIG. 3, FIG. 3 is a schematic structural diagram of another tunneling transistor according to an embodiment of the present invention.

In the present embodiment, the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction. Wherein, the heterojunction acts as a channel structure. In a specific arrangement, the first conductive material layer 1 in the heterojunction acts as a substrate for the entire tunneling transistor. The material of each component in the embodiment is the same as that in the embodiment 1, and details are not described herein again.

In a specific arrangement, in order to prevent the drain 7 from coming into contact with the first conductive material layer 1, the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is disposed, the insulating layer 6 is disposed at On the first conductive material layer 1, specifically, the first conductive material layer 1 is provided with a recess 11 , the insulating layer 6 is disposed in the recess 11 , and the drain 7 is disposed on the second conductive material layer 3 and partially Covering the insulating layer 6, the isolation of the insulating layer 6 prevents the drain 7 and the first conductive material from appearing during processing. In the case where the material layer 1 is electrically connected, the partition between the drain electrode 7 and the first conductive material layer 1 is ensured. In order to ensure the barrier effect, it is preferable that the edge of the insulating layer 6 is not covered by the drain 7, thereby ensuring the effect of insulation.

In addition, in order to improve the insulation effect between the source 2 and the second conductive material layer 3, the gate dielectric layer 5 provided in this embodiment covers the second conductive material layer 3, and the gate dielectric layer 5 portion Covering the first conductive material layer 1 , and a portion of the gate dielectric layer 5 covering the first conductive material layer 1 is interposed between the source 2 and the second conductive material layer 3 . That is, when the gate dielectric layer 5 is disposed, the disposed position of one end is located outside the second conductive material layer 3, so that one end of the gate dielectric layer 5 covers the first conductive material layer 1, that is, one end of the gate dielectric layer 5 is interposed. Between the source 2 and the second conductive material layer 3, insulation between the source 2 and the second conductive material layer 3 is achieved by the gate dielectric layer 5. Improved insulation.

Referring to FIG. 4a to FIG. 4g, in the specific preparation, the tunneling transistor is prepared as follows:

Step 1: Forming the insulating layer 6. Providing an n-type doped InAs substrate, the substrate is a first conductive material layer 11, applying a photoresist on the InAs substrate, and defining an Oxide insulating layer 6 by photolithography, as shown in FIG. 4a, using the reaction Ion etching (RIE) etches a recess 11 on the InAs substrate. The insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide by vapor deposition or ALD growth, and the photoresist may be removed by a lift off process. This is obtained as shown in Figure 4b.

Step 2: Transfer the second conductive material layer 3. The oxide layer was removed by placing the substrate in 35% HF: 35% HCl = 1:1 for about 2 minutes, and the CVD-grown WSe2 was transferred onto the InAs substrate. The structure shown in Figure 4c is obtained.

Step 3: spin-coating the photoresist on the sample in step 2, exposing and developing the photoresist, using a photoresist as a mask, removing the exposed WSe2 by dry etching, patterning the WSe2, and removing the photoresist. Mask. As shown in Figure 4d.

Step 4: Forming the source and drain electrodes 7. Applying a photoresist to the sample of step 3, defining the source and drain 7 regions by photolithography, and then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form source-drain 7 contacts, using lift off The process removes the photoresist. As shown in Figure 4e.

Step 5: Forming the gate dielectric layer 5. Applying a photoresist to the sample from step 4, using photolithography The gate area. As shown in FIG. 4f, a high-k gate dielectric yttrium oxide (or a high-k material such as alumina or zirconia) is grown by low-temperature atomic layer deposition, and a gate metal layer 4 (for example, Ti/Au: 5/50 nm) is evaporated and used. The lift off process removes the photoresist to give a sample as shown in Figure 4g.

With continued reference to FIG. 4f, at the time of producing the gate dielectric layer 5, one end of the gate dielectric layer 5 covers the first conductive material layer 1 and is interposed between the second conductive material layer 3 and the source 2.

The structure realized by the above steps can also be implemented by other similar processes. For example, the formation of the gate dielectric layer 5 and the gate metal layer 4 can be performed by using a photoresist and a gate metal, and then using a photoresist as a mask for wet etching. The method of etching is obtained.

Example 3

As shown in FIG. 5, FIG. 5 is a schematic structural diagram of another tunneling transistor according to an embodiment of the present invention.

In this embodiment, the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, a heterojunction, a substrate 9, and an isolation layer 8; wherein the heterojunction serves as a channel structure.

As shown in FIG. 5, in the present embodiment, the tunneling transistor includes a substrate 9 using a silicon substrate 9, a source 2, a drain 7, a first conductive material layer 1, and a second conductive material. A portion of the layer 3 that is not interlaced with the first conductive material layer 1 is disposed on the substrate 9 and insulated from the substrate 9. Thereby, the substrate 9 is insulated from the heterojunction. In order to achieve the above insulation, an isolation layer 8 is formed on the substrate 9, and the above structure is formed on the isolation layer 8, and the isolation layer 8 is oxidized in a specific arrangement. silicon.

In a specific arrangement, the first conductive material layer 1 and the second conductive material layer 3 are stacked and partially staggered, and the second conductive material layer 3 partially covers the first material layer; the first conductive material layer 1 is provided with the insulating layer 6 The source 2 is insulated from the second conductive material layer 3 by the insulating layer 6.

In order to facilitate the understanding of the above structure, a method of fabricating the tunneling transistor will be described in detail below with reference to FIGS. 6a to 6f.

Step 1: Providing WSe ₂ material grown on the target substrate 9, or transferring the grown WSe ₂ material onto the isolation layer 8 on the target substrate 9, and then performing WSe ₂ by a method similar to that of Embodiment 1. Etching patterning. The result shown in Figure 6a is obtained.

Step 2: Prepare source 2. Applying a photoresist to the sample from step 1, using lithography to define the source The pole 2 region is then vapor-deposited with metal Ti/Pt/Au (about 5/20/30 nm) to form a source 2 contact, which is removed using a liftoff process. Figure 6b.

Step 3: Forming the insulating layer 6. The photoresist is applied to the sample of step 2, the Oxide insulating layer 6 is defined by photolithography, and then the oxide insulating layer 6 is grown by evaporation or ALD. The insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide. The lift off process removes the photoresist. As shown in Fig. 6c, a portion of the insulating layer 6 covers the source 2 and another portion overlies the first conductive material layer 1.

Step 4: Transfer the SnSe ₂ material. The grown SnSe ₂ material is transferred onto the substrate 9. SnSe ₂ is patterned using the aforementioned etching process. As shown in FIG. 6d, the step is a step of generating a second conductive material layer 3, as shown in FIG. 6d, the generated second conductive material layer 3 partially covers the first conductive material layer 1, partially covered in isolation. On the layer 8, such that the first conductive material layer 1 and the second conductive material layer 3 are stacked and partially staggered, and as shown in FIG. 6d, the formed second conductive material layer 3 and the source 2 are spaced apart The insulating layer 6 prevents the source 2 and the second conductive material layer 3 from being turned on during processing.

Step 5: Form the drain 7. Applying a photoresist to the sample of step 4, defining a drain 7 region by photolithography, and then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form a drain 7 contact connected to SnSe2. The photoresist is removed using a liftoff process. A sample as shown in Figure 6e was obtained.

Step 6: Form a gate dielectric layer 5 which is a high-k material. Applying a photoresist to the sample of step 5, defining a gate region by photolithography, and growing a high-k material such as HfO ₂ , Al ₂ O ₃ , ZrO ₂ , Y ₂ O _{3 ,} etc. by low-temperature atomic layer deposition. Material, vapor-deposited gate metal (eg Ti/Au: 5/50 nm), the photoresist was removed using a lift off process to obtain a sample as shown in Figure 6f.

It can be seen from the descriptions of Embodiment 1 and Embodiment 2 that the tunneling transistor provided in this embodiment uses a heterojunction, which may be a heterojunction composed of 2D material and 2D material or 2D material and 3D material. The channel material is controlled by a local gate. However, it should be understood that the difference provided by this embodiment The material of the knot is not limited to the above materials, but the following materials can also be used:

For 2D-3D heterojunction TFET, which heterostructure composed of _{_{InAs-WSe 2, SnSe 2 -Si}} , MoTe 2 -InAs like.

For 2D-2D heterojunction TFET, which heterostructure composition _{_{_{WSe 2 -SnSe 2, SnSe 2 -MoSe}}} 2, SnSe 2 -MoTe 2 and the like.

In addition, as can be seen from the foregoing specific embodiment 1 and the second embodiment, the embodiment of the present invention further provides a method for fabricating the tunneling transistor described above, the method comprising the following steps:

Forming a first conductive material layer 1;

Forming a second conductive material layer 3 on the first conductive material layer 1, wherein one of the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is a two-dimensional material or a three-dimensional material. The layer of material produced;

Forming the source 2, and the formed source 2 is electrically connected to the first conductive material layer 1 and insulated from the second conductive material layer 3;

The drain electrode 7 is formed, and the formed drain electrode 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.

In the above technical solution, the channel material is a two-dimensional material with a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current. In addition, two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current. With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.

For the tunneling transistor in Embodiment 1, it can be seen from the description of the preparation method in Embodiment 1, the method further includes:

Forming an insulating layer 6 on the first conductive material layer 1, and forming an insulating layer 6 covering a portion of the second conductive material layer 3;

When the drain electrode 7 is formed, the drain electrode 7 formed is located on the second conductive material layer 3 and covers a portion of the insulating layer 6.

Forming a gate dielectric layer 5 on the second conductive material layer 3;

A gate metal layer 4 is formed on the gate dielectric layer 5.

For the tunneling transistor in Embodiment 2, as can be seen from the description of the preparation method in Embodiment 2, the method further includes:

Forming a groove on the first conductive material layer, providing an insulating layer in the groove; and forming a second conductive material layer covering a portion of the insulating layer;

When the drain is formed, the formed drain is on the second conductive material layer and covers a portion of the insulating layer.

Forming a gate dielectric layer 5 on the second conductive material layer 3;

Forming a gate metal layer 4 on the gate dielectric layer 5;

When the gate dielectric layer 5 is formed, the gate dielectric layer 5 partially covers the first conductive material layer 1, and the portion of the gate dielectric layer 5 covering the first conductive material layer 1 is interposed The source 2 is between the second conductive material layer 3.

For the tunneling transistor in Embodiment 3, it can be seen from the description of the preparation method in Embodiment 3 that the method further includes: before forming the first conductive material layer 1 further comprising:

Making a substrate;

An insulating layer 6 is formed on the substrate.

An insulating layer 6 is formed on the first conductive material layer 1, and the insulating layer 6 covers a part of the source 2.

Forming a gate dielectric layer 5 on the second conductive material layer 3;

A gate metal layer 4 is formed on the gate dielectric layer 5.

In the above specific preparation steps, the details are described in the first embodiment, the second embodiment and the third embodiment, and will not be described in detail herein.

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A tunneling transistor, comprising: a source, a drain, and a heterojunction; wherein the heterojunction comprises a stacked first conductive material layer and a second conductive material layer, the first conductive material In the layer and the second conductive material layer, one conductive material layer is a material layer made of a two-dimensional material, and the other conductive material layer is a material layer made of a two-dimensional material or a three-dimensional material;

The source is electrically connected to the first conductive material layer and insulated from the second conductive material layer, and the drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.
The tunneling transistor of claim 1 further comprising a gate dielectric layer and a gate metal layer, wherein the gate dielectric layer is disposed on the heterojunction, and the gate metal layer is disposed on On the gate dielectric layer.
The tunneling transistor of claim 2, wherein the gate dielectric layer covers the second conductive material layer, and the gate dielectric layer partially covers the first conductive material layer, and A portion of the gate dielectric layer overlying the first conductive material layer is interposed between the source and the second conductive material layer.
A tunneling transistor according to any one of claims 1 to 3, further comprising a substrate, said first conductive material layer being a substrate of said tunneling transistor.
A tunneling transistor according to claim 4, further comprising an insulating layer disposed on said first conductive material layer, said insulating layer covering a portion of said second conductive material layer, said drain passing through The insulating layer is insulated from the first conductive material layer.
A tunneling transistor according to claim 4, further comprising an insulating layer, said first conductive material layer being provided with a recess, said insulating layer being disposed in said recess, said drain setting On the insulating layer and partially covering the second conductive material layer.
The tunneling transistor according to claim 1 or 2, wherein the first conductive material layer and the second conductive material layer are stacked and partially staggered, and the second conductive material layer partially covers the a first material layer; an insulating layer disposed on the first conductive material layer, wherein the source is insulated from the second conductive material layer by the insulating layer.
The tunneling transistor of claim 7 further comprising a substrate, said source, drain, first conductive material layer and said second conductive material layer and said first conductive material layer not Interleaved portions are disposed on the substrate and insulated from the substrate.
The tunneling transistor of claim 8 , wherein the substrate is provided with an isolation layer, the source, the drain, the first conductive material layer and the second conductive material layer and the first A portion of the conductive material layer that is not staggered is disposed on the isolation layer.
The tunneling transistor according to any one of claims 1 to 9, wherein the two-dimensional material is tungsten diselenide, tin diselenide or molybdenum telluride; and the three-dimensional material is: indium arsenide or silicon.
A method for fabricating a tunneling transistor, comprising the steps of:

Forming a first conductive material layer;

Forming a second conductive material layer on the first conductive material layer, wherein one of the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material. Material layer

Forming a source, and forming a source electrically connected to the first conductive material layer and insulated from the second conductive material layer;

A drain is formed, and the formed drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.
The preparation method according to claim 11, further comprising:

Forming an insulating layer on the first conductive material layer, and forming an insulating layer covering a portion of the second conductive material layer;

When the drain is formed, the formed drain is on the second conductive material layer and covers a portion of the insulating layer.
The preparation method according to claim 11, further comprising:

Forming a groove on the first conductive material layer, providing an insulating layer in the groove; and forming a second conductive material layer covering a portion of the insulating layer;

When the drain is formed, the formed drain is on the second conductive material layer and covers a portion of the insulating layer.
The preparation method according to claim 11, further comprising:

An insulating layer is formed on the first conductive material layer, and the insulating layer covers a portion of the source.
The method according to claim 14, further comprising: before forming the first conductive material layer:

Making a substrate;

An isolation layer is formed on the substrate.
The preparation method according to any one of claims 11 to 15, further comprising:

Forming a gate dielectric layer on the second conductive material layer;

A gate metal layer is formed on the gate dielectric layer.
The method according to claim 16, wherein when the gate dielectric layer is formed, the gate dielectric layer partially covers the first conductive material layer, and the gate dielectric layer covers the first A portion between the layers of electrically conductive material is interposed between the source and the second layer of electrically conductive material.