CN103329244B - There is the graphene device of local double grid - Google Patents

There is the graphene device of local double grid Download PDF

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Publication number
CN103329244B
CN103329244B CN201180064269.0A CN201180064269A CN103329244B CN 103329244 B CN103329244 B CN 103329244B CN 201180064269 A CN201180064269 A CN 201180064269A CN 103329244 B CN103329244 B CN 103329244B
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China
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described
grid
local
dielectric layer
insulator
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CN201180064269.0A
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Chinese (zh)
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CN103329244A (en
Inventor
陈志宏
A·D·富兰克林
汉述仁
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国际商业机器公司
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Priority to US12/986,342 priority Critical patent/US9076873B2/en
Priority to US12/986,342 priority
Application filed by 国际商业机器公司 filed Critical 国际商业机器公司
Priority to PCT/US2011/066463 priority patent/WO2012094154A1/en
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Publication of CN103329244B publication Critical patent/CN103329244B/en

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Abstract

A kind of electronic device includes: insulator; Embedding the local first grid in described insulator, the top surface of wherein said first grid is substantially coplanar with the surface of described insulator; The first dielectric layer formed on described first grid and insulator; And raceway groove. Described raceway groove includes the bilayer graphene layer formed on described first dielectric layer. Described first dielectric layer provides substantially flat surface, and described raceway groove is formed on this substantially flat surface. The second dielectric layer formed on described bilayer graphene layer and the local second grid formed on described second dielectric layer. The described raceway groove capacitive coupling of each in the first and second grid of described local and described bilayer graphene layer. Described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly.

Description

There is the graphene device of local double grid

Technical field

The present invention relates to semiconductor structure, especially, relate to the device based on local double grid (localdualgates) Graphene and manufacture method thereof.

Background technology

In a semiconductor material, band gap is important parameter, and this parameter determines the characteristic of semi-conducting material to a great extent. Band gap is defined as the energy difference between bottom valence band top and conduction band. This be by electronics from valence to conduction band needed for energy. Electronics in conduction band has the ability moving through material such that it is able to conduction.

A kind of semi-conducting material Graphene (graphene) is due to the carrier mobility more much higher than silicon, so receiving great concern for nanoscale electric. Graphene is the two dimensional surface thin slice of the carbon atom with the arrangement of hexagonal benzene ring structure. Independent graphene-structured is only stable in two-dimensional space in theory, it means that plane graphene-structured can not exist with free state, unstable relative to the formation of the warp architecture of such as flue dust (soot), fullerene (fullerenes) and nanotube. But, two-dimensional graphene structure has turned out on the surface that may be located at three dimensional structure, for instance, it is positioned at silicon dioxide (SiO2) surface on. Typical graphene layer can include single or multiple carbon atom thin layer, for instance between 1 to 10 thin layer.

Field-effect transistor (FET) is device main and important in manufacturing integrated circuit. FET can be used for amplifying, switching and detect signal. In FET device, FET relies on electric field to control carrier density, thus controlling the channel conductance of a type of electric charge carrier. Known Graphene has been used for forming FET. Regrettably, although have high carrier mobility, Graphene has zero band gap, and this causes the FET Leakage Current of extreme difference. It is use both to there is top-gated also there is the bilayer graphene of substrate to a solution of this problem, thus opening the band gap of this material. But, control owing to lacking the threshold voltage (Vt) to each device, therefore, this substrat structure makes extensive complementary metal oxide semiconductors (CMOS) (CMOS) transistor unrealistic.

Summary of the invention

The present invention relates to semiconductor structure, especially, relate to the device based on local double grid Graphene and manufacture method thereof. More specifically, the present invention provides the technology forming bilayer graphene layer, described bilayer graphene layer device includes top-gated and the bottom gate of composition, in order to according to device and/or circuit requirement by the different voltage bias of the different components on same wafer to different band gap or threshold voltage (Vt).

Such as, in the first aspect, a kind of method forming electronic device includes: form insulator; Embedding in described insulator by local first grid, the top surface of wherein said first grid is substantially coplanar with the surface of described insulator; Depositing first dielectric layer on described first grid and insulator; And formation raceway groove, described raceway groove includes the bilayer graphene layer formed on described first dielectric layer. Described first dielectric layer provides flat surfaces, and described raceway groove is formed on this flat surfaces. Described method is additionally included on described bilayer graphene layer depositing second dielectric layer and forms local second grid on described second dielectric layer. The described raceway groove capacitive coupling of each in the first and second grid of described local and described bilayer graphene layer. Described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly.

Described method can also include: forms local the 3rd grid being embedded in described insulator, and the top surface of wherein said 3rd grid is substantially coplanar with the surface of described insulator; And on described second dielectric layer, form local the 4th grid. The described raceway groove capacitive coupling of each in the third and fourth grid of described local and described bilayer graphene layer. Described local the third and fourth grid forms at least the second pair of grid to control at least Part II of described bilayer graphene layer partly. Described at least the second pair of grid works as the grid of transistor seconds.

In a second aspect of the present invention, a kind of electronic device includes: insulator; Embedding the local first grid in described insulator, the top surface of wherein said first grid is substantially coplanar with the surface of described insulator; The first dielectric layer formed on described first grid and insulator; And raceway groove, it includes the bilayer graphene layer formed on described first dielectric layer. Described first dielectric layer provides flat surfaces, and described raceway groove is formed on this flat surfaces. Described device is additionally included in the second dielectric layer formed on described bilayer graphene layer and the local second grid formed on described second dielectric layer. The described raceway groove capacitive coupling of each in the first and second grid of described local and described bilayer graphene layer. Described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly.

According to the third aspect of the invention we, a kind of integrated circuit includes at least one double grid graphene layer device circuitry. At least one device circuitry described includes: insulator; Embedding the local first grid in described insulator, the top surface of wherein said first grid is substantially coplanar with the surface of described insulator; The first dielectric layer formed on described first grid and insulator; And raceway groove, it includes the bilayer graphene layer formed on described first dielectric layer. Described first dielectric layer provides flat surfaces, and described raceway groove is formed on this flat surfaces. Described device is additionally included in the second dielectric layer formed on described bilayer graphene layer and the local second grid formed on described second dielectric layer. The described raceway groove capacitive coupling of each in the first and second grid of described local and described bilayer graphene layer. Described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly.

Advantageously, said structure and technology utilize the advantageous feature of Graphene.

Reading the detailed description of the following exemplary embodiment to the present invention in conjunction with the drawings, these and other target of the present invention, feature and advantage will become clear from.

Accompanying drawing explanation

Fig. 1 illustrates the electronic device of the exemplary embodiment according to the present invention.

Fig. 2 illustrates the first top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 3 illustrates the second top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 4 illustrates the 3rd top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 5 illustrates the 4th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 6 illustrates the 5th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 7 illustrates the 6th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 8 illustrates the 7th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Fig. 9 illustrates the 8th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 10 illustrates the 9th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 11 illustrates the tenth top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 12 illustrates the 11st top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 13 illustrates the 12nd top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 14 illustrates the 13rd top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 15 illustrates the 14th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 16 illustrates the 15th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 17 illustrates the 16th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 18 illustrates the 17th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 19 illustrates the 18th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 20 illustrates the 19th top-down view of the electronic device of the exemplary embodiment according to the present invention.

Figure 21 illustrates the Alternative electronic device of the exemplary embodiment according to the present invention.

Figure 22 illustrates another Alternative electronic device of the exemplary embodiment according to the present invention.

Figure 23 illustrates the another Alternative electronic device of the exemplary embodiment according to the present invention.

Detailed description of the invention

The present invention relates to the electronic device (such as field-effect transistor (FET)) based on Graphene and manufacture method thereof. The two-layer electronic band structure of Graphene has caused the concern to the gap tunable two-layer electronic device producing such as FET. When manufacturing electronic device, a usual wafer can hold multiple device. Electronic device described herein includes top-gated and the bottom gate of composition, with according to device and/or circuit requirement by the different voltage bias on the different components on same wafer to different band gap or threshold voltage (Vt). Using the advantage of bottom gate of composition for forming ability and/or the technology of the CMOS logic device that can provide multiple device Vt, this is very common in semi-conductor industry now. Such as, the low Vt device of high switch speed it is arranged to generally on the same wafer and for lower powered high Vt device.

Except lacking the control ability to independent device Vt, the bottom gate of non-composition also means that whole wafer and shares same bottom gate, and this can cause unpractical high gate leakage from bottom gate. It is said that in general, when the length of gate electrode and the thickness of gate oxide reduce, it is possible to higher speed switching electronic device. But, the thickness of gate oxide reduces can cause that substantial amounts of Leakage Current flows through gate oxide, thus the excessive non-firm power (standbypower) that can expend. Leakage Current exponentially changes along with the change of the thickness of gate oxide. This affects the functional of circuit.

In order to alleviate gate leakage problem, top-gated and the bottom gate of the present invention are patterned. Band gap and device threshold voltage (Vt) are determined by the biasing relative to bottom gate. When the bottom gate of composition, it is possible to by different threshold voltages or band gap, each independent device on same wafer is adjusted independently. Such as, the NFET(electron conductive type device on same wafer) and PFET(hole conduction type device) top-gated of device and bottom gate can have different biasings.

Fig. 1 illustrates the example tunable gap electron device 100 of the exemplary embodiment according to the present invention, for instance FET device. Electronic device 100 includes substrate 105 and covers insulator 110 on the substrate 105. Local first grid 115 is embedded in insulator 110, and wherein the top surface of local first grid 115 is substantially coplanar with the surface of insulator 110. First dielectric layer 120 covers on first grid 115 and insulator 110. Raceway groove 125 is formed by bilayer graphene layer 130, and described bilayer graphene layer 130 is formed on the first dielectric layer 120 on the first grid 115 of local. Being positioned at the first dielectric layer 120 on local first grid 115 and insulator 110 and provide flat surfaces, raceway groove 125 is formed on this flat surfaces.

Second dielectric layer 135 is formed on bilayer graphene layer 130. Local second grid 140 is formed on the second dielectric layer 135. The locally raceway groove capacitive coupling of each in the first and second grids 115,140 and bilayer graphene layer 130. Electronic device 100 also includes the source/drain region 150 connected by raceway groove 125. First and second grids 115,140 regulate the electron stream by raceway groove 125. Although Fig. 1 exemplifies three transistors 175,180,185 of manufacture on Single Electron device 100 on a single wafer, it should be understood that, it is possible to there is the transistor of more than three or less than three of that. Should also be understood that in addition to transistors, it is also possible on electronic device 100, manufacture other electronic device.

Fig. 2-20 exemplifies in the present invention for manufacturing each manufacturing step of electronic device 100. As described in this, electronic device 100 has three transistors 175,180,185. The first transistor 175 is n-type polycrystalline crystal pipe, the 3rd and third transistor 180,185 be p-type polycrystalline crystal pipe. With reference now to Fig. 2, it is provided that substrate 105. Substrate 105 is made up of any materials, and described material can be but not limited to silicon (Si). Oxidation technology is used to form such as silicon dioxide (SiO on the top of substrate 1052) oxide skin(coating)/insulator 110. Oxidation technology relates to, in comprising the atmosphere of oxygen or steam, the substrate 105 of such as Si substrate is heated to about 900 degrees Celsius to about 1200 degrees Celsius. Oxygen or water are diffused into the surface of substrate 105 and occur oxidation reaction to form thickness thermal oxide layer in about 300 (300) nanometers (nm) to the scope of one (1) micron (��m). Oxide skin(coating) 110 serves as insulator, in this insulator, forms multiple bottom gate 196, as shown in Figure 3. Although Fig. 3 illustrates three bottom gates 196, it should be appreciated that, it is positioned on the device 100 on single wafer and can have the bottom gate fewer of more than three. The plurality of bottom gate 196 includes first grid 115.

Formed after oxide skin(coating) 110 on the substrate 105, device 100 is carried out photoetching (lithography). Photoetching is typically via being optionally exposed to the radiation source of such as light by Graphic transitions to sensitive material. Sensitive material refers to the material that its physical characteristic changes when being exposed to radiation source. By sensitive material is optionally exposed to radiation (such as, radiated by shaded portions), owing to the characteristic with unexposed region exposed is different, the figure of the radiation on material is transferred on the material exposed.

Photoetching process includes being applied on oxide skin(coating) 110 (as shown in Figure 3) by photoresist 190, photoresist 190 is exposed to radiating pattern, and use conventional resist development agent to be developed in photoresist 190 by this figure, then perform the dry etching of such as ionic reaction etching (as shown by the arrows in figure 4), ion beam milling, plasma etching or laser ablation. Etching step can include single etch process or multiple etch process, thinks that this structure provides the degree of depth (being denoted as " D ") to be as shown in Figure 4 at least one in about 20nm to the bottom gate 196 of about 300nm. After the etching, conventional lift-off process well known to those skilled in the art is utilized to remove photoresist from this structure, as shown in Figure 5. The trench length (being denoted as " L ") formed at least one in bottom gate 196 is about one (1) nm to about (1) ��m.

Including the insulator layer 110(of bottom gate 196 as shown in Figure 6) on form polysilicon 195(also referred to as polycrystalline Si or polycrystalline (poly)) film. The thickness of the film of polysilicon 195 is about 200 (200) nm to about 700 (700) nm. Then polysilicon 195 is carried out chemically mechanical polishing (CMP) to manufacture the device with structure as shown in Figure 7. CMP is the technique for planarized semiconductor wafer. CMP utilizes the synergism of physics and chemical force that wafer is polished. This is by the back imposed load power of wafer being realized while resting on liner by wafer. Then comprise the slurry of grinding agent and reactive chemistry product below by while, make both liner and wafer reversely rotate.

After the cmp process, device architecture 100 is carried out conventional lithographic, is applied on the top of oxide skin(coating) including by photoresist 190, but second and third transistor 180,185 are performed ion implanting, specifically, p-type polycrystalline ion implanting. Photoetching process includes being exposed to photoresist 190 radiating pattern, and uses conventional resist development agent to be developed in photoresist by this figure. Then device 100 is carried out the dry etching of such as reactive ion etching, ion beam milling, plasma etching or laser ablation. Etching step can include single etch process or multiple etch process to provide the structure exemplified by Fig. 8.

After the etching, device 100 is carried out ion implanting to form source area as shown in Figure 9 and drain region 150. Perform ion implantation technology, electrical dopant to be injected in the expose portion (it is, the part not covered by photoresist 190) of bottom gate 196. More specifically, second and the local bottom gate 155,165 of third transistor 180,185 adulterated by p-type polycrystalline respectively. But, dopant ion can be n-type or p-type dopant. In one embodiment, it is respectively directed to the local bottom gate 155,165 of second and third transistor 180,185, with about five (5) kilo electron volts (KeV) to the energy rank of about ten (10) KeV, performs dosage from about 1E14 atom/cm2To about 5E15 atom/cm2The boron (B) of dosage or boron difluoride (BF2) inject. Other adulterant can include aluminum (Al), gallium (Ga), indium (In), phosphorus (P), argon (Ar), antimony (Sb) and its combination. The angle of ion implanting, dosage and energy can be selected, in order to provide high conductivity for source area and drain region 150, so that the source electrode of the transistor to be formed and drain resistance minimize. Then conventional lift-off process well known to those skilled in the art is used to remove photoresist, to provide the structure exemplified by Figure 10.

Next step is generation n-type polycrystalline in the first transistor 175. In order to produce the first transistor 175 with n-type polycrystalline, device 100 is carried out photoetching. This technique includes applying another photoresist 190 on oxide skin(coating) 110 and local the 3rd and the 5th grid 155,165, but exposes local first grid 115, as shown in figure 11. Photoetching process also includes photoresist 190 is exposed to radiating pattern, and use conventional resist development agent to be developed in photoresist 190 by figure, and carry out the dry etching of such as reactive ion etching, ion beam milling, plasma etching or laser ablation. Etching step can include single etch process or multiple etch process, has the degree of depth for the structure of at least one in the bottom gate 196 of about 100nm with offer. After the etching, device 100 is carried out ion implanting, as shown in figure 12. In one embodiment, the n-type material of such as phosphorus (P) or arsenic (As) is injected into local first bottom gate 115 of the first transistor 175. Then utilize and well known to a person skilled in the art that conventional lift-off process removes photoresist 190, to provide the structure of example as shown in figure 13.

After the implant step, device 100 carrying out under such as about 1,000 (1,000) degree Celsius rapid thermal annealing (RTA) technique of about five (5) seconds, this is used for diffusing, doping agent ion. Such as, the time continuing about one (1) minute or more of a specified duration in the inert atmosphere of such as helium (He), argon (Ar) or their mixture at the temperature of about 700 (700) degrees Celsius or higher performs activation annealing steps. As shown in figure 13, local the first bottom gate 115 is n-type polycrystalline grid, and local bottom gate 155,165 is p-type polycrystalline grid.

After ion implantation, depositing first dielectric floor 120 on each several part in oxide skin(coating) 110 and bottom gate district 196, as shown in figure 14. First dielectric layer 120 can comprise high-k dielectric material, for instance hafnium oxide (HFO2), zirconium oxide (ZrO2), aluminium oxide (Al2O3), titanium dioxide (TiO2), lanthana (La2O3), strontium titanates (SrTiO3), lanthanum aluminate (LaAlO3), hafnium silicate (HfSixOy), barium strontium (BSTs) or lead zirconate titanate (PZT). Grid dielectric material can pass through ald (ALD), thermal oxide or plasma oxidation, tropical resources or pecvd nitride, chemical vapor deposition (CVD) and/or physical vapor deposition (PVD) and be formed. The gross thickness of dielectric layer 120 can in about 0.5nm to the scope of about 30nm. Alternatively, dielectric layer 120 can comprise conventional gate dielectric, for instance silicon oxide or silicon nitride, and it is deposited as similar thickness by chemical vapour deposition (CVD). Then on dielectric layer 120, form bilayer graphene layer 130.

Bilayer graphene layer 130 can be grown by solid-state graphitization. During graphitization technique, carbon atom forms bilayer graphene layer 130 from silicon carbide distillation. The technique that those skilled in the art can also utilize other known formation bilayer graphene layer 130.

The second dielectric layer 135 is formed on bilayer graphene layer 130. Second dielectric layer 135 can comprise high-k dielectric material, for instance HFO2��ZrO2��Al2O3��TiO2��La2O3��SrTiO3��LaAlO3, hafnium silicate, barium strontium (BST) or lead zirconate titanate (PZT). Grid dielectric material can pass through ald (ALD), thermal oxide or plasma oxidation, tropical resources or pecvd nitride, chemical vapor deposition (CVD) and/or physical vapor deposition (PVD) and be formed. The gross thickness of the second dielectric layer 135 is in about 0.5nm to the scope of about 30nm. Alternatively, the second dielectric layer 135 can comprise conventional gate dielectric, for instance silicon oxide or silicon nitride, and it is deposited as similar thickness by chemical vapour deposition (CVD).

After forming the second dielectric layer 135, as shown in figure 15, device 100 is carried out photoetching and etching, with composition local top-gated 140,160,170, as shown in figure 16. Photoetching process includes peeling off with composition local top-gated 135,160,170.

Then deposition photoresist oxidant layer 190 is to cover local the second top-gated 140 and to expose local the 4th and the 6th grid 160,170. Perform ion implantation process with such as p-type polycrystalline doping local the 4th and the 6th grid 160,170, as shown in figure 17. But, dopant ion can be n-type or p-type dopant. Then use and well known to a person skilled in the art that conventional lift-off process removes photoresist oxidant layer 190.

Next step is generation n-type polycrystalline in the first transistor 175. In order to produce the first transistor 175 with n-type polycrystalline, device 100 is carried out photoetching. This technique includes applying another photoresist 190 to cover local the 4th and the 6th grid 160,170, but exposes local second grid 140, as shown in figure 18. Photoetching process also includes photoresist 190 is exposed to radiating pattern, and use conventional resist development agent to be developed by figure in photoresist 190, then perform the dry etching of such as reactive ion etching, ion beam milling, plasma etching or laser ablation. Etching step can include single etch process or multiple etch process, has the degree of depth for the structure of at least one in the top-gated 197 of about 100nm with offer. After the etching, device 100 is carried out ion implanting. In one embodiment, the n-type material of such as phosphorus (P) or arsenic (As) is injected into local second top-gated 140 of the first transistor 175. Then utilize and well known to a person skilled in the art that conventional lift-off process removes photoresist, to provide the structure exemplified by Figure 19.

After forming source area and drain region 150, form contact 145 for each source/drain region 150, as shown in figure 20. Figure 20 is also shown on electronic device 100 have three transistors 175,180,185, and this electronic device 100 is positioned on single wafer. Local the first and second grid 115,140 forms first to grid to control the Part I of bilayer graphene layer 130 partly. The first pair of grid works as the grid of the first transistor 175.

Local the third and fourth grid 155,160 forms second to grid to control the Part II of bilayer graphene layer 130 partly. The second pair of grid works as the grid of transistor seconds 180.

Local the 5th and the 6th grid 165,170 forms the 3rd pair of grid to control the Part III of bilayer graphene layer 130 partly. The 3rd pair of grid works as the grid of third transistor 185.

Every pair of grid has top-gated and the bottom gate of composition, in order to according to device and/or circuit requirement by the different voltage bias on the different crystal pipe 175,180,185 on same device 100 to different band gap or threshold voltage. Band gap and device threshold voltage are determined by the biasing relative to bottom gate. Utilize the bottom gate of composition, it is possible to by different threshold voltages or band gap, each independent transistor 175,180,185 on same device 100 is carried out independent regulation.

Figure 21 exemplifies another embodiment of device 200. Be doped with except n-type or p-type dopant except all grids, device 200 is similar to device 100. Such as, all local grid 215,240,255,260,265,270 is n-type dopant. Alternatively, all local grid 215,240,255,260,265,270 is p-type dopant. Owing to all grids are similarly adulterated, therefore three transistors 275,280,285 are identical type. Partly different by gate bias conditions control and the device 100 that partly controlled by gate work-function (such as, doping) with wherein Vt, the Vt of device 200 is completely by gate bias conditions control.

Figure 22 exemplifies another embodiment of device 300. Except the metal that all local grid 315,340,355,360,365,370 is single type, device 300 is similar to device 100. Such as, local grid 315,340,355,360,365,370 is made up of such as aluminum or tungsten material. Therefore, omit ion implanting step and manufacture device 300.

Figure 23 exemplifies another embodiment of device 400. Except have two metalloids as grid except, device 400 is similar to device 300. Such as, first pair of grid 405 works as being used for controlling the grid of n-type field-effect transistor (FET). First pair of grid 405 can have the metal gates being made up of such as aluminum. Second pair and the 3rd pair of grid 410,415 can be another kind of metal materials, for instance tungsten, to produce p-type FET.

Can realizing in integrated circuits at least partially of the double grid graphene device circuit of the present invention. When forming integrated circuit, typically manufacture multiple identical tube cores (die) with the pattern repeated on a surface of a semiconductor wafer. Each tube core includes device described here, and can include other structure and/or circuit. Cut out from wafer or mark independent tube core, being then encapsulated as integrated circuit. Skilled artisan would know how wafer carries out scribing and how package die is to manufacture integrated circuit. The integrated circuit so manufactured is considered the part of the present invention.

It will be appreciated that and it should be appreciated that the exemplary embodiment of the invention described above can be realized by modes different in a large number. When providing the teachings of the present invention provided herein, those of ordinary skill in the related art are by it is contemplated that other embodiment of the present invention. Actually, although describe the exemplary embodiment of the present invention herein with reference to accompanying drawing, it will be understood that, the invention is not restricted to these accurate embodiments, when not necessarily departing from the scope of the present invention or spirit, those skilled in the art can make various other and change and amendment.

Claims (17)

1. an electronic device, including:
Insulator;
Embed the local first grid in described insulator and local the 3rd grid, the top surface of wherein said local first grid and the top surface of described local the 3rd grid and the surface of described insulator is substantially coplanar;
The first dielectric layer formed on described local first grid, described local the 3rd grid and described insulator;
Raceway groove, it includes the bilayer graphene layer formed on described first dielectric layer, and wherein, described first dielectric layer provides substantially flat surface, and described raceway groove is formed on this substantially flat surface;
The second dielectric layer formed on described bilayer graphene layer; And
The local second grid formed on described second dielectric layer and local the 4th grid, each in the first, second, third and fourth grid of described local is configured to the described raceway groove capacitive coupling with described bilayer graphene layer;
Wherein, described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly, and described local the third and fourth grid forms at least the second pair of grid to control at least Part II of described bilayer graphene layer partly
Wherein, described first pair of grid works as the grid of the first transistor, and described at least the second pair of grid works as the grid of transistor seconds, and
Wherein, described first pair of grid and described at least the second pair of grid provide the independence of the threshold voltage of the threshold voltage to described the first transistor and described transistor seconds to control respectively.
2. device according to claim 1, also includes each source area for being connected and the contact of drain region formation by described raceway groove.
3. device according to claim 1, wherein, at least one in the first, second, third and fourth grid of described local comprises metal material.
4. device according to claim 1, wherein, at least one in the first, second, third and fourth grid of described local has the channel length of 1nm to 1 ��m.
5. device according to claim 1, wherein, at least one in the first, second, third and fourth grid of described local comprises polysilicon.
6. device according to claim 1, wherein, described the first transistor has the threshold voltage determined by described local the first and second grid.
7. device according to claim 1, wherein, described at least transistor seconds has the threshold voltage determined by described local the third and fourth grid.
8. device according to claim 1, wherein, at least one in described first and second dielectric layers comprises one or more in aluminium oxide and hafnium oxide.
9. device according to claim 1, wherein, described insulator includes silicon dioxide.
10. the method forming electronic device, including:
Form insulator;
Local first grid and local the 3rd grid being embedded in described insulator, the top surface of wherein said local first grid and the top surface of described local the 3rd grid and the surface of described insulator are substantially coplanar;
Depositing first dielectric layer on described local first grid, described local the 3rd grid and insulator;
Forming raceway groove, described raceway groove includes the bilayer graphene layer formed on described first dielectric layer, and wherein, described first dielectric layer provides flat surfaces, and described raceway groove is formed on this flat surfaces;
Depositing second dielectric layer on described bilayer graphene layer; And
Forming local second grid and local the 4th grid on described second dielectric layer, each in the first, second, third and fourth grid of described local is configured to the described raceway groove capacitive coupling with described bilayer graphene layer;
Wherein, described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly, and described local the third and fourth grid forms at least the second pair of grid to control at least Part II of described bilayer graphene layer partly
Wherein, described first pair of grid works as the grid of the first transistor, and described at least the second pair of grid works as the grid of transistor seconds, and
Wherein, described first pair of grid and described at least the second pair of grid provide the independence of the threshold voltage of the threshold voltage to described the first transistor and described transistor seconds to control respectively.
11. method according to claim 10, wherein, at least one in the first, second, third and fourth grid of described local comprises metal material.
12. method according to claim 10, wherein, at least one in the first, second, third and fourth grid of described local has the channel length of 1nm to 1 ��m.
13. method according to claim 10, wherein, at least one in the first, second, third and fourth grid of described local comprises polysilicon.
14. method according to claim 10, wherein, described the first transistor has the threshold voltage determined by described local the first and second grid.
15. method according to claim 10, wherein, described at least transistor seconds has the threshold voltage determined by described local the third and fourth grid.
16. method according to claim 10, wherein, at least one in described first and second dielectric layers comprises one or more in aluminium oxide and hafnium oxide.
17. include an integrated circuit at least one double grid graphene device circuit, at least one device circuitry described includes:
Insulator;
Embed the local first grid in described insulator and local the 3rd grid, the top surface of wherein said local first grid and the top surface of described local the 3rd grid and the surface of described insulator is substantially coplanar;
The first dielectric layer formed on described local first grid, described local the 3rd grid and described insulator;
Raceway groove, it includes the bilayer graphene layer formed on described first dielectric layer, and wherein, described first dielectric layer provides substantially flat surface, and described raceway groove is formed on this substantially flat surface;
The second dielectric layer formed on described bilayer graphene layer; And
The local second grid formed on described second dielectric layer and local the 4th grid, each in the first, second, third and fourth grid of described local is configured to the described raceway groove capacitive coupling with described bilayer graphene layer;
Wherein, described local the first and second grid forms first to grid to control the Part I of described bilayer graphene layer partly, and described local the third and fourth grid forms at least the second pair of grid to control at least Part II of described bilayer graphene layer partly
Wherein, described first pair of grid works as the grid of the first transistor, and described at least the second pair of grid works as the grid of transistor seconds, and
Wherein, described first pair of grid and described at least the second pair of grid provide the independence of the threshold voltage of the threshold voltage to described the first transistor and described transistor seconds to control respectively.
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