CN109155333B - Tunneling transistor and preparation method thereof - Google Patents
Tunneling transistor and preparation method thereof Download PDFInfo
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- CN109155333B CN109155333B CN201680085756.8A CN201680085756A CN109155333B CN 109155333 B CN109155333 B CN 109155333B CN 201680085756 A CN201680085756 A CN 201680085756A CN 109155333 B CN109155333 B CN 109155333B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
A tunneling transistor and a preparation method thereof are provided, the transistor comprises: a source, a drain and a heterojunction; the heterojunction comprises a first conductive material layer and a second conductive material layer which are stacked, wherein one of the two conductive material layers is a two-dimensional material, and the other one of the two conductive material layers is a material layer made of a two-dimensional or three-dimensional material; the source electrode is electrically connected with the first conductive material layer and insulated from the second conductive material layer, and the drain electrode is electrically connected with the second conductive material layer and insulated from the first conductive material layer. In the technical scheme, the channel material is a two-dimensional material, the heterojunction interface barrier is small (less than 0.3eV), the tunneling probability is increased, and the tunneling current is improved. And a local area gate structure is adopted, and the grid only controls the heterojunction tunneling area. The heterojunction is simple to form, has no interface defect caused by lattice mismatch, and can effectively inhibit leakage current.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a tunneling transistor and a preparation method thereof.
Background
As the size of transistors is continuously reduced, the leakage current caused by short channel effect is continuously increased, so that the power consumption of the integrated circuit becomes more and more a non-negligible problem. Unlike a traditional MOSFET, a TFET (tunneling transistor) adopts an interband tunneling mechanism, SS of the TFET can be lower than the room temperature limit of 60mV/dec, and the working voltage can be effectively reduced, so that the power consumption is remarkably reduced.
The existing TFET technology mainly comprises a homojunction TFET taking silicon as a channel material and a heterojunction TFET taking III-V group materials as a channel. Because the silicon material has a larger band gap and is an indirect band gap semiconductor, although the silicon-based TFET can obtain SS with the concentration of less than 60mV/dec, the on-state current of the silicon-based TFET is mostly less than 1 muA/mum and can not meet the application requirements. Although the band gap of the III-V group material is small, the effective mass is small, and the heterojunction TFET based on the III-V group material can obtain large on-state current, the SS smaller than 60mV/dec cannot be obtained due to heterojunction interface defects caused by lattice mismatch and the like.
Disclosure of Invention
The embodiment of the invention provides a tunneling transistor and a preparation method thereof, which are used for improving the conduction performance of the tunneling transistor.
An embodiment of the present invention provides a tunneling transistor, including: a source, a drain and a heterojunction; the heterojunction comprises a first conductive material layer and a second conductive material layer which are stacked, wherein one conductive material layer is made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material; the source electrode is electrically connected with the first conductive material layer and is insulated from the second conductive material layer, and the drain electrode is electrically connected with the second conductive material layer and is insulated from the first conductive material layer.
In the embodiment of the invention, the channel material is an atomic-level thin two-dimensional material, the control of the gate to the channel can be enhanced, a linear tunneling structure is adopted, the tunneling area is large, and the tunneling current can be effectively increased. In addition, two types of heterojunction structures are adopted, and the heterojunction interface potential barrier is small (less than 0.3eV), so that the tunneling probability is increased, and the tunneling current is improved. And a local area gate structure is adopted, and the grid only controls the heterojunction tunneling area. The heterojunction is simple to form, has no interface defect caused by lattice mismatch, and can effectively inhibit leakage current.
In a specific arrangement, the tunneling transistor further includes a gate dielectric layer and a gate metal layer, wherein the gate dielectric layer is disposed on the heterojunction, and the gate metal layer is disposed on the gate dielectric layer.
In a specific arrangement, the gate dielectric layer covers the second conductive material layer, a part of the gate dielectric layer covers the first conductive material layer, and a part of the gate dielectric layer covering the first conductive material layer is between the source electrode and the second conductive material layer. Namely, the source electrode and the second conductive material layer are insulated through the gate dielectric layer.
In the above embodiment, the tunneling transistor further includes a substrate, and the first conductive material layer is the substrate of the tunneling transistor. And a two-dimensional material is adopted as a substrate, so that the structure of the tunneling transistor is simplified.
In one embodiment, the semiconductor device further includes an insulating layer disposed on the first conductive material layer, and the insulating layer covers a portion of the second conductive material layer, and the drain electrode is insulated from the first conductive material layer by the insulating layer.
In another specific embodiment, the device further includes an insulating layer, a groove is disposed on the first conductive material layer, the insulating layer is disposed in the groove, and the drain electrode is disposed on the insulating layer and partially covers the second conductive material layer.
When the structure is specifically arranged, the drain electrode partially covers the insulating layer, and the edge of the insulating layer is exposed and uncovered, so that the insulating effect between the first conductive material layer and the drain electrode is ensured.
In one embodiment, the first conductive material layer is stacked and partially staggered with the second conductive material layer, and the second conductive material layer partially covers the first material layer; an insulating layer is arranged on the first conductive material layer, and the source electrode is insulated from the second conductive material layer through the insulating layer.
In one embodiment, the semiconductor device further includes a substrate, and the source electrode, the drain electrode, the first conductive material layer and the portion of the second conductive material layer not intersecting with the first conductive material layer are disposed on the substrate and insulated from the substrate.
In one embodiment, an isolation layer is disposed on the substrate, and the source electrode, the drain electrode, the first conductive material layer, and the portion of the second conductive material layer that is not staggered from the first conductive material layer are disposed on the isolation layer.
When a specific material is selected, the two-dimensional material can be tungsten diselenide, tin diselenide or molybdenum telluride; the three-dimensional material may be: indium arsenide or silicon.
The embodiment of the invention also provides a preparation method of the tunneling transistor, which comprises the following steps:
forming a first conductive material layer;
forming a second conductive material layer on the first conductive material layer, wherein one conductive material layer in the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is a material layer made of a two-dimensional material or a three-dimensional material;
forming a source electrode, wherein the formed source electrode is electrically connected with the first conductive material layer and is insulated from the second conductive material layer;
and forming a drain electrode which is electrically connected with the second conductive material layer and insulated from the first conductive material layer.
In the embodiment, the channel material is an atomic-level thin two-dimensional material, so that the control of the gate on the channel can be enhanced, and the tunneling current can be effectively increased due to the adoption of a linear tunneling structure and a large tunneling area. In addition, two types of heterojunction structures are adopted, and the heterojunction interface barrier is small (less than 0.3eV), so that the tunneling probability is increased, and the tunneling current is improved. And a local area gate structure is adopted, and the grid only controls the heterojunction tunneling area. The heterojunction is simple to form, has no interface defect caused by lattice mismatch, and can effectively inhibit leakage current.
In a specific arrangement, the method further comprises:
forming an insulating layer on the first conductive material layer, wherein the formed insulating layer covers a part of the second conductive material layer; when the drain electrode is formed, the formed drain electrode is positioned on the second conductive material layer and covers a part of the insulating layer.
In a specific arrangement, the method further comprises:
forming a groove in the first conductive material layer, and arranging an insulating layer in the groove; and the second conductive material layer is formed to cover a part of the insulating layer; when the drain electrode is formed, the formed drain electrode is positioned on the second conductive material layer and covers a part of the insulating layer.
In a specific arrangement, the method further comprises: an insulating layer is formed on the first conductive material layer, and the insulating layer covers a portion of the source electrode.
In a specific arrangement, before forming the first conductive material layer, the method further comprises:
manufacturing a substrate;
an isolation layer is formed on a substrate.
In a specific arrangement, the method further comprises: forming a gate dielectric layer on the second conductive material layer; and forming a grid metal layer on the grid dielectric layer.
In a specific arrangement, the method further comprises: when the gate dielectric layer is formed, the gate dielectric layer partially covers the first conductive material layer, and the part of the gate dielectric layer, which covers the first conductive material layer, is between the source electrode and the second conductive material layer.
Drawings
Fig. 1 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention;
fig. 2a to fig. 2f are flow charts of the tunnel transistor shown in fig. 1 according to the embodiment of the present invention;
fig. 3 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention;
fig. 4a to fig. 4g are flow charts of the preparation of the tunneling transistor shown in fig. 1 according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of a tunneling transistor according to another embodiment of the present invention;
fig. 6a to 6f are flow charts of the tunnel transistor shown in fig. 5 according to the embodiment of the present invention.
Reference numerals are as follows:
1-first conductive material layer 11-groove 2-source 3-second conductive material layer
4-gate metal layer 5-gate dielectric layer 6-insulating layer
7-drain 8-isolation layer 9-substrate
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments.
As shown in fig. 1 and fig. 3, fig. 1 and fig. 3 illustrate tunneling transistors with different structures according to an embodiment of the present invention.
The tunneling transistor provided in fig. 1 and 3 includes: a source 2, a drain 7 and a heterojunction; the heterojunction comprises a first conductive material layer 1 and a second conductive material layer 3 which are stacked, wherein one of the first conductive material layer 1 and the second conductive material layer 3 is made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material;
the source electrode 2 is electrically connected to the first conductive material layer 1 and insulated from the second conductive material layer 3, and the drain electrode 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.
In the implementation, the heterojunction is used as a channel, the channel material is a two-dimensional material or a three-dimensional material, the surface of the two-dimensional material has the excellent characteristics of atomic-level thinness, no dangling bonds and the like, the heterojunction based on the two-dimensional material is formed without interface defects caused by lattice mismatch, two types of heterojunction structures are adopted, the interface barrier of the heterojunction is small (less than 0.3eV), the tunneling probability is increased, and the tunneling current is improved.
Compared with the traditional tunneling transistor, the tunneling transistor based on the two-dimensional material has the advantages of stronger grid control, less interface defects, capability of effectively inhibiting leakage current, larger tunneling area and the like, and the heterojunction is formed simply, so that the manufacturing of the tunneling transistor is facilitated.
In the above embodiments, the tunneling transistor has the gate dielectric layer 5 and the gate metal layer 4, wherein the gate dielectric layer 5 is disposed on the heterojunction, and the gate metal layer 4 is disposed on the gate dielectric layer 5. The control of the grid electrode to the channel can be enhanced, a linear tunneling structure is adopted, the tunneling area is large, and the tunneling current can be effectively increased. And a local area gate structure is adopted, and the grid only controls the heterojunction tunneling area. In the above embodiments, the tunneling transistor has a substrate, and the first conductive material layer 1 is the substrate of the tunneling transistor. And a two-dimensional material is adopted as a substrate, so that the structure of the tunneling transistor is simplified.
To facilitate understanding of the tunneling transistor provided in the present embodiment, a detailed description thereof will be given below with reference to specific embodiments.
Example 1
As shown in fig. 1, in the present embodiment, the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction. Wherein the heterojunction serves as a channel structure. In a particular arrangement, the first layer of conductive material 1 in this heterojunction acts as the substrate for the entire tunnel transistor.
In specific setting, in order to avoid the contact between the drain electrode 7 and the first conductive material layer 1, the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is set, the insulating layer 6 is set on the first conductive material layer 1, and the insulating layer 6 covers a part of the second conductive material layer 3, so as to form a step structure, when the drain electrode 7 is formed on the second conductive material layer 3, a part of the drain electrode 7 covers the insulating layer 6, and through the isolation of the insulating layer 6, the situation that the drain electrode 7 is in conductive communication with the first conductive material layer 1 during processing is avoided, and the partition between the drain electrode 7 and the first conductive material layer 1 is ensured.
In a specific arrangement, the two-dimensional material (2D material) is tungsten diselenide (WSe)2) Tin diselenide (SnSe)2) Or molybdenum telluride (MoTe)2) (ii) a The three-dimensional material (3D material) is: indium arsenide (InAs) or silicon (Si). And when the two-dimensional material is adopted to manufacture the heterojunction, the two-dimensional material is a layered material, the thickness of the layered material is 0.5-10nm, such as: 0.5nm, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc. with a thickness of 0.5-10 nm.
Referring to fig. 2a to 2f, in the specific preparation, the preparation method of the tunneling transistor is as follows:
step 1: in InAs-WSe2Heterojunction TFET fabrication as an example, an n-type doped InAs substrate is provided, i.e., a first layer of conductive material 1, and the substrate is placed at 35% HF: 3Remove oxide layer in 5% HCl 1: 1 for about 2 minutes and grow CVD WSe2Transferred to an InAs substrate to obtain the structure shown in fig. 2 a.
Step 2: spin-coating photoresist on the sample obtained in the step 1, exposing and developing the sample, using the photoresist as a mask, and removing the exposed WSe by dry etching2WSe2And patterning and removing the photoresist mask. Patterned WSe, as shown in FIG. 2b2I.e. the second layer of conductive material 3.
And step 3: the source electrode 2 is formed. A photoresist is coated on the sample subjected to the step 2, the source electrode 2 area is defined by photoetching, then metal Ti/Pt/Au (about 5/20/30nm) is evaporated to form a source electrode 2 contact, and the photoresist is removed by a liftoff process. As in fig. 2 c.
And 4, step 4: an insulating layer 6 is formed. And (3) coating photoresist on the sample subjected to the step (3), defining an Oxide insulating layer 6 by adopting photoetching, growing the Oxide insulating layer 6 by adopting evaporation or ALD (atomic layer deposition), wherein the insulating layer 6 can be made of insulating materials such as silicon Oxide, aluminum Oxide and the like, and removing the photoresist by using a liftoff process. As shown in fig. 2d, an insulating layer 6 is partially covered on the second conductive material layer 3 as shown in fig. 2 d.
And 5: the drain electrode 7 is prepared. The photoresist was applied to the sample from step 4, the drain 7 region was defined by photolithography, and the metal Ti/Pt/Au (about 5/20/30nm) was evaporated to form and WSe2The connected drain 7 is contacted and the photoresist is removed using a liftoff process. A sample as shown in figure 2e was obtained.
Step 6: and forming a gate dielectric layer 5, wherein the gate dielectric layer is made of a high-K material in specific arrangement. The method comprises the following specific steps: applying photoresist on the sample obtained in the step 5, defining a gate region by photolithography, growing a high-K material hafnium oxide (or a high-K material such as aluminum oxide, zirconium oxide) by low-temperature atomic layer deposition, evaporating a gate metal (such as Ti/Au: 5/50nm), and removing the photoresist by a liftfff process to obtain a sample as shown in FIG. 2f, thereby forming a gate metal layer 4 on the gate dielectric layer 5.
The structure realized by the steps can also be realized by other similar processes, for example, the gate dielectric layer 5 and the gate metal layer 4 can be formed by firstly growing the gate dielectric layer 5 and the gate metal layer 4 and then performing wet etching by using photoresist as a mask. In addition, oxide deposition methods include, but are not limited to, ALD deposition, evaporation coating deposition.
Example 2
As shown in fig. 3, fig. 3 is a schematic structural diagram of another tunneling transistor provided in the embodiment of the present invention.
In the present embodiment, the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction. Wherein the heterojunction serves as a channel structure. In a particular arrangement, the first layer of conductive material 1 in this heterojunction acts as the substrate for the entire tunnel transistor. And the materials of the components in this embodiment are the same as those in embodiment 1, and are not described in detail here.
In specific setting, in order to avoid the contact between the drain electrode 7 and the first conductive material layer 1, the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is set, the insulating layer 6 is set on the first conductive material layer 1, specifically, the first conductive material layer 1 is provided with a groove 11, the insulating layer 6 is set in the groove 11, the drain electrode 7 is set on the second conductive material layer 3 and partially covers the insulating layer 6, and through the isolation of the insulating layer 6, the situation that the drain electrode 7 is in conductive communication with the first conductive material layer 1 during processing is avoided, and the partition between the drain electrode 7 and the first conductive material layer 1 is ensured. In order to ensure the isolation effect, preferably, the edge of the insulating layer 6 is exposed and not covered by the drain electrode 7, thereby ensuring the insulation effect.
In addition, in order to improve the insulation effect between the source electrode 2 and the second conductive material layer 3, the gate dielectric layer 5 provided in this embodiment covers the second conductive material layer 3, and the gate dielectric layer 5 partially covers the first conductive material layer 1, and the portion of the gate dielectric layer 5 covering the first conductive material layer 1 is between the source electrode 2 and the second conductive material layer 3. Namely, when the gate dielectric layer 5 is arranged, the arrangement position of one end is located outside the second conductive material layer 3, so that one end of the gate dielectric layer 5 covers the first conductive material layer 1, namely, one end of the gate dielectric layer 5 is located between the source electrode 2 and the second conductive material layer 3, and thus, the source electrode 2 and the second conductive material layer 3 are insulated through the gate dielectric layer 5. The insulation effect is improved.
Referring to fig. 4a to 4g, in the specific preparation, the preparation method of the tunneling transistor is as follows:
step 1: an insulating layer 6 is formed. Providing an n-type doped InAs substrate, which is the first conductive material layer 11, coating a photoresist on the InAs substrate, defining an Oxide insulating layer 6 by photolithography, and etching a groove 11 on the InAs substrate by Reactive Ion Etching (RIE) as shown in FIG. 4 a. The insulating layer 6 is grown by evaporation or ALD, the insulating layer 6 can be made of insulating materials such as silicon oxide and aluminum oxide, and photoresist is removed by lift off process. As shown in fig. 4 b.
Step 2: the second layer of conductive material 3 is transferred. The oxide layer was removed by placing the substrate in 35% HF: 35% HCl 1: 1 for about 2 minutes and CVD grown WSe2 was transferred to an InAs substrate. A structure as shown in figure 4c is obtained.
And step 3: and (3) spin-coating photoresist on the sample in the step (2), exposing and developing the sample, using the photoresist as a mask, removing the exposed WSe2 by using dry etching, patterning the WSe2, and removing the photoresist mask. As shown in fig. 4 d.
And 4, step 4: source and drain electrodes 7 are formed. And (3) coating photoresist on the sample subjected to the step (3), defining the region of the source and drain electrode 7 by photoetching, then evaporating metal Ti/Pt/Au (about 5/20/30nm) to form a contact of the source and drain electrode 7, and removing the photoresist by using a lift off process. As shown in fig. 4 e.
And 5: and forming a gate dielectric layer 5. And 4, coating photoresist on the sample subjected to the step 4, and defining a grid region by adopting photoetching. As shown in FIG. 4f, a high-k gate dielectric hafnium oxide (or high-k materials such as aluminum oxide and zirconium oxide) is grown by low temperature atomic layer deposition, a gate metal layer 4 (e.g., Ti/Au: 5/50nm) is evaporated, and the photoresist is removed by lift off process to obtain the sample shown in FIG. 4 g.
With continued reference to fig. 4f, in producing the gate dielectric layer 5, one end of the gate dielectric layer 5 covers the first conductive material layer 1 and is interposed between the second conductive material layer 3 and the source electrode 2.
The structure realized by the steps can also be realized by other similar processes, for example, the formation of the gate dielectric layer 5 and the gate metal layer 4 can be obtained by firstly growing the gate dielectric and the gate metal and then carrying out wet etching by using photoresist as a mask.
Example 3
As shown in fig. 5, fig. 5 is a schematic structural diagram of another tunneling transistor according to an embodiment of the present invention.
In the embodiment, the tunneling transistor comprises a source electrode 2, a drain electrode 7, a gate metal layer 4, a gate dielectric layer 5, a heterojunction, a substrate 9 and an isolation layer 8; wherein the heterojunction serves as a channel structure.
As shown in fig. 5, in the present embodiment, the tunneling transistor includes a substrate 9, the substrate 9 is a silicon substrate 9, and the source 2, the drain 7, the first conductive material layer 1, and the portion of the second conductive material layer 3 that is not intersected with the first conductive material layer 1 are disposed on the substrate 9 and are insulated from the substrate 9. Thus insulating the substrate 9 from the heterojunction, a spacer 8 is formed on the substrate 9 in order to achieve this insulation, the structure being formed on this spacer 8, in particular when provided, this spacer 8 being of silicon oxide.
In specific arrangement, the first conductive material layer 1 and the second conductive material layer 3 are arranged in a laminating way and are partially staggered, and the second conductive material layer 3 partially covers the first material layer; an insulating layer 6 is disposed on the first conductive material layer 1, and the source electrode 2 is insulated from the second conductive material layer 3 by the insulating layer 6.
For convenience of understanding the above structure, the following describes the preparation method of the tunneling transistor in detail with reference to fig. 6a to 6 f.
Step 1: providing WSe grown on a target substrate 92Materials, or WSe to be grown2The material was transferred to the spacer layer 8 on the target substrate 9 and then the WSe was aligned using a method similar to that of example 12And etching and patterning. The results shown in figure 6a were obtained.
Step 2: a source electrode 2 is prepared. A photoresist is coated on the sample subjected to the step 1, the source electrode 2 area is defined by photoetching, then metal Ti/Pt/Au (about 5/20/30nm) is evaporated to form a source electrode 2 contact, and the photoresist is removed by a liftoff process. As shown in fig. 6 b.
And step 3: an insulating layer 6 is formed. And (3) coating photoresist on the sample subjected to the step (2), defining an Oxide insulating layer 6 by adopting photoetching, growing the Oxide insulating layer 6 by adopting evaporation or ALD (atomic layer deposition), wherein the insulating layer 6 can be made of insulating materials such as silicon Oxide, aluminum Oxide and the like, and removing the photoresist by using a lift off process. This results in that a part of the insulating layer 6 covers the source electrode 2 and another part covers the first layer of conductive material 1, as shown in fig. 6 c.
And 4, step 4: transferring SnSe2A material. SnSe to be grown2The material is transferred to the substrate 9. And adopting the etching process to perform etching on the SnSe2And patterning is carried out. The result shown in fig. 6d is obtained, which is a step of generating the second conductive material layer 3, as shown in fig. 6d, the generated second conductive material layer 3 partially covers the first conductive material layer 1 and partially covers the isolation layer 8, so that the first conductive material layer 1 and the second conductive material layer 3 are stacked and partially staggered, and as shown in fig. 6d, the second conductive material layer 3 and the source electrode 2 are formed with the isolation layer 6 therebetween, so as to avoid the situation that the source electrode 2 and the second conductive material layer 3 are conducted during the processing.
And 5: the drain 7 is formed. Photoresist was applied to the sample from step 4, the drain 7 region was defined by photolithography, then metal Ti/Pt/Au (about 5/20/30nm) was evaporated to form the drain 7 contact to SnSe2, and the photoresist was removed using a liftoff process. A sample as shown in figure 6e was obtained.
And 6: and forming a gate dielectric layer 5 which is made of a high-k material. Coating photoresist on the sample obtained in the step 5, defining a grid region by photoetching, and growing high-k materials by low-temperature atomic layer deposition, wherein the high-k materials comprise: HfO2、Al2O3、ZrO2、Y2O3High k material, gate metal (e.g., Ti/Au: 5/50nm) was evaporated and photoresist was removed using lift off process to obtain the sample shown in FIG. 6 f.
The structure realized by the steps can also be realized by other similar processes, for example, the gate dielectric layer 5 and the gate metal layer 4 can be formed by firstly growing the gate dielectric layer 5 and the gate metal layer 4 and then performing wet etching by using photoresist as a mask. In addition, the oxide deposition method includes, but is not limited to, ALD deposition, and evaporation coating deposition.
As can be seen from the above description of embodiment 1 and embodiment 2, the tunneling transistor provided in this embodiment employs a heterojunction, which may be a heterojunction composed of a 2D material and a 2D material or a 2D material and a 3D material, and a channel material is controlled by a local gate. It should be understood, however, that the material of the heterojunction provided in this embodiment is not limited to the above-mentioned material, and the following materials may be adopted:
for the 2D-3D heterojunction TFET, the heterojunction material composition is InAs-WSe2、SnSe2-Si、MoTe2InAs and the like.
For a 2D-2D type heterojunction TFET, the heterojunction material composition is WSe2-SnSe2、SnSe2-MoSe2、SnSe2-MoTe2And the like.
In addition, as can be seen from the specific embodiments 1 and 2, an embodiment of the present invention further provides a method for manufacturing the tunneling transistor, where the method includes the following steps:
forming a first conductive material layer 1;
forming a second conductive material layer 3 on the first conductive material layer 1, wherein one conductive material layer is made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material;
forming a source electrode 2, wherein the formed source electrode 2 is electrically connected with the first conductive material layer 1 and insulated from the second conductive material layer 3;
a drain electrode 7 is formed, and the formed drain electrode 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.
In the technical scheme, the channel material is an atomic-scale thin two-dimensional material, the control of the gate to the channel can be enhanced, a linear tunneling structure is adopted, the tunneling area is large, and the tunneling current can be effectively increased. In addition, two types of heterojunction structures are adopted, and the heterojunction interface barrier is small (less than 0.3eV), so that the tunneling probability is increased, and the tunneling current is improved. And a local area gate structure is adopted, and the grid only controls the heterojunction tunneling area. The heterojunction is simple to form, has no interface defect caused by lattice mismatch, and can effectively inhibit leakage current.
As for the tunneling transistor in example 1, as can be seen from the description of the preparation method in example 1, the method further includes:
forming an insulating layer 6 on the first conductive material layer 1, and forming the insulating layer 6 to cover a part of the second conductive material layer 3;
when the drain electrode 7 is formed, the drain electrode 7 is formed on the second conductive material layer 3 and covers a portion of the insulating layer 6.
Forming a gate dielectric layer 5 on the second conductive material layer 3;
and forming a gate metal layer 4 on the gate dielectric layer 5.
As for the tunneling transistor in example 2, as can be seen from the description of the preparation method in example 2, the method further includes:
forming a groove in the first conductive material layer, and arranging an insulating layer in the groove; and the second conductive material layer is formed to cover a part of the insulating layer;
when the drain electrode is formed, the formed drain electrode is positioned on the second conductive material layer and covers a part of the insulating layer.
Forming a gate dielectric layer 5 on the second conductive material layer 3;
forming a grid metal layer 4 on the grid dielectric layer 5;
when the gate dielectric layer 5 is formed, the gate dielectric layer 5 partially covers the first conductive material layer 1, and the part of the gate dielectric layer 5, which covers the first conductive material layer 1, is between the source electrode 2 and the second conductive material layer 3.
As for the tunneling transistor in example 3, as can be seen from the description of the preparation method in example 3, the method further includes: before forming the first conductive material layer 1, the method further comprises:
manufacturing a substrate;
an insulating layer 6 is made on the substrate.
An insulating layer 6 is formed on the first conductive material layer 1, and the insulating layer 6 covers a portion of the source 2.
Forming a gate dielectric layer 5 on the second conductive material layer 3;
and forming a gate metal layer 4 on the gate dielectric layer 5.
The above specific preparation steps are described in detail in example 1, example 2 and example 3, and are not described in detail herein.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A tunneling transistor, comprising: a source, a drain and a heterojunction; wherein the heterojunction comprises a first conductive material layer and a second conductive material layer which are stacked;
the source electrode is electrically connected with the first conductive material layer and is insulated from the second conductive material layer, the drain electrode is electrically connected with the second conductive material layer and is insulated from the first conductive material layer, an insulating layer is arranged on the first conductive material layer, and the drain electrode is insulated from the first conductive material layer through the insulating layer;
the tunneling transistor comprises a first conductive material layer, a second conductive material layer and a substrate, wherein the first conductive material layer is a two-dimensional material layer, the second conductive material layer is a two-dimensional material layer or a three-dimensional material layer, and the first conductive material layer is the substrate of the tunneling transistor;
the two-dimensional material is tungsten diselenide, tin diselenide or molybdenum telluride; the three-dimensional material is: indium arsenide or silicon.
2. A tunneling transistor according to claim 1, further comprising a gate dielectric layer and a gate metal layer, wherein said gate dielectric layer is disposed on said heterojunction and said gate metal layer is disposed on said gate dielectric layer.
3. The tunneling transistor of claim 2, wherein the gate dielectric layer overlies the second layer of conductive material, and the gate dielectric layer partially overlies the first layer of conductive material, and the portion of the gate dielectric layer overlying the first layer of conductive material is between the source electrode and the second layer of conductive material.
4. A tunneling transistor as claimed in claim 1, wherein the insulating layer covers a portion of the second conductive material layer, and the drain is insulated from the first conductive material layer by the insulating layer.
5. The tunneling transistor of claim 1, wherein a groove is disposed on the first layer of conductive material, the insulating layer is disposed within the groove, and the drain is disposed on the insulating layer and partially covers the second layer of conductive material.
6. A method of fabricating a tunneling transistor according to claim 1, comprising the steps of:
forming a first conductive material layer;
forming a second conductive material layer on the first conductive material layer;
forming a source electrode, wherein the formed source electrode is electrically connected with the first conductive material layer and is insulated from the second conductive material layer;
and forming a drain electrode which is electrically connected with the second conductive material layer and insulated from the first conductive material layer.
7. The method of claim 6, further comprising:
forming an insulating layer on the first conductive material layer, wherein the insulating layer is formed to cover a part of the second conductive material layer;
when the drain electrode is formed, the formed drain electrode is positioned on the second conductive material layer and covers a part of the insulating layer.
8. The method of claim 6, further comprising:
forming a groove in the first conductive material layer, and arranging an insulating layer in the groove; and the second conductive material layer is formed to cover a part of the insulating layer;
when the drain electrode is formed, the formed drain electrode is positioned on the second conductive material layer and covers a part of the insulating layer.
9. The method according to any one of claims 6 to 8, further comprising:
forming a gate dielectric layer on the second conductive material layer;
and forming a grid metal layer on the grid dielectric layer.
10. The method of claim 9, wherein the gate dielectric layer is partially covered by the first conductive material layer when the gate dielectric layer is formed, and a portion of the gate dielectric layer covered between the first conductive material layer is between the source electrode and the second conductive material layer.
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| PCT/CN2016/106986 WO2018094619A1 (en) | 2016-11-23 | 2016-11-23 | Tunneling transistor and preparation method therefor |
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| KR101919425B1 (en) * | 2012-10-09 | 2018-11-19 | 삼성전자주식회사 | Tunneling field effect transistor including graphene channel |
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