CN117794257A - Ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition - Google Patents
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- 239000000463 material Substances 0.000 claims abstract description 31
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Abstract
The invention discloses an ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, and belongs to the technical field of metal-semiconductor. Comprising the following steps: the semiconductor device comprises a substrate layer structure, a semiconductor module, an insulating medium layer module, an electrode module and a top layer structure; the semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module; the insulating medium layer module is positioned at one end above the semiconductor structure; the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module; the top layer structure is positioned above the insulating medium layer module; the semiconductor module is made of a two-dimensional semiconductor material; the insulating dielectric layer module is made of dielectric materials; the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material; atoms in the two-dimensional semi-metal electrode material are combined through covalent bonds, and Van der Waals stacking is adopted between the two-dimensional semi-metal electrode material and the two-dimensional semi-metal electrode material. The invention is beneficial to the structural design and optimization of the thyristor based on the two-dimensional semiconductor and expands the application of the novel semiconductor material.
Description
Technical Field
The invention belongs to the technical field of metal-semiconductors, and particularly relates to an ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition.
Background
With the development of moore's law, the number of transistors that can be accommodated in an integrated circuit is doubled every 18 months to 24 months, and the power consumption is increased while the density and performance of transistors are improved. Especially, in the late Moore age, the problem of power consumption of the semiconductor device becomes more prominent on a technical node of sub-ten nanometers; the mobility of the silicon-based device is sharply reduced and the transmission efficiency is deteriorated under the scale approaching the physical limit; the traditional silicon-based doping process can damage the bulk material, so that the defect states among interfaces are more, and the contact resistance is increased; as the dimensions shrink, the area of the channel depletion layer decreases to a trapezoidal area, resulting in a decrease in majority carrier concentration, and the gate voltage required for carrier inversion in the channel depletion layer region decreases, making the device more difficult to shut down, increasing leakage current, which all cause a dramatic increase in device power consumption. New structures such as Fin FET, GAA, etc. have been designed to slow the continued scaling of transistors. However, increasingly severe short channel effects continue to limit the further development of integrated circuits, microelectronic devices enter the technology node below 10nm and approach its fundamental limits, requiring new channel materials to continue scaling the device dimensions while maintaining superior performance. Compared with the traditional silicon substrate material semiconductor, the two-dimensional material comprises N-type, P-type and bipolar semiconductor materials in the aspect of variety advantage, so that the problem of material damage caused by high-temperature diffusion and ion implantation doping modification in the silicon substrate process can be completely avoided; in structural advantage, the two-dimensional material has atomic-level thickness, which is favorable for grid regulation and control, and the surface has no dangling bond, so that the capture of electrons at an interface can be effectively reduced; on the device construction advantage, vertical construction can be carried out through Van der Waals force between two-dimensional materials, and heterogeneous integration is simplified; in terms of performance advantages, the mobility of the two-dimensional material is not greatly changed along with the thickness of the layer number under the limit scale, and is far higher than that of a silicon-based material below 5 nanometers. Thus, two-dimensional semiconductor materials are considered as one of the most potential material systems for developing low power devices.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides an ultrathin short-channel tunneling thyristor structure based on a two-dimensional device, which adopts vertical MoS unlike a common two-dimensional planar transistor 2 /WSe 2 The junction and the in-plane channel realize the switch state through the gate control barrier height of the heterojunction, and realize the conversion of the hot electron emission and the tunnel transmission mechanism. The device utilizes high-speed tunnel current and a unique short channel structure, and solves the problems of voltage spike, long reverse recovery time and the like of a common electronic device, thereby obtaining access to an IC interface. The invention provides a double-gate modulation-based concept verification type thyristor structure, which opens up a wide prospectAnd (3) prospect.
In order to achieve the above object, the present invention provides the following solutions:
an ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition, comprising: the semiconductor device comprises a substrate layer structure, a semiconductor module, an insulating medium layer module, an electrode module and a top layer structure;
the semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module;
the insulating medium layer module is positioned at one end above the semiconductor structure;
the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module;
the top layer structure is positioned above the insulating medium layer module;
the semiconductor module is made of a two-dimensional semiconductor material;
the insulating medium layer module is made of dielectric materials;
the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material; atoms in the two-dimensional semi-metal electrode material are combined through covalent bonds, and Van der Waals stacking is adopted between the two-dimensional semi-metal electrode material layers.
Further preferably, the thickness of the two-dimensional semiconductor material is 0.7-10nm, the thickness of the dielectric material is 5-10nm, the thickness of the two-dimensional semi-metal electrode material is 10-20nm, and the thickness of the conventional metal electrode material is 40-50nm.
Further preferably, the two-dimensional semiconductor material is a transition metal chalcogenide MX 2 And graphene; m is a transition metal element, and X is a chalcogen element.
Further preferably, the dielectric material is h-BN, hfO 2 、ZrO 2 、Hf x Zr 1-x O 2 One of them.
Further preferably, the conventional metal electrode material is one of Cr/Au, ti/Au, ag/Au, au.
Further preferably, the two-dimensional semi-metal electrode material is 1T' -MoTe 2 、1T’-WTe 2 、1T-PtSe 2 、2H-NbSe 2 、1T’-Te Se 2 、1T’-Ti S 2 、1T-Hf Te 2 、1T-Ti Te 2 、1T’-WS 2 And Pt Te 2 One of them.
The invention also provides an ultrathin short-channel tunneling thyristor based on two-dimensional device composition, which adopts the thyristor structure and comprises the following components: a substrate layer structure, a top layer structure; the semiconductor module includes: graphene layer, moS 2 Layer and WSe 2 The layer, insulating medium layer module includes: the h-BN layer and electrode module includes: 1T' -MoTe 2 A layer and an Au layer;
the top layer structure is made of a metal material;
the graphene layer and MoS 2 The layers are sequentially positioned above the substrate layer, and the graphene layer and MoS 2 A gap is arranged in the middle of the layer;
the WSe 2 The layer is positioned on the MoS 2 One side above the layer and across the gap;
the h-BN layer is positioned at the WSe 2 Over the layer and fully covered;
the 1T' -MoTe 2 The layer is positioned on the MoS 2 The other side above the layer and not crossing the gap, with the WSe 2 The layers are not connected;
the Au layer is positioned on the 1T' -MoTe 2 Above the layer.
The invention also provides a method for preparing the ultrathin short-channel tunneling thyristor based on the two-dimensional device composition, which comprises the following steps:
material preparation: preparing single-layer or less-layer MoS by chemical vapor deposition 2 The method comprises the steps of carrying out a first treatment on the surface of the The mechanical stripping method is adopted to obtain a few-layer h-BN and 1T' -MoTe 2 WSe 2 The method comprises the steps of carrying out a first treatment on the surface of the A small amount of graphene layer is peeled off on the substrate layer structure;
etching: cutting MoS using focused ion beam technology 2 The layer and the graphene layer are used for preparing a nano gap of about 50nm to separate a source electrode terminal from a drain electrode terminal;
electrode deposition: a small amount of graphene layer is stripped on the substrate layer structure and is used as a contact electrode, and the electrode of the thyristor is deposited by combining electron beam lithography and thermal evaporation;
and (3) accurate transfer: graphene layer as contact electrode, moS 2 The layer is used as an n-type carrier transmission channel to be transferred to the top of the graphene layer, and the WSe is a few layer 2 Stacked on top of the gap; transfer of h-BN layer to WSe 2 The upper part of the layer is used as a top gate dielectric covering device; 1T' -MoTe 2 MoS with layer transferred to one side 2 On the layer, finally, the metal Au layer is transferred to 1T' -MoTe by using a sacrificial layer auxiliary method 2 On the layer;
vacuum annealing: annealing in a vacuum environment to obtain the ultrathin short-channel tunneling thyristor.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides an ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, in the structure, graphene is used as a source electrode terminal and a drain electrode terminal, a few-layer h-BN is used as a top dielectric insulator, and a transmission channel is formed by back-to-back vertical MoS 2 /WSe 2 Junction and plane WSe 2 The channel composition, the van der Waals heterojunction formed by stacking the two-dimensional semi-metal electrode material and the two-dimensional semiconductor material has no limitation of lattice matching and processing compatibility requirements of the traditional bonding heterojunction, and the Schottky barrier height formed by the contact region weakens the strong Fermi pinning effect. Unlike a typical two-dimensional field effect thyristor, the switching behavior of such a thyristor relies on the band modulation of the vertical p-n junction by the double gate, resulting in a transition in the transport mechanism between thermionic emission and tunneling. The thyristor structure design and optimization based on the two-dimensional semiconductor are facilitated, and the application of the novel semiconductor material is expanded.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the embodiments are briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a novel two-dimensional semiconductor material thyristor provided by the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Embodiment one:
as shown in fig. 1, this embodiment provides an ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, including: substrate layer structure, semiconductor module, insulating dielectric layer module, electrode module and top layer structure. The semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module; the insulating medium layer module is positioned at one end above the semiconductor structure; the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module. The top layer structure is located above the insulating medium layer module. The semiconductor module is made of a two-dimensional semiconductor material; the insulating dielectric layer module is made of dielectric materials; the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material. The two-dimensional semi-metal electrode material is a novel low-dimensional material with nano-scale on one scale, atoms in the plane are combined through covalent bonds with strong acting force, and two adjacent layers of materials are stacked through van der Waals force coupling with weak acting force.
Wherein the thickness of the two-dimensional semiconductor material is 0.7-10nm, the thickness of the dielectric material is 5-10nm, the thickness of the two-dimensional semi-metal electrode material is 10-20nm, and the thickness of the traditional metal electrode material is 40-50nm.
Further, the two-dimensional semiconductor material adopts transition metal chalcogenide MX 2 And graphene;m is a transition metal element, mo, W and the like; x is chalcogen element, S, se, te, etc. The two-dimensional semiconductor material is prepared by one of mechanical stripping, chemical vapor deposition, organic auxiliary vapor deposition, physical vapor deposition and magnetron sputtering methods. The dielectric material is h-BN, hfO 2 、ZrO 2 、Hf x Zr 1-x O 2 One of them. The dielectric material is prepared by one of mechanical lift-off, atomic layer deposition methods. The traditional metal electrode material is one of Cr/Au, ti/Au, ag/Au and Au. The traditional metal electrode material is prepared by one of thermal evaporation, electron beam evaporation and magnetron sputtering methods. The two-dimensional semi-metal electrode material is 1T' -MoTe 2 、1T’-WTe 2 、1T-PtSe 2 、2H-NbSe 2 、1T’-Te Se 2 、1T’-Ti S 2 、1T-Hf Te 2 、1T-Ti Te 2 、1T’-WS 2 And Pt Te 2 One of them.
Embodiment two:
the embodiment provides an ultrathin short-channel tunneling thyristor based on two-dimensional device composition, which adopts the thyristor structure and comprises: a substrate layer structure, a top layer structure; the semiconductor module includes: graphene layer, moS 2 Layer and WSe 2 The layer, insulating medium layer module includes: the h-BN layer and electrode module includes: 1T' -MoTe 2 A layer and an Au layer.
The top layer structure is made of metal materials. Graphene layer and MoS 2 The layers are sequentially positioned above the substrate layer, and the graphene layer and MoS 2 A gap is arranged in the middle of the layer; WSe (Wireless sensor set) 2 The layer is located at MoS 2 One side above the layer and across the gap; the h-BN layer is located at WSe 2 Over the layer and fully covered; 1T' -MoTe 2 The layer is located at MoS 2 The other side above the layer, and not across the gap, with WSe 2 The layers are not connected; the Au layer is located at 1T' -MoTe 2 Above the layer.
Embodiment III:
the embodiment provides a preparation method of an ultrathin short-channel tunneling thyristor, which comprises the following steps:
material preparation: by chemical vapor depositionMethod for preparing single-layer or less-layer MoS by using accumulation method 2 The method comprises the steps of carrying out a first treatment on the surface of the The mechanical stripping method is adopted to obtain a few-layer h-BN and 1T' -MoTe 2 WSe 2 The method comprises the steps of carrying out a first treatment on the surface of the A small amount of graphene layer is formed on 300nm SiO 2 And stripping off the Si substrate layer structure.
Etching: cutting MoS using focused ion beam technology 2 The layer and the graphene layer, a nanogap of approximately 50nm was prepared to separate the source and drain terminals.
Electrode deposition: a small amount of graphene layer is firstly formed on 300nm SiO 2 The Si substrate layer is structurally peeled off and can be used as a contact electrode due to the extraordinary fluidity and the smooth contact interface of atoms. The electrodes of the thyristors are deposited by electron beam lithography in combination with thermal evaporation.
And (3) accurate transfer: graphene layer as contact electrode, moS 2 The layer is transferred to the top of the graphene layer as an n-type carrier transmission channel, and is taken as a typical bipolar two-dimensional semiconductor, and the WSe is a few-layer 2 Stacked on top of the gap; transfer of h-BN layer with high k and wide bandgap to WSe 2 The upper part of the layer is used as a top gate dielectric to cover the device to improve interface contact; 1T' -MoTe 2 MoS with layer exactly transferred to one side 2 On the layer, finally, the metal Au layer is transferred to 1T' -MoTe by using a sacrificial layer auxiliary method 2 On the layer.
Vacuum annealing: annealing in a vacuum environment, strengthening Van der Waals bonding and contact between materials, and obtaining the ultrathin short-channel tunneling thyristor.
The above embodiments are merely illustrative of the preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, but various modifications and improvements made by those skilled in the art to which the present invention pertains are made without departing from the spirit of the present invention, and all modifications and improvements fall within the scope of the present invention as defined in the appended claims.
Claims (8)
1. An ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, which is characterized by comprising: the semiconductor device comprises a substrate layer structure, a semiconductor module, an insulating medium layer module, an electrode module and a top layer structure;
the semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module;
the insulating medium layer module is positioned at one end above the semiconductor structure;
the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module;
the top layer structure is positioned above the insulating medium layer module;
the semiconductor module is made of a two-dimensional semiconductor material;
the insulating medium layer module is made of dielectric materials;
the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material; atoms in the two-dimensional semi-metal electrode material are combined through covalent bonds, and Van der Waals stacking is adopted between the two-dimensional semi-metal electrode material layers.
2. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein the thickness of said two-dimensional semiconductor material is 0.7-10nm, the thickness of said dielectric material is 5-10nm, the thickness of said two-dimensional semi-metal electrode material is 10-20nm, and the thickness of said conventional metal electrode material is 40-50nm.
3. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said two-dimensional semiconductor material is transition metal chalcogenide MX 2 And graphene; m is a transition metal element, and X is a chalcogen element.
4. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said dielectric material is h-BN, hfO 2 、ZrO 2 、Hf x Zr 1-x O 2 One of them.
5. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said conventional metal electrode material is one of Cr/Au, ti/Au, ag/Au, au.
6. The ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein the two-dimensional semi-metal electrode material is 1T' -MoTe 2 、1T’-WTe 2 、1T-PtSe 2 、2H-NbSe 2 、1T’-Te Se 2 、1T’-Ti S 2 、1T-Hf Te 2 、1T-Ti Te 2 、1T’-WS 2 And Pt Te 2 One of them.
7. An ultrathin short-channel tunneling thyristor based on two-dimensional device composition, adopting the thyristor structure of any one of claims 1-6, comprising: a substrate layer structure, a top layer structure; the semiconductor module includes: graphene layer, moS 2 Layer and WSe 2 The layer, insulating medium layer module includes: the h-BN layer and electrode module includes: 1T' -MoTe 2 A layer and an Au layer;
the top layer structure is made of a metal material;
the graphene layer and MoS 2 The layers are sequentially positioned above the substrate layer, and the graphene layer and MoS 2 A gap is arranged in the middle of the layer;
the WSe 2 The layer is positioned on the MoS 2 One side above the layer and across the gap;
the h-BN layer is positioned at the WSe 2 Over the layer and fully covered;
the 1T' -MoTe 2 The layer is positioned on the MoS 2 The other side above the layer and not crossing the gap, with the WSe 2 The layers are not connected;
the Au layer is positioned on the 1T' -MoTe 2 Above the layer.
8. A method for preparing the ultra-thin short channel tunneling thyristor based on two-dimensional device composition as claimed in claim 7, comprising the steps of:
material preparation: preparing single-layer or less-layer MoS by chemical vapor deposition 2 The method comprises the steps of carrying out a first treatment on the surface of the The mechanical stripping method is adopted to obtain a few-layer h-BN and 1T' -MoTe 2 WSe 2 The method comprises the steps of carrying out a first treatment on the surface of the A small amount of graphene layer is peeled off on the substrate layer structure;
etching: cutting MoS using focused ion beam technology 2 The layer and the graphene layer are used for preparing a nano gap of about 50nm to separate a source electrode terminal from a drain electrode terminal;
electrode deposition: a small amount of graphene layer is stripped on the substrate layer structure and is used as a contact electrode, and the electrode of the thyristor is deposited by combining electron beam lithography and thermal evaporation;
and (3) accurate transfer: graphene layer as contact electrode, moS 2 The layer is used as an n-type carrier transmission channel to be transferred to the top of the graphene layer, and the WSe is a few layer 2 Stacked on top of the gap; transfer of h-BN layer to WSe 2 The upper part of the layer is used as a top gate dielectric covering device; 1T' -MoTe 2 MoS with layer transferred to one side 2 On the layer, finally, the metal Au layer is transferred to 1T' -MoTe by using a sacrificial layer auxiliary method 2 On the layer;
vacuum annealing: annealing in a vacuum environment to obtain the ultrathin short-channel tunneling thyristor.
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