CN117794257A - An ultra-thin short-channel tunneling thyristor structure based on two-dimensional devices - Google Patents

Abstract

The invention discloses an ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, and belongs to the technical field of metal-semiconductor. Comprising the following steps: the semiconductor device comprises a substrate layer structure, a semiconductor module, an insulating medium layer module, an electrode module and a top layer structure; the semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module; the insulating medium layer module is positioned at one end above the semiconductor structure; the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module; the top layer structure is positioned above the insulating medium layer module; the semiconductor module is made of a two-dimensional semiconductor material; the insulating dielectric layer module is made of dielectric materials; the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material; atoms in the two-dimensional semi-metal electrode material are combined through covalent bonds, and Van der Waals stacking is adopted between the two-dimensional semi-metal electrode material and the two-dimensional semi-metal electrode material. The invention is beneficial to the structural design and optimization of the thyristor based on the two-dimensional semiconductor and expands the application of the novel semiconductor material.

Description

An ultra-thin short-channel tunneling thyristor structure based on two-dimensional devices

Technical field

The invention belongs to the field of metal-semiconductor technology, and specifically relates to an ultra-thin short-channel tunneling thyristor structure composed of two-dimensional devices.

Background technique

With the development of Moore's Law, the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 to 24 months. While transistor density and performance are improved, power consumption will also increase. Especially in the post-Moore era, the power consumption problem of semiconductor devices has become more prominent at the sub-ten-nanometer technology node; the mobility of silicon-based devices drops sharply and the transmission efficiency deteriorates at a scale close to the physical limit; the traditional silicon-based doping process will damage the body material, resulting in more defect states between interfaces, leading to increased contact resistance; as the size shrinks, the area of the channel depletion layer is reduced to a trapezoidal area, resulting in a decrease in the majority carrier concentration, and a decrease in the gate voltage required for carrier inversion in the channel depletion layer region, making the device more difficult to turn off and increasing leakage current. These factors will lead to a sharp increase in device power consumption. People have designed new structures such as FinFET and GAA to delay the continuous miniaturization of transistors. However, the increasingly serious short channel effect has always restricted the further development of integrated circuits. Microelectronic devices have entered the technology node below 10nm and are close to their basic limits. New channel materials are needed to continue to scale device size while maintaining superior performance. Compared with traditional silicon-based semiconductors, two-dimensional materials have advantages in variety, including N-type, P-type and bipolar semiconductor materials, which can completely avoid the material damage caused by high-temperature diffusion and ion implantation in silicon-based processes; in terms of structural advantages, two-dimensional materials have atomic-level thickness, which is conducive to gate regulation, and there are no dangling bonds on the surface, which can effectively reduce the capture of electrons at the interface; in terms of device construction advantages, they can be vertically constructed through the van der Waals force between two-dimensional materials, simplifying heterogeneous integration; in terms of performance advantages, at the extreme scale, the mobility of two-dimensional materials does not change much with the thickness of the layer, which is much higher than the mobility of silicon-based materials below 5 nanometers. Therefore, two-dimensional semiconductor materials are considered to be one of the most promising material systems for the development of low-power devices.

Contents of the invention

The present invention aims to solve the deficiencies of the prior art and proposes an ultra-thin short-channel tunneling thyristor structure based on a two-dimensional device composition. Unlike the usual two-dimensional planar transistor, the device uses a vertical _MoS2 / _WSe2 junction and an in-plane channel to achieve the switching state through the gate-controlled barrier height of the heterojunction, realizing the conversion of thermal electron emission and tunneling transport mechanisms. The device utilizes high-speed tunneling current and a unique short-channel structure to overcome the problems of voltage spikes and long reverse recovery time existing in ordinary electronic devices, thereby gaining access to IC interfaces. The present invention provides a proof-of-concept thyristor structure based on dual-gate modulation, opening up a promising prospect.

In order to achieve the above objects, the present invention provides the following solutions:

An ultra-thin short-channel tunneling thyristor structure based on two-dimensional devices, including: substrate layer structure, semiconductor module, insulating dielectric layer module, electrode module and top layer structure;

The semiconductor module is located above the substrate layer structure with a gap in between;

The insulating dielectric layer module is located at one end above the semiconductor structure;

The electrode module is located at the other end above the semiconductor structure and is not connected to the insulating dielectric layer module;

The top structure is located above the insulating dielectric layer module;

The semiconductor module uses two-dimensional semiconductor material;

The insulating medium layer module is made of dielectric material;

The electrode module uses two-dimensional semi-metal electrode materials and traditional metal electrode materials; the atoms in the plane of the two-dimensional semi-metal electrode material are bonded through covalent bonds, and van der Waals stacking is used between layers.

Further preferably, the thickness of the two-dimensional semiconductor material is 0.7-10 nm, the thickness of the dielectric material is 5-10 nm, the thickness of the two-dimensional semi-metal electrode material is 10-20 nm, and the thickness of the traditional metal electrode material is Thickness is 40-50nm.

Further preferably, the two-dimensional semiconductor material uses transition metal chalcogen compound MX ₂ and graphene; M is a transition metal element, and X is a chalcogen element.

Further preferably, the dielectric material is one of h-BN, HfO ₂ , ZrO ₂ , and Hf _x Zr _1-x O ₂ .

Further preferably, the traditional metal electrode material is one of Cr/Au, Ti/Au, Ag/Au, and Au.

Further preferably, the two-dimensional semi-metal electrode material is 1T'-MoTe ₂ , 1T'-WTe ₂ , 1T-PtSe ₂ , 2H-NbSe ₂ , 1T'-Te Se ₂ , 1T'-Ti S ₂ , 1T One of -Hf Te ₂ , 1T-Ti Te ₂ , 1T'-WS ₂ and Pt Te ₂ .

The invention also provides an ultra-thin short-channel tunneling thyristor based on two-dimensional devices, using the above-mentioned thyristor structure, including: a substrate layer structure and a top layer structure; the semiconductor module includes: a graphene layer, MoS ₂ layers and WSe ₂ layers , The insulating dielectric layer module includes: h-BN layer, the electrode module includes: 1T'-MoTe ₂ layers and Au layer;

The top layer structure is made of metal material;

The graphene layer and the MoS ₂ layer are located above the substrate layer in sequence, and there is a gap between the graphene layer and the MoS ₂ layer;

The WSe ₂ layer is located on one side above the MoS ₂ layer and spans the gap;

The h-BN layer is located above the WSe ₂ layer and fully covers it;

The 1T'-MoTe ₂ layer is located on the other side above the MoS ₂ layer and does not cross the gap and is not connected to the WSe ₂ layer;

The Au layer is located above the 1T'-MoTe ₂ layer.

The invention also provides a method for preparing an ultra-thin short-channel tunneling thyristor composed of two-dimensional devices, including:

Material preparation: Single-layer or few-layer MoS ₂ is prepared by chemical vapor deposition method; few-layer h-BN, 1T'-MoTe ₂ and WSe ₂ are obtained by mechanical exfoliation method; a small amount of graphene layer is peeled off on the substrate layer structure;

Etching: Use focused ion beam technology to cut the MoS ₂ layer and the graphene layer to prepare a nanogap of ≈50nm to separate the source and drain terminals;

Electrode deposition: A small amount of graphene layer is peeled off on the substrate layer structure to serve as a contact electrode, and the electrode of the thyristor is deposited by electron beam lithography combined with thermal evaporation;

Precise transfer: the graphene layer serves as a contact electrode, the MoS ₂ layer serves as an n-type carrier transmission channel and is transferred to the top of the graphene layer, and a few layers of WSe ₂ are stacked on top of the gap; the h-BN layer is transferred to the top of the WSe ₂ layer, As a top gate dielectric covering device; transfer the 1T'-MoTe ₂ layer to the MoS ₂ layer on one side, and finally use the sacrificial layer assisted method to transfer the metal Au layer to the 1T'-MoTe ₂ layer;

Vacuum annealing: annealing in a vacuum environment to obtain the ultra-thin short channel tunneling thyristor.

Compared with the prior art, the beneficial effects of the present invention are:

The invention provides an ultra-thin short-channel tunneling thyristor structure based on two-dimensional devices. In this structure, graphene serves as the source and drain terminals, few layers of h-BN serve as the top dielectric insulator, and the transmission channel is composed of back-to-back Composed of a vertical MoS ₂ /WSe ₂ junction and a planar WSe ₂ channel, the van der Waals heterojunction formed by stacking two-dimensional semi-metal electrode materials and two-dimensional semiconductor materials does not have the limitations of lattice matching and processing compatibility requirements of traditional bonded heterojunctions. , the Schottky barrier height formed in the contact area weakens the strong Fermi pinning effect. Unlike usual two-dimensional field-effect thyristors, the switching behavior of this thyristor relies on frequency band modulation of the vertical pn junction through dual gates, resulting in a shift in the transport mechanism between thermionic emission and tunneling. It contributes to the design and optimization of thyristor structures based on two-dimensional semiconductors and expands the application of new semiconductor materials.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions of the present invention more clearly, the drawings required to be used in the embodiments are briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary people in the art, Technical personnel can also obtain other drawings based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of a new two-dimensional semiconductor material thyristor provided by the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In order to make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

Example 1:

As shown in Figure 1, this embodiment provides an ultra-thin short-channel tunneling thyristor structure based on two-dimensional devices, including: a substrate layer structure, a semiconductor module, an insulating dielectric layer module, an electrode module, and a top-level structure. The semiconductor module is located above the substrate layer structure with a gap in the middle; the insulating dielectric layer module is located at one end above the semiconductor structure; the electrode module is located at the other end above the semiconductor structure and is not connected to the insulating dielectric layer module. The top structure is located above the insulating dielectric layer module. The semiconductor module uses two-dimensional semiconductor materials; the insulating dielectric layer module uses dielectric materials; the electrode module uses two-dimensional semi-metal electrode materials and traditional metal electrode materials. The two-dimensional semi-metal electrode material is a new low-dimensional material with a scale of nanometers. In-plane atoms are bonded through strong covalent bonds, and two adjacent layers of materials are stacked using van der Waals coupling coupling with weak forces.

Among them, the thickness of two-dimensional semiconductor materials is 0.7-10nm, the thickness of dielectric materials is 5-10nm, the thickness of two-dimensional semi-metal electrode materials is 10-20nm, and the thickness of traditional metal electrode materials is 40-50nm.

Further, the two-dimensional semiconductor material uses transition metal chalcogenide MX ₂ and graphene; M is a transition metal element, such as Mo, W, etc.; X is a chalcogen element, such as S, Se, Te, etc. Two-dimensional semiconductor materials are prepared by one of mechanical exfoliation, chemical vapor deposition, organic-assisted vapor deposition, physical vapor deposition, and magnetron sputtering. The dielectric material is one of h-BN, HfO ₂ , ZrO ₂ , and Hf _x Zr _1-x O ₂ . Dielectric materials are prepared by one of mechanical exfoliation and atomic layer deposition methods. Traditional metal electrode materials are one of Cr/Au, Ti/Au, Ag/Au, and Au. Traditional metal electrode materials are prepared by one of thermal evaporation, electron beam evaporation, and magnetron sputtering. Two-dimensional semi-metal electrode materials are 1T'-MoTe ₂ , 1T'-WTe ₂ , 1T-PtSe ₂ , 2H-NbSe ₂ , 1T'-Te Se ₂ , 1T'-Ti S ₂ , 1T-Hf Te ₂ , 1T -One of Ti Te ₂ , 1T'-WS ₂ and Pt Te ₂ .

Example 2:

This embodiment provides an ultra-thin short-channel tunneling thyristor based on two-dimensional devices, using the above-mentioned thyristor structure, including: a substrate layer structure and a top layer structure; the semiconductor module includes: a graphene layer, a MoS ₂ layer, and a WSe ₂ layer. The insulating dielectric layer module includes: h-BN layer, and the electrode module includes: 1T'-MoTe ₂ layers and Au layer.

The top structure is made of metal. The graphene layer and the MoS ₂ layer are located above the substrate layer in sequence, and there is a gap between the graphene layer and the MoS ₂ layer; the WSe ₂ layer is located on one side above the MoS ₂ layer and spans the gap; the h-BN layer is located on the WSe ₂ layer above, and fully covered; the 1T'-MoTe ₂ layer is located on the other side above the MoS ₂ layer, and does not cross the gap, and is not connected to the WSe ₂ layer; the Au layer is located above the 1T'-MoTe ₂ layer.

Embodiment three:

This embodiment provides a method for preparing an ultra-thin short channel tunneling thyristor. The steps of the preparation method include:

Material preparation: Single-layer or few-layer MoS ₂ is prepared by chemical vapor deposition method; few-layer h-BN, 1T'-MoTe ₂ and WSe ₂ are obtained by mechanical exfoliation method; a small amount of graphene layer is placed on the 300nm SiO ₂ /Si substrate layer Structurally stripped.

Etching: Focused ion beam technology is used to cut the MoS ₂ layer and the graphene layer to prepare a nanogap of ≈50nm to separate the source and drain terminals.

Electrode deposition: A small amount of graphene layer is first peeled off on the 300nm SiO ₂ /Si substrate layer structure, which can be used as a contact electrode due to its extraordinary fluidity and atomically smooth contact interface. The electrodes of the thyristor are deposited by electron beam lithography combined with thermal evaporation.

Precise transfer: the graphene layer serves as a contact electrode, and the MoS ₂ layer serves as an n-type carrier transmission channel and is transferred to the top of the graphene layer. As a typical bipolar two-dimensional semiconductor, a few layers of WSe ₂ are stacked on the top of the gap; The h-BN layer with high k and wide bandgap is transferred to the WSe ₂ layer as a top gate dielectric covering device to improve the interface contact; the 1T'-MoTe ₂ layer is accurately transferred to the MoS ₂ layer on one side, and finally the sacrificial device is used The layer-assisted method transfers the metallic Au layer onto the 1T'-MoTe ₂ layer.

Vacuum annealing: Annealing in a vacuum environment strengthens the van der Waals bonding and contact between materials to obtain ultra-thin short-channel tunneling thyristors.

The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should fall within the protection scope determined by the claims of the present invention.

Claims (8)

1. An ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition, which is characterized by comprising: the semiconductor device comprises a substrate layer structure, a semiconductor module, an insulating medium layer module, an electrode module and a top layer structure;

the semiconductor module is positioned above the substrate layer structure, and a gap is formed in the middle of the semiconductor module;

the insulating medium layer module is positioned at one end above the semiconductor structure;

the electrode module is positioned at the other end above the semiconductor structure and is not connected with the insulating medium layer module;

the top layer structure is positioned above the insulating medium layer module;

the semiconductor module is made of a two-dimensional semiconductor material;

the insulating medium layer module is made of dielectric materials;

the electrode module adopts a two-dimensional semi-metal electrode material and a traditional metal electrode material; atoms in the two-dimensional semi-metal electrode material are combined through covalent bonds, and Van der Waals stacking is adopted between the two-dimensional semi-metal electrode material layers.

2. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein the thickness of said two-dimensional semiconductor material is 0.7-10nm, the thickness of said dielectric material is 5-10nm, the thickness of said two-dimensional semi-metal electrode material is 10-20nm, and the thickness of said conventional metal electrode material is 40-50nm.

3. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said two-dimensional semiconductor material is transition metal chalcogenide MX ₂ And graphene; m is a transition metal element, and X is a chalcogen element.

4. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said dielectric material is h-BN, hfO ₂ 、ZrO ₂ 、Hf _x Zr _1-x O ₂ One of them.

5. The ultra-thin short channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein said conventional metal electrode material is one of Cr/Au, ti/Au, ag/Au, au.

6. The ultrathin short-channel tunneling thyristor structure based on two-dimensional device composition according to claim 1, wherein the two-dimensional semi-metal electrode material is 1T' -MoTe ₂ 、1T’-WTe ₂ 、1T-PtSe ₂ 、2H-NbSe ₂ 、1T’-Te Se ₂ 、1T’-Ti S ₂ 、1T-Hf Te ₂ 、1T-Ti Te ₂ 、1T’-WS ₂ And Pt Te ₂ One of them.

7. An ultrathin short-channel tunneling thyristor based on two-dimensional device composition, adopting the thyristor structure of any one of claims 1-6, comprising: a substrate layer structure, a top layer structure; the semiconductor module includes: graphene layer, moS ₂ Layer and WSe ₂ The layer, insulating medium layer module includes: the h-BN layer and electrode module includes: 1T' -MoTe ₂ A layer and an Au layer;

the top layer structure is made of a metal material;

the graphene layer and MoS ₂ The layers are sequentially positioned above the substrate layer, and the graphene layer and MoS ₂ A gap is arranged in the middle of the layer;

the WSe ₂ The layer is positioned on the MoS ₂ One side above the layer and across the gap;

the h-BN layer is positioned at the WSe ₂ Over the layer and fully covered;

the 1T' -MoTe ₂ The layer is positioned on the MoS ₂ The other side above the layer and not crossing the gap, with the WSe ₂ The layers are not connected;

the Au layer is positioned on the 1T' -MoTe ₂ Above the layer.

8. A method for preparing the ultra-thin short channel tunneling thyristor based on two-dimensional device composition as claimed in claim 7, comprising the steps of:

material preparation: preparing single-layer or less-layer MoS by chemical vapor deposition ₂ The method comprises the steps of carrying out a first treatment on the surface of the The mechanical stripping method is adopted to obtain a few-layer h-BN and 1T' -MoTe ₂ WSe ₂ The method comprises the steps of carrying out a first treatment on the surface of the A small amount of graphene layer is peeled off on the substrate layer structure;

etching: cutting MoS using focused ion beam technology ₂ The layer and the graphene layer are used for preparing a nano gap of about 50nm to separate a source electrode terminal from a drain electrode terminal;

electrode deposition: a small amount of graphene layer is stripped on the substrate layer structure and is used as a contact electrode, and the electrode of the thyristor is deposited by combining electron beam lithography and thermal evaporation;

and (3) accurate transfer: graphene layer as contact electrode, moS ₂ The layer is used as an n-type carrier transmission channel to be transferred to the top of the graphene layer, and the WSe is a few layer ₂ Stacked on top of the gap; transfer of h-BN layer to WSe ₂ The upper part of the layer is used as a top gate dielectric covering device; 1T' -MoTe ₂ MoS with layer transferred to one side ₂ On the layer, finally, the metal Au layer is transferred to 1T' -MoTe by using a sacrificial layer auxiliary method ₂ On the layer;

vacuum annealing: annealing in a vacuum environment to obtain the ultrathin short-channel tunneling thyristor.