CN105742345A - Tunneling field-effect transistor and preparation method therefor - Google Patents
Tunneling field-effect transistor and preparation method therefor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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Abstract
The invention belongs to the technical field of a transistor, and specifically relates to a tunneling field-effect transistor and a preparation method therefor. The tunneling field-effect transistor comprises a two-dimensional material layer, a metal source electrode and a metal drain electrode, and a first gate stack, wherein the metal source electrode and the metal drain electrode are positioned on the two sides of the two-dimensional material layer respectively; the metal source electrode and the metal drain electrode have different work functions, and form electric contact having opposite polarities with that of the two-dimensional material layer; the first gate stack is positioned on the surface of the two-dimensional material layer; and the first gate stack comprises a first gate dielectric layer and a first gate electrode layer, wherein the first gate dielectric layer is positioned between the two-dimensional material layer and the first gate electrode layer. The metals with different work functions are used as the source electrode and the drain electrode of the device; electron and hole schottky barriers are formed on the interface of the metals and the two-dimensional material layer; P type and N type contact on the two sides of the device channel are further formed; and a typical TFET device structure is skillfully obtained.
Description
Technical field
The invention belongs to transistor arts, be specifically related to tunneling field-effect transistor and preparation method thereof.
Background technology
Along with the further scaled down of feature sizes of semiconductor devices, traditional semiconductor device is up to the limit of size.For improving the performance of device further, technical staff starts new construction, new material, and new technology carries out positive exploration.
Tunneling field-effect transistor (TFET, TunnelingField-EffectTransistor) adopts the new conduction mechanism of band-to-band-tunneling (BTBT), is a kind of Novel low power consumption device being suitable to system integration application development having very much development potentiality.TFET controls the tunnelling width of source and raceway groove interface place tunnel junctions by gate electrode so that source valence-band electrons is tunneling to channel conduction band (or raceway groove valence-band electrons is tunneling to source conduction band) and forms tunnelling current.This novel conduction mechanism breaks through the restriction of thermoelectrical potential kT/q in conventional MOS FET sub-threshold slope theoretical limit, it is possible to achieve lower than the super steep sub-threshold slope that has of 60mV/dec, reduces device static leakage current and then reduces device quiescent dissipation.
Additionally, in recent years, two-dimensional semiconductor material becomes a global scientific research focus by the physicochemical properties of its novelty.2010, the Graphene that physics Nobel Prize relates to was exactly the two-dimentional conductive material of a kind of only atomic thickness, and it is in the ascendant so far in research and the application of every field.Along with the discovery of Graphene, molybdenum bisuphide, tungsten disulfide, the two-dimensional material such as black phosphorus is similar with Graphene due to structure, becomes research focus again.For tungsten disulfide, the material of single layer structure, except showing the excellent electrical properties such as high mobility, high on-off ratio, it is often more important that it also have not available for Graphene ~ band gap of 1.9eV.These newfound two-dimensional material systems can well be applied in generation semiconductor devices, improves device performance further.
Summary of the invention
It is an object of the invention to propose a kind of tunneling field-effect transistor and preparation method thereof.
The present invention provides tunneling field-effect transistor, including:
Two-dimensional material layer；
Metal source and metal-drain, lay respectively at the both sides of described two-dimensional material layer, and described metal source and metal-drain have different work functions, forms opposite polarity electrical contact with described two-dimensional material layer；
The first grid is stacking, is positioned on one of them surface of described two-dimensional material layer, and including first grid dielectric layer and first gate electrode layer, wherein, described first grid dielectric layer is between described two-dimensional material layer and described first gate electrode layer.
Preferably, also include: second gate stack, stacking with the described first grid relative, it is positioned at another surface of described two-dimensional material layer, including second gate dielectric layer and second gate electrode layer, wherein, described second gate dielectric layer is between two-dimensional material layer and described second gate electrode layer.
Preferably, described first gate electrode layer is attached most importance to dope semiconductor substrates.
Preferably, also include: boundary layer, be positioned on described two-dimensional material layer, between metal source and metal-drain, under gate dielectric layer.
Preferably, described two-dimensional material is molybdenum bisuphide, tungsten disulfide or black phosphorus.
The preparation method that the present invention also provides for above-mentioned tunneling field-effect transistor, specifically comprises the following steps that
Form two-dimensional material layer to be formed；
Form metal source and metal-drain, form metal source and metal-drain in described two-dimensional material layer both sides, and described metal source and metal-drain have different work functions, form opposite polarity electrical contact with described two-dimensional material layer；And,
Form the stacking shape of the first grid, a surface of described two-dimensional material layer forms the first grid stacking, described first grid stack layer includes first grid dielectric layer and first gate electrode layer, and wherein, described first grid dielectric layer is formed between described two-dimensional material layer and first gate electrode layer.
Preferably, also include forming second gate stack step:
On another surface of described two-dimensional material layer, forming second gate stack with the stacking relative position of the described first grid, including second gate dielectric layer and second gate electrode layer, wherein, described second gate dielectric layer is between two-dimensional material layer and described second gate electrode layer.
Preferably, described first gate electrode layer is attached most importance to dope semiconductor substrates.
Preferably, before forming the step of described metal source and metal-drain, also include forming boundary layer step: on described two-dimensional material layer, form boundary layer.
Preferably, described two-dimensional material is molybdenum bisuphide, tungsten disulfide or black phosphorus.
The present invention adopts the metal source as device of different work functions, drain electrode, the Schottky barrier in electronics and hole is formed respectively in metal/two-dimensional material interface, and then realize P type in device channel both sides and contact with N-type, constitute typical TFET device architecture dexterously, the method can simplification of flowsheet, reduce production cost and preparing on a large scale of the TFET device based on two-dimensional material can be realized.Additionally, the length of device channel is determined by device source and drain distance, the accurate control of device size therefore can be realized by regulating the distance of TFET device source and drain.
Accompanying drawing explanation
Fig. 1 is the TFET device architecture schematic diagram with top gate structure.
Fig. 2 has top gate structure and the TFET device architecture schematic diagram comprising boundary layer.
Fig. 3 is the TFET device architecture schematic diagram with back grid structure.
Fig. 4 has back grid structure and the TFET device architecture schematic diagram comprising boundary layer.
Fig. 5 is the TFET device architecture schematic diagram with double-gate structure.
Fig. 6 has double-gate structure and the TFET device architecture schematic diagram comprising boundary layer.
Fig. 7 is the TFET device architecture schematic diagram with back grid structure using substrate as first gate electrode layer.
Fig. 8 is the TFET device architecture schematic diagram with double-gate structure using substrate as first gate electrode layer.
Fig. 9 is the flow chart that the preparation method to the TFET device using substrate as first gate electrode layer is indicated.
Figure 10 is the device profile structural representation after forming two-dimensional material layer.
Figure 11 is the device profile structural representation after forming boundary layer.
Figure 12 is the cross-sectional view after forming metal source.
Figure 13 is the TFET device architecture schematic diagram of the back grid structure after forming metal-drain.
Figure 14 is the cross-sectional view after forming second gate dielectric layer.
Figure 15 is the TFET device architecture schematic diagram of the double-gate structure after forming second gate electrode layer.
Figure 16 is the flow chart that the preparation method to the TFET device with double-gate structure is indicated.
Figure 17 is the flow chart that the preparation method to the TFET device with top gate structure is indicated.
Detailed description of the invention
Embodiments of the invention being described in detail hereinafter with reference to accompanying drawing, in various figures, identical element adopts similar accompanying drawing labelling to represent.Embodiment described below is illustrative of, and in order to simplify disclosure of the invention, hereinafter parts and setting to specific examples are described.Certainly, these are only example, it is intended to explain that the present invention is not considered as limiting the invention.Additionally, the invention provides the example of various specific technique and material, but just as the skilled person will understand, it is possible to do not realize the present invention according to these specific details.Unless particularly pointed out hereinafter, each several part of device all can adopt technique well known in the art and material to realize.Additionally, in describing the invention, it will be appreciated that, term " goes up ", " under " etc. the orientation of instruction or position relationship be based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or hint indication device or element must have specific orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention.Additionally, term " first ", " second " are only for descriptive purposes, and it is not intended that indicate or imply relative importance or the implicit quantity indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or implicitly include one or more these features.
It is illustrated in figure 1 the tunneling field-effect transistor structure chart with top gate structure based on two-dimensional material of the embodiment of the present invention.Tunneling field-effect transistor includes:
Support substrate 30, supporting substrate 30 can be silicon substrate, may also be other type of Semiconductor substrate, for instance, germanium substrate, GaAs substrate, InAs substrate, InSb substrate, GaSb substrate etc. on silicon substrate, insulating barrier on monocrystalline germanium, monocrystalline germanium silicon, polysilicon, poly-SiGe, insulating barrier.
Two-dimensional material layer 102, be positioned at support substrate 30 on, two-dimensional material layer 102 can be molybdenum bisuphide, tungsten disulfide or black phosphorus etc., thickness can be monoatomic layer and more than, it is preferred to 1～3 atomic layer.
Metal source 104 and metal-drain 105, lay respectively at the both sides of described two-dimensional material layer 102, and described metal source 104 and metal-drain 105 have different work functions, form opposite polarity electrical contact with described two-dimensional material layer 102.Such as, two-dimensional material layer 102 is tungsten disulfide in one embodiment of the invention, metal source 104 is Titanium, form N-type at metal source 104 with the interface of two-dimensional material layer 102 to contact, metal-drain 105 is Metal Palladium, forms P type in metal-drain 105 with the interface of two-dimensional material layer 102 and contacts.Certainly, the metal material that above-mentioned metal source 104 and metal-drain 105 can also be had different work functions by other is formed, if electrical contact that can be contrary with two-dimensional material layer 102 internus.It is to say, when metal source 104 formed with two-dimensional material layer 102 P type contact time, metal-drain 105 forms N-type with two-dimensional material layer 102 and contacts；Otherwise, when metal source 104 formed with two-dimensional material layer 102 N-type contact time, metal-drain 105 forms P type with two-dimensional material layer 102 and contacts.
The first grid is stacking, is positioned at the upper surface of two-dimensional material layer 102, and including first grid dielectric layer 101 and first gate electrode layer 100, wherein, first grid dielectric layer 101 is positioned on two-dimensional material layer 102, and first gate electrode layer 100 is positioned on first grid dielectric layer 101.Preferably, first grid dielectric layer 101 can be silicon oxide, silicon oxynitride or high K medium material etc., high K medium material such as hafnio oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other dielectric materials.First gate electrode layer 100 can include metal gate electrode or polysilicon etc., such as may include that Ti, TiAlx, TiN, TaNx, HfN, TiCx, TaCx, HfCx, Ru, TaNx, TiAlN, WCN, MoAlN, RuOx, polysilicon or other suitable materials or their combination.
Preferably, tunneling field-effect transistor also includes boundary layer 103, is positioned on two-dimensional material layer 102, as shown in Figure 2.Thereby, it is possible to improve source-drain electrode contact and the optimised devices electrology characteristic of device further.Boundary layer 103 can adopt TiO2、Al2O3Deng.
In one embodiment of the invention, tunneling field-effect transistor is back grid structure, as shown in Figure 3.Including supporting that substrate 30, two-dimensional material layer 102, the first grid be stacking, metal source 104 and metal-drain 105, wherein, the first grid is stacking, including first grid dielectric layer 101 and first gate electrode layer 100, and is positioned at the lower surface of two-dimensional material layer 102,
Metal source 104 and metal-drain 105, lay respectively at the both sides of two-dimensional material layer 102, and metal source 104 and metal-drain 105 have different work functions, form opposite polarity electrical contact with two-dimensional material layer 102.
Preferably, tunneling field-effect transistor also includes boundary layer 103, is positioned on two-dimensional material layer 102, as shown in Figure 4.
In one embodiment of the invention, tunneling field-effect transistor is double-gate structure, also include second gate stack, stacking with the first grid relative, it is positioned at another surface of two-dimensional material layer 102, including second gate dielectric layer 106 and second gate electrode layer 107, wherein, second gate dielectric layer 106 is positioned on two-dimensional material layer 102, second gate electrode layer 107, it is positioned on second gate dielectric layer 106, as shown in Figure 5.
Preferably, tunneling field-effect transistor also includes boundary layer 103, is positioned on two-dimensional material layer 102, as shown in Figure 6.
In one embodiment of the invention, heavily-doped semiconductor substrate is adopted to form the tunneling field-effect transistor of back grid structure as first gate electrode layer 100, as shown in Figure 7.Adopting heavily doped monocrystalline substrate in the present embodiment, its doping content is about 1E18cm-3~1E20cm-3.Can certainly be other heavily-doped semiconductor substrates, for instance, heavily doped monocrystal silicon, monocrystalline germanium, monocrystalline germanium silicon, polysilicon, poly-SiGe etc..In addition it is also possible to be metal basal board etc..That is, as long as the substrate can played a supporting role and can use as gate electrode layer.In this structure and another embodiment, structure as shown in Figure 3 differs only in, it is possible to directly use substrate is as first gate electrode layer 100, it is possible to simplification of flowsheet, saves material, thus reducing production cost.
Preferably, tunneling field-effect transistor also includes boundary layer 103, is positioned on two-dimensional material layer 102, as shown in figure 13.
In one embodiment of the invention, heavily-doped semiconductor substrate is adopted to form the tunneling field-effect transistor of double-gate structure as first gate electrode layer, as shown in Figure 8.Differing only in of structure (as shown in Figure 5) of this structure and another embodiment, it is possible to directly use substrate as first gate electrode layer 100, it is possible to simplification of flowsheet, save material, thus reducing production cost.
Preferably, tunneling field-effect transistor also includes boundary layer 103, is positioned on two-dimensional material layer 102, as shown in figure 15.
Hereinafter, the structural representation in each stage in the process preparing tunneling field-effect transistor shown in reference to the accompanying drawings, the example for the embodiment of the preparation method of tunneling field-effect transistor involved in the present invention illustrates.
In one embodiment of the invention, as it is shown in figure 9, comprise the following steps:
The stacking forming step S11 of the first grid.Adopt heavily-doped semiconductor substrate as first gate electrode layer 100, be thermally generated silicon oxide thick for 300nm as first grid dielectric layer 101, it is possible to compound substrate stacking directly as the first grid, make technological process simplify, reduce production cost.Certainly, it is also adopted by other kinds of heavily-doped semiconductor substrate, for instance, germanium, GaAs, indium arsenide, indium antimonide, gallium antimonide etc. on silicon, insulating barrier on monocrystalline germanium, monocrystalline germanium silicon, polysilicon, poly-SiGe, insulating barrier.In addition it is also possible to be metal basal board etc..As long as it is to say, can play a supporting role and can as gate electrode layer use substrate.It addition, first grid dielectric layer 101 can also be silicon oxynitride or high K medium material etc., high K medium material such as hafnio oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other dielectric materials, for instance La2O3、TiO2Deng.
Two-dimensional material layer forming step S12.Being transferred in compound substrate by two-dimensional material layer 102, namely first grid heap is stacked on, resulting structures is as shown in Figure 10.Two-dimensional material layer 102 can be such as tungsten disulfide, it is also possible to be molybdenum bisuphide, black phosphorus etc..Thickness is monoatomic layer or polyatom layer, it is preferred to 1 ~ 3 atomic layer.Two-dimensional material layer 102 transfer method such as, the method adopting mechanical stripping, it would however also be possible to employ the transfer method that this area is conventional.Preferably, two-dimensional material may be used without chemical meteorology deposition (CVD) method or ald (ALD) method is grown directly upon on substrate.
Preferably, before forming two-dimensional material layer 102, substrate forms marker graphic.Such as, adopt normalized optical photoetching process, expose marker graphic, metal laminated at the titanium of its surface evaporation about 50 nano thickness by physical vapor deposition (PVD) method, obtain the figure of alignment mark after removing photoresist so that follow-up alignment uses.
Preferably, boundary layer forming step S13 is also included.Adopt atomic layer deposition strategy at the titanium oxide of two-dimensional material layer 102 one layer of about 2nm of superficial growth as boundary layer 103.It is of course also possible to adopt Al2O3Deng dielectric material.Thereby, it is possible to improve source-drain electrode contact and the optimised devices electrology characteristic of device further.Figure 11 shows the device architecture schematic diagram located after forming boundary layer.
Metal source forming step S14.Source electrode is patterned, is coated with electron beam resist (AR-679.04), adopt electron beam set lithography, expose the source electrode of device.It is of course also possible to employing normal photolithographic process.Adopt the Titanium that PVD method deposits about 30 nanometers, after removing photoresist, form metal source 104.In this case, metal source 104 forms N-type with two-dimensional material layer 102 and contacts.Figure 12 has illustrated the device architecture schematic diagram after forming metal source.
Metal-drain forming step S15.It is coated with electron beam resist (AR-679.04), adopts electron beam set lithography, expose the drain electrode of device.It is of course also possible to employing normal photolithographic process.Adopt PVD method deposit Metal Palladium, after removing photoresist, form metal-drain 105.In this case, metal source 105 forms P type with two-dimensional material layer 102 and contacts.Thus, the TFET device of back grid structure is formed, as shown in figure 13.
Certainly, the metal material that above-mentioned metal source 104 and metal-drain 105 can also be had different work functions by other is formed, if electrical contact that can be contrary with two-dimensional material layer 102 internus.It is to say, when metal source 104 formed with two-dimensional material layer 102 P type contact time, metal-drain 105 forms N-type with two-dimensional material layer 102 and contacts；Otherwise, when metal source 104 formed with two-dimensional material layer 102 N-type contact time, metal-drain 105 forms P type with two-dimensional material layer 102 and contacts.
In an embodiment of the preparation method of tunneling field-effect transistor, also include the forming step S16 of second gate stack 20.Specifically, including second gate dielectric layer forming step, adopting ALD to deposit the titanium oxide second gate dielectric layer 106 as device of one layer of 5nm thickness at device channel place, resulting structures is as shown in figure 14.And, second gate electrode layer forming step, it is coated with electron beam resist, adopts electron beam overlay method to expose top-gated figure, PVD method deposit chromium gold lamination metal, sample is carried out under 600 degrees Celsius, nitrogen atmosphere, anneal 1 minute.Thus, the TFET device of double-gate structure is formed, as shown in figure 15.
Certainly, second gate dielectric layer 106 can be silicon oxide, silicon oxynitride or high K medium material etc., high K medium material such as hafnio oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other dielectric materials.Preferably, second gate dielectric layer 106 and boundary layer 103 are identical material.Second gate electrode layer 107 can be one or more layers structure, and gate electrode can include metal gate electrode or polysilicon etc., for instance may include that Ti, TiAlx、TiN、TaNx、HfN、TiCx、TaCx、HfCx、Ru、TaNx、TiAlN、WCN、MoAlN、RuOx, polysilicon or other suitable materials, or their combination.
In an embodiment of the preparation method of tunneling field-effect transistor, as shown in flow process Figure 16, comprise the steps:
Step S21, it is provided that support substrate 30.
Step S22, supporting, the formation first grid on substrate 30 is stacking, including first gate electrode layer 100 and first grid dielectric layer 101.Concrete grammar, identical with the forming method of second gate dielectric layer 106 and second gate electrode layer 107 in step S16 in above-described embodiment, no longer describe in detail.
Afterwards, same as the previously described embodiments, carry out two-dimensional material layer forming step S12, metal source forming step S14, metal-drain forming step S15, thus forming the TFET device of back grid structure, as shown in Figure 3.
Preferably, before metal source forming step S14, also include boundary layer forming step S13.Adopt atomic layer deposition strategy at the titanium oxide of two-dimensional material layer 102 one layer of about 2nm of superficial growth as boundary layer 103.It is of course also possible to adopt Al2O3Deng dielectric material.Figure 4 illustrates the structural representation of the TFET device of the back grid structure formed.
Preferably, in an embodiment of the preparation method of tunneling field-effect transistor, proceed the forming step S16 of second gate stack, thus forming the TFET device of double-gate structure, as shown in Figure 5, Figure 6.
Preferably, second gate dielectric layer 106 and boundary layer 103 are identical material.
In an embodiment of the preparation method of tunneling field-effect transistor, as shown in flow process Figure 17, carry out in accordance with the following steps:
Step S31, it is provided that support substrate 30.
Step S32, forms two-dimensional material layer 102 supporting on substrate 30.Two-dimensional material layer 102 is transferred on support substrate 30.Two-dimensional material layer 102 can be such as tungsten disulfide, it is also possible to be molybdenum bisuphide, black phosphorus etc..Two-dimensional material layer transfer method such as, the method adopting mechanical stripping, it would however also be possible to employ the transfer method that this area is conventional.
Afterwards, same as the previously described embodiments, carry out metal source forming step S14, metal-drain forming step S15.
Afterwards, carrying out step S33, two-dimensional material layer 102 forming the first grid stacking, including first grid dielectric layer 101 and first gate electrode layer 100, thus obtaining the TFET device of top gate structure, as shown in Figure 1.Concrete grammar, identical with the forming method of second gate dielectric layer 106 and second gate electrode layer 107 in step S16 in above-described embodiment, no longer describe in detail.
Preferably, boundary layer forming step S13 is also included.Adopt atomic layer deposition strategy at the titanium oxide of two-dimensional material layer 102 one layer of about 2nm of superficial growth as boundary layer 103.It is of course also possible to adopt Al2O3Deng dielectric material.Preferably, first grid dielectric layer 101 and boundary layer 103 are identical material.Fig. 2 has illustrated the schematic diagram of the tunneling field-effect transistor with top gate structure prepared by this embodiment.
Owing to, in above-described embodiment, giving identical symbol for identical part or identical step, for the preparation process having been described above, repeating no more.
In the above-mentioned any embodiment comprising and supporting substrate 30, supporting substrate 30 is Si substrate, according to specific needs, supports substrate 30 and can also select the substrate that other are suitable.
First or second gate dielectric layer can be silicon oxide, silicon oxynitride or high K medium material etc., high K medium material such as hafnio oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other dielectric materials etc..First or second gate electrode layer can be one or more layers structure, gate electrode can include metal gate electrode or polysilicon etc., such as may include that Ti, TiAlx, TiN, TaNx, HfN, TiCx, TaCx, HfCx, Ru, TaNx, TiAlN, WCN, MoAlN, RuOx, polysilicon or other suitable materials or their combination.Grid can pass through other metal level or directly lead out as required.
Metal source and metal-drain are formed by the metal material with different work functions respectively, the electrical contact contrary with two-dimensional material layer 102 internus.It is to say, when metal source 104 formed with two-dimensional material layer 102 P type contact time, metal-drain 105 forms N-type with two-dimensional material layer 102 and contacts；Otherwise, when metal source 104 formed with two-dimensional material layer 102 N-type contact time, metal-drain 105 forms P type with two-dimensional material layer 102 and contacts.
The present invention passes through the metal adopting different work functions as the source of device, drain electrode, the Schottky barrier in electronics and hole is formed respectively in metal and two-dimensional material interface, and then realize P type in device channel both sides and contact with N-type, constitute typical TFET device architecture dexterously, simplifying technological process, reducing technology difficulty, thus reducing production cost.It addition, the extensive preparation of the TFET device based on two-dimensional material can be realized according to the present invention.
Above, the tunneling field-effect transistor and preparation method thereof for the present invention has explained, but the invention is not restricted to above example, without departing from the scope of idea of the invention, naturally it is also possible to carry out various improvement, deformation.
Claims (10)
1. a tunneling field-effect transistor, it is characterised in that including:
Two-dimensional material layer；
Metal source and metal-drain, lay respectively at the both sides of described two-dimensional material layer, and described metal source and metal-drain have different work functions, forms opposite polarity electrical contact with described two-dimensional material layer；
The first grid is stacking, is positioned on one of them surface of described two-dimensional material layer, and the first grid is stacking includes first grid dielectric layer and first gate electrode layer, and wherein, described first grid dielectric layer is between described two-dimensional material layer and described first gate electrode layer.
2. tunneling field-effect transistor according to claim 1, it is characterised in that also include:
Second gate stack, stacking with the described first grid relative, it is positioned at another surface of described two-dimensional material layer, second gate stack includes second gate dielectric layer and second gate electrode layer, and wherein, described second gate dielectric layer is between two-dimensional material layer and described second gate electrode layer.
3. tunneling field-effect transistor according to claim 1 and 2, it is characterised in that described first gate electrode layer is attached most importance to dope semiconductor substrates.
4. tunneling field-effect transistor according to claim 1 and 2, it is characterised in that also include:
Boundary layer, is positioned on described two-dimensional material layer.
5. tunneling field-effect transistor according to claim 1 and 2, it is characterised in that
Described two-dimensional material is molybdenum bisuphide, tungsten disulfide or black phosphorus.
6. the preparation method of the described tunneling field-effect transistor of one of claim 1-5, it is characterised in that comprise the following steps:
Form two-dimensional material layer；
Form metal source and metal-drain in described two-dimensional material layer both sides, and described metal source and metal-drain have different work functions, form opposite polarity electrical contact with described two-dimensional material layer；And,
The formation first grid is stacking: form the first grid on a surface of described two-dimensional material layer stacking, described first grid stack layer includes first grid dielectric layer and first gate electrode layer, wherein, described first grid dielectric layer is formed between described two-dimensional material layer and first gate electrode layer.
7. the preparation method of tunneling field-effect crystal according to claim 6, it is characterized in that, also include second gate stack forming step: on another surface of described two-dimensional material layer, relative position stacking with the described first grid, form second gate stack, second gate stack includes second gate dielectric layer and second gate electrode layer, and wherein, described second gate dielectric layer is between two-dimensional material layer and described second gate electrode layer.
8. the preparation method of the tunneling field-effect transistor according to claim 6 or 7, it is characterised in that described first gate electrode layer is attached most importance to dope semiconductor substrates.
9. the method preparing tunneling field-effect transistor according to claim 6 or 7, it is characterised in that also included boundary layer forming step before forming the step of described metal source and metal-drain: form boundary layer on described two-dimensional material layer.
10. the preparation method of the tunneling field-effect crystal according to claim 6 or 7, it is characterised in that described two-dimensional material is molybdenum bisuphide, tungsten disulfide or black phosphorus.
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| CN107342320A (en) * | 2017-07-18 | 2017-11-10 | 清华大学 | Junctionless tunneling field effect transistor and preparation method |
| CN107731924A (en) * | 2017-09-26 | 2018-02-23 | 复旦大学 | A kind of black phosphorus field-effect transistor and preparation method thereof |
| CN109155333A (en) * | 2016-11-23 | 2019-01-04 | 华为技术有限公司 | A kind of tunneling transistor and preparation method thereof |
| CN109417095A (en) * | 2016-07-19 | 2019-03-01 | 华为技术有限公司 | Tunneling field-effect transistor and preparation method thereof |
| CN110634958A (en) * | 2019-09-24 | 2019-12-31 | 山东大学 | Semiconductor thin film field effect transistor made of unstable two-dimensional material and preparation method thereof |
| CN111969058A (en) * | 2020-07-30 | 2020-11-20 | 电子科技大学中山学院 | Molybdenum disulfide field effect transistor and preparation method and application thereof |
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| CN104241378A (en) * | 2014-09-10 | 2014-12-24 | 北京大学 | Double-graphene-layer tunneling field effect transistor and manufacturing method thereof |
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| CN109417095A (en) * | 2016-07-19 | 2019-03-01 | 华为技术有限公司 | Tunneling field-effect transistor and preparation method thereof |
| CN109417095B (en) * | 2016-07-19 | 2021-10-15 | 华为技术有限公司 | Tunneling field effect transistor and preparation method thereof |
| CN109155333A (en) * | 2016-11-23 | 2019-01-04 | 华为技术有限公司 | A kind of tunneling transistor and preparation method thereof |
| CN107342320A (en) * | 2017-07-18 | 2017-11-10 | 清华大学 | Junctionless tunneling field effect transistor and preparation method |
| CN107342320B (en) * | 2017-07-18 | 2021-02-02 | 清华大学 | Junction-free tunneling field effect transistor and preparation method thereof |
| CN107731924A (en) * | 2017-09-26 | 2018-02-23 | 复旦大学 | A kind of black phosphorus field-effect transistor and preparation method thereof |
| CN110634958A (en) * | 2019-09-24 | 2019-12-31 | 山东大学 | Semiconductor thin film field effect transistor made of unstable two-dimensional material and preparation method thereof |
| CN110634958B (en) * | 2019-09-24 | 2021-01-15 | 山东大学 | Semiconductor thin film field effect transistor made of unstable two-dimensional material and preparation method thereof |
| CN111969058A (en) * | 2020-07-30 | 2020-11-20 | 电子科技大学中山学院 | Molybdenum disulfide field effect transistor and preparation method and application thereof |
| CN113066905A (en) * | 2021-04-12 | 2021-07-02 | 山东大学 | Method for preparing indium selenide photoelectric detector by photoetching technology |
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