US8754403B2 - Epitaxial source/drain contacts self-aligned to gates for deposited FET channels - Google Patents
Epitaxial source/drain contacts self-aligned to gates for deposited FET channels Download PDFInfo
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- US8754403B2 US8754403B2 US13/565,342 US201213565342A US8754403B2 US 8754403 B2 US8754403 B2 US 8754403B2 US 201213565342 A US201213565342 A US 201213565342A US 8754403 B2 US8754403 B2 US 8754403B2
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 87
- 239000002041 carbon nanotube Substances 0.000 claims abstract description 67
- 229910021393 carbon nanotube Inorganic materials 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- JVWJBBYNBCYSNA-UHFFFAOYSA-N lanthanum(3+) oxygen(2-) yttrium(3+) Chemical compound [O--].[O--].[O--].[Y+3].[La+3] JVWJBBYNBCYSNA-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 16
- 238000000151 deposition Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 13
- 238000000407 epitaxy Methods 0.000 description 4
- 239000002086 nanomaterial Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002230 CNT30 Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- -1 again Chemical compound 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Definitions
- aspects of the present invention are directed to epitaxial source/drain contacts that are self aligned to gates for carbon nanotube-based field effect transistors (CNTFETs).
- CNTFETs carbon nanotube-based field effect transistors
- CNTFETs have been proposed as a potential post-silicon complementary-metal-oxide-semiconductor (CMOS) solution for dense logic applications.
- CMOS complementary-metal-oxide-semiconductor
- CMOS complementary-metal-oxide-semiconductor
- the high mobility of the ideal CNTFET enables width scaling and good short-channel effects of the ideal CNTFET enables gate length scaling.
- CMOS complementary-metal-oxide-semiconductor
- one of the many additional challenges a CNTFET-base technology must overcome is compatibility with the high layout density that traditional silicon CMOS technology currently supports.
- the source/drain and gate contacts to the switching device built around each CNT must all be precisely positioned.
- Gate pitch scaling requires a manufacturable device structure in which the source/drain is self-aligned to the gate.
- Such self-alignment eliminates the variability in parasitic resistance and capacitance caused by misalignment of the source/drain to the gate and it also eliminates the area penalty of having to include a margin for misalignment in the layout.
- CMOS complementary metal-oxide-semiconductor
- this precise positioning is enabled by using gate shadowing to define implanted junction profiles and by the self-aligned silicide process. For CNTFETs, these methods are often inapplicable.
- SA CNTFETs with source-drain contacts that are self-aligned to the gate have been demonstrated using directional evaporation, chemical doping and electrostatic doping.
- problems remain.
- the process window for directional evaporation is too narrow for manufacturability
- chemical doping of CNT source/drain contacts continues to be an active area of research but results remain irreproducible and inconsistent and electrostatic doping works relatively well but is not ideal because the back gate required for electrostatic doping requires additional layout area and introduces a large parasitic capacitance.
- a method of forming a self-aligned device includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
- CNTs carbon nanotubes
- a process of forming self-aligned epitaxial source/drain contacts includes depositing carbon nanotubes (CNTs) on a crystalline dielectric underlayer, masking off field regions by a hard mask, patterning a gate stack with a hardmask atop the CNTs, encapsulating the gate stack with spacers and epitaxially growing source/drain regions adjacent to the spacers to provide a self-aligned source/drain.
- CNTs carbon nanotubes
- a self-aligned device includes a plurality of carbon nanotubes (CNTs) disposed on a crystalline dielectric substrate, a field mask disposed on the crystalline dielectric substrate as a rectangular planar enclosure of the CNTs, a plurality of insulated gate stacks formed on the CNTs with a structural integrity thereof maintained and epitaxial source and drain regions provided in contact with portions of the CNTs exposed by the insulated gate stacks.
- CNTs carbon nanotubes
- FIG. 1 illustrates a silicon substrate with a crystalline dielectric layer and deposited carbon nanotubes
- FIG. 2 illustrates a field mask formed around the carbon nanotubes
- FIG. 3 illustrates gate stacks patterned onto the carbon nanotubes
- FIG. 4 illustrates insulation formed around the gate stacks
- FIG. 5 illustrates epitaxial growth at source and drain regions
- FIG. 6 shows a view of a carbon nanotube in contact with epitaxial source/drain material.
- the self-aligned epitaxial source/drain contact process disclosed herein provides a platform for building self-aligned devices from deposited nanostructures, such as carbon nanotubes or semiconducting nanowires.
- the nanostructures are assumed to have already been deposited on an insulating crystalline underlayer, such as lanthanum yttrium oxide (LaYO).
- Field regions are masked off by a hard mask, a gate stack with a hardmask is patterned atop the nanostructures and the gate stack is then encapsulated with a spacer.
- a non-insulating material such as silicon is then epitaxially grown in the source/drain regions to provide a self-aligned source/drain.
- a silicon substrate 10 is provided and has a top surface on which a layer of crystalline dielectric 20 is disposed.
- the crystalline dielectric 20 may include LaYO or some other similar crystalline dielectric on which silicon epitaxy can be seeded and epitaxial growth of silicon is possible.
- LaYO as the crystalline dielectric 20 enables the growth of silicon epitaxy due to the fact that a crystalline structure of silicon epitaxy has been found to be substantially similar to that of LaYO to an extent that the silicon epitaxial growth is possible even without the presence of a silicon or a silicon-germanium sub-structure.
- a plurality of nanostructures such as carbon nanotubes (CNTs) 30 or nanowires, are deposited on a surface 21 , such as the top surface, of the crystalline dielectric 20 .
- the CNTs 30 are deposited substantially in alignment with one another and substantially in parallel with one another, although this is not required.
- the CNT 30 deposition may be accomplished in accordance with various known methods and descriptions thereof are therefore omitted.
- a field mask 40 including silicon dioxide (SiO 2 ) or some other similar material is placed on the crystalline dielectric 20 as a substantially rectangular planar enclosure of the CNTs 30 .
- the field mask may include edges 41 that form a perimeter around the CNTs 30 .
- the field mask 40 may be formed with various shapes and sizes as long as the CNTs 30 are isolated as necessary for a given application and that the rectangular shape shown in FIG. 2 is merely exemplary.
- isolation of the portion of the crystalline dielectric 20 encompassing the location of the CNTs 30 may also be accomplished by etching the crystalline dielectric 20 around the CNTs 30 to form a groove. The exposed surfaces of the groove and/or the substrate 10 are then oxidized.
- gate dielectric and gate electrode gate stacks 50 are patterned onto the CNTs 30 , the crystalline dielectric 20 and the field mask 40 .
- the gate stacks 50 are substantially parallel with one another and substantially perpendicular with respect to an orientation of the CNTs 30 , although this is not required.
- the gate stacks 50 may be formed of various materials in various arrangements, such as for example, a layer of a gate dielectric 51 (e.g., hafnium oxide, HfO2), a layer of gate stack material 52 (e.g., titanium nitride, TiN, or tungsten, W) and a secondary layer of gate mask material 53 (e.g., silicon nitride, SiN).
- a gate dielectric 51 e.g., hafnium oxide, HfO2
- gate stack material 52 e.g., titanium nitride, TiN, or tungsten, W
- secondary layer of gate mask material 53 e.g., silicon nitride, SiN
- the gate dielectric 51 may be deposited by way of atomic layer deposition (ALD) or spin-on deposition, in particular, which would not be expected to damage the CNTs 30 .
- the gate stacks 50 are insulated by the secondary layer of the gate mask material 53 .
- Gates are then defined using lithography and patterned using, for example, partial reactive ion etching (RIE) that is timed to end in close proximity to the CNTs 30 .
- RIE partial reactive ion etching
- Spacers 60 are then formed along the sidewalls of the gates using a conformal deposition of spacer material followed by an anisotropic etch process that is performed so as to avoid damage to the CNTs 30 . That is, the anisotropic etch of the spacers 60 is either end-pointed to stop once the remaining gate dielectric 51 is exposed or timed to end just prior to the time at which the CNTs 30 are about to be reached by the etchant (i.e., a plasma based etchant). In either case, once the etch process is stopped, it is followed by an isotropic wet etch that substantially completely removes all spacer 60 and gate dielectric 51 material from the source and drain regions 70 .
- the anisotropic etch of the spacers 60 is either end-pointed to stop once the remaining gate dielectric 51 is exposed or timed to end just prior to the time at which the CNTs 30 are about to be reached by the etchant (i.e., a plasma based etchant
- a result of this process is that the spacers 60 , or the spacers 60 and the gate dielectric 51 , will contact and substantially surround the CNTs 30 in an axial and a circumferential direction such that source and drain regions 70 , which are described below, can be isolated from the gate stacks 50 .
- the spacers 60 , or the spacers 60 and the gate dielectric 51 contact the CNTs 30 along contact surfaces spanning the spacer 60 thicknesses and nearly the entire curved surfaces of the CNTs 30 (i.e., around the CNTs 30 for nearly 360°) without removing the CNTs 30 from contact with the crystalline dielectric 20 .
- source and drain regions 70 are epitaxially grown to be in contact with portions of the CNTs 30 exposed by the insulated gate stacks 50 . As shown in FIG. 6 , the contact between the epitaxial source and drain regions 70 with the CNTs 30 extends around nearly the entire circumference of the CNTs 30 with the result being formation of a reliable contact surface 80 .
- the source and drain regions 70 contact the CNTs 30 along contact surfaces spanning the source and drain region 70 thicknesses and nearly the entire curved surfaces of the CNTs 30 (i.e., again, around the CNTs 30 for nearly 360°) without removing the CNTs 30 from contact with the crystalline dielectric 20 .
- the epitaxial growth of the source and drain regions 70 is facilitated by the presence of the crystalline dielectric 20 , which seeds and subsequently permits epitaxial growth of silicon by virtue of its crystalline structure being similar to that of epitaxial silicon.
- the resulting epitaxial source/drain regions 70 are self aligned in that one-step lithography was employed for the definition of both the insulated gate regions.
- the process of epitaxially growing the source and drain regions 70 may be accomplished in accordance with various known methods with full or partial silicidation completed later.
- the source and drain regions 70 may be formed by the addition of boron or phosphorous doped silicon to the exposed CNTs 30 using in situ doped silicon epitaxy.
- the source and drain regions 70 may be grown undoped and to be later implanted with ion species such as boron (B), arsenide (As) or phosphorous (P) followed by a rapid thermal annealing to activate the implanted dopants.
- the epitaxial source drain regions may be converted to a metal silicide using a self-aligned silicide process, which is well known in the field of microelectronics.
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- Physics & Mathematics (AREA)
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- Crystallography & Structural Chemistry (AREA)
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Abstract
Description
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/565,342 US8754403B2 (en) | 2010-06-17 | 2012-08-02 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
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US12/817,733 US8513099B2 (en) | 2010-06-17 | 2010-06-17 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
US13/565,342 US8754403B2 (en) | 2010-06-17 | 2012-08-02 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
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US12/817,733 Division US8513099B2 (en) | 2010-06-17 | 2010-06-17 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
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US20120292598A1 US20120292598A1 (en) | 2012-11-22 |
US8754403B2 true US8754403B2 (en) | 2014-06-17 |
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US12/817,733 Expired - Fee Related US8513099B2 (en) | 2010-06-17 | 2010-06-17 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
US13/565,342 Expired - Fee Related US8754403B2 (en) | 2010-06-17 | 2012-08-02 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
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US12/817,733 Expired - Fee Related US8513099B2 (en) | 2010-06-17 | 2010-06-17 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels |
Country Status (7)
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US (2) | US8513099B2 (en) |
JP (1) | JP5852643B2 (en) |
CN (1) | CN102906893B (en) |
DE (1) | DE112011101023B4 (en) |
GB (1) | GB2494012B (en) |
TW (1) | TWI505375B (en) |
WO (1) | WO2011157487A1 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9024310B2 (en) * | 2011-01-12 | 2015-05-05 | Tsinghua University | Epitaxial structure |
KR20120100630A (en) * | 2011-03-04 | 2012-09-12 | 삼성전자주식회사 | Semiconductor device, method of manufacturing the same and electronic device including semiconductor device |
US8492748B2 (en) * | 2011-06-27 | 2013-07-23 | International Business Machines Corporation | Collapsable gate for deposited nanostructures |
CN103730366B (en) * | 2012-10-16 | 2018-07-31 | 中国科学院微电子研究所 | Method for manufacturing stacked nanowire MOS transistor |
US8778768B1 (en) | 2013-03-12 | 2014-07-15 | International Business Machines Corporation | Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain |
CN103715097B (en) * | 2013-12-27 | 2019-03-19 | 上海集成电路研发中心有限公司 | The method for enclosing gate type MOSFET of vertical-channel is prepared using epitaxy technique |
US9203041B2 (en) * | 2014-01-31 | 2015-12-01 | International Business Machines Corporation | Carbon nanotube transistor having extended contacts |
US9502673B2 (en) * | 2015-03-31 | 2016-11-22 | International Business Machines Corporation | Transistor devices with tapered suspended vertical arrays of carbon nanotubes |
US9543535B1 (en) | 2015-06-29 | 2017-01-10 | International Business Machines Corporation | Self-aligned carbon nanotube transistor including source/drain extensions and top gate |
US10276698B2 (en) | 2015-10-21 | 2019-04-30 | International Business Machines Corporation | Scalable process for the formation of self aligned, planar electrodes for devices employing one or two dimensional lattice structures |
US10319926B2 (en) | 2015-11-05 | 2019-06-11 | International Business Machines Corporation | End-bonded metal contacts on carbon nanotubes |
US9472773B1 (en) | 2015-12-09 | 2016-10-18 | International Business Machines Corporation | Stacked carbon nanotube multiple threshold device |
CN105609636B (en) * | 2016-02-17 | 2018-05-08 | 上海交通大学 | Directional single-wall carbon nanotube array is the field-effect transistor and production method of raceway groove |
US11165032B2 (en) * | 2019-09-05 | 2021-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor using carbon nanotubes |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166771A (en) | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US20030178617A1 (en) | 2002-03-20 | 2003-09-25 | International Business Machines Corporation | Self-aligned nanotube field effect transistor and method of fabricating same |
US20050037582A1 (en) | 2003-08-13 | 2005-02-17 | International Business Machines Corporation | Device threshold control of front-gate silicon-on-insulator mosfet using a self-aligned back-gate |
US20050142766A1 (en) * | 2003-07-28 | 2005-06-30 | Hareland Scott A. | Method of fabricating an ultra-narrow channel semiconductor device |
US20070014151A1 (en) * | 2005-06-30 | 2007-01-18 | Yuegang Zhang | Nanotube-and nanocrystal-based non-volatile memory |
US20070267703A1 (en) | 2006-05-17 | 2007-11-22 | Chartered Semiconductor Manufacturing Ltd. | Strained channel transistor and method of fabrication thereof |
US20080258207A1 (en) * | 2005-06-30 | 2008-10-23 | Marko Radosavljevic | Block Contact Architectures for Nanoscale Channel Transistors |
US20080293228A1 (en) * | 2007-05-25 | 2008-11-27 | Kalburge Amol M | CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices |
US20080296562A1 (en) | 2007-05-31 | 2008-12-04 | Murduck James M | Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices |
US20080308831A1 (en) * | 2001-07-05 | 2008-12-18 | International Business Machines Corporation | Semiconductor structure including mixed rare earth oxide formed on silicon |
US20090032804A1 (en) | 2007-07-31 | 2009-02-05 | Kalburge Amol M | Self-Aligned T-Gate Carbon Nanotube Field Effect Transistor Devices and Method for Forming the Same |
US7534675B2 (en) | 2007-09-05 | 2009-05-19 | International Business Machiens Corporation | Techniques for fabricating nanowire field-effect transistors |
US20090236675A1 (en) | 2008-03-21 | 2009-09-24 | National Tsing Hua University | Self-aligned field-effect transistor structure and manufacturing method thereof |
US7598516B2 (en) | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
US20100029063A1 (en) | 2007-01-16 | 2010-02-04 | Northrop Grumman Space & Mission Systems Corporation | Carbon nanotube fabrication from crystallography oriented catalyst |
WO2010020579A1 (en) | 2008-08-18 | 2010-02-25 | International Business Machines Corporation | Thin body silicon-on-insulator transistor with borderless self-aligned contacts |
US20100155696A1 (en) * | 2002-09-30 | 2010-06-24 | Nanosys, Inc. | Large-Area Nanoenabled Macroelectronic Substrates and Uses Therefor |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6360153A (en) * | 1986-08-29 | 1988-03-16 | 株式会社日立製作所 | Mullite base ceramic insulation substrate |
JPH0357228A (en) * | 1989-07-25 | 1991-03-12 | Nec Corp | Compound semiconductor device |
JP2839018B2 (en) * | 1996-07-31 | 1998-12-16 | 日本電気株式会社 | Method for manufacturing semiconductor device |
KR100376197B1 (en) * | 1999-06-15 | 2003-03-15 | 일진나노텍 주식회사 | Low temperature synthesis of carbon nanotubes using metal catalyst layer for decompsing carbon source gas |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
WO2004094308A1 (en) * | 2003-04-22 | 2004-11-04 | Commissariat A L'energie Atomique | A process for modifying at least one electrical property of a nanotube or a nanowire and a transistor incorporating it. |
JP2005126323A (en) * | 2004-11-15 | 2005-05-19 | Nec Corp | Catalyst carrying substrate, method for growing carbon nanotube using the same, and transistor using the carbon nanotube |
US7582534B2 (en) * | 2004-11-18 | 2009-09-01 | International Business Machines Corporation | Chemical doping of nano-components |
US7452759B2 (en) * | 2005-11-29 | 2008-11-18 | Micron Technology, Inc. | Carbon nanotube field effect transistor and methods for making same |
JP2008235752A (en) * | 2007-03-23 | 2008-10-02 | Toshiba Corp | Semiconductor apparatus and method of manufacturing the same |
JP2009010140A (en) * | 2007-06-27 | 2009-01-15 | Oki Electric Ind Co Ltd | Semiconductor wafer |
US8106455B2 (en) * | 2009-04-30 | 2012-01-31 | International Business Machines Corporation | Threshold voltage adjustment through gate dielectric stack modification |
-
2010
- 2010-06-17 US US12/817,733 patent/US8513099B2/en not_active Expired - Fee Related
-
2011
- 2011-05-10 GB GB1209073.4A patent/GB2494012B/en active Active
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- 2011-05-10 WO PCT/EP2011/057455 patent/WO2011157487A1/en active Application Filing
- 2011-06-17 TW TW100121192A patent/TWI505375B/en active
-
2012
- 2012-08-02 US US13/565,342 patent/US8754403B2/en not_active Expired - Fee Related
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166771A (en) | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US20080308831A1 (en) * | 2001-07-05 | 2008-12-18 | International Business Machines Corporation | Semiconductor structure including mixed rare earth oxide formed on silicon |
US20030178617A1 (en) | 2002-03-20 | 2003-09-25 | International Business Machines Corporation | Self-aligned nanotube field effect transistor and method of fabricating same |
WO2003081687A2 (en) | 2002-03-20 | 2003-10-02 | International Business Machines Corporation | Self-aligned nanotube field effect transistor and method of fabricating same |
WO2003081687A3 (en) | 2002-03-20 | 2004-09-30 | Ibm | Self-aligned nanotube field effect transistor and method of fabricating same |
US20100155696A1 (en) * | 2002-09-30 | 2010-06-24 | Nanosys, Inc. | Large-Area Nanoenabled Macroelectronic Substrates and Uses Therefor |
US20050142766A1 (en) * | 2003-07-28 | 2005-06-30 | Hareland Scott A. | Method of fabricating an ultra-narrow channel semiconductor device |
US20050037582A1 (en) | 2003-08-13 | 2005-02-17 | International Business Machines Corporation | Device threshold control of front-gate silicon-on-insulator mosfet using a self-aligned back-gate |
US7598516B2 (en) | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
US20080258207A1 (en) * | 2005-06-30 | 2008-10-23 | Marko Radosavljevic | Block Contact Architectures for Nanoscale Channel Transistors |
US20070014151A1 (en) * | 2005-06-30 | 2007-01-18 | Yuegang Zhang | Nanotube-and nanocrystal-based non-volatile memory |
US20070267703A1 (en) | 2006-05-17 | 2007-11-22 | Chartered Semiconductor Manufacturing Ltd. | Strained channel transistor and method of fabrication thereof |
US20100029063A1 (en) | 2007-01-16 | 2010-02-04 | Northrop Grumman Space & Mission Systems Corporation | Carbon nanotube fabrication from crystallography oriented catalyst |
US20080293228A1 (en) * | 2007-05-25 | 2008-11-27 | Kalburge Amol M | CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices |
US20080296562A1 (en) | 2007-05-31 | 2008-12-04 | Murduck James M | Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices |
US20090032804A1 (en) | 2007-07-31 | 2009-02-05 | Kalburge Amol M | Self-Aligned T-Gate Carbon Nanotube Field Effect Transistor Devices and Method for Forming the Same |
US7534675B2 (en) | 2007-09-05 | 2009-05-19 | International Business Machiens Corporation | Techniques for fabricating nanowire field-effect transistors |
US20090236675A1 (en) | 2008-03-21 | 2009-09-24 | National Tsing Hua University | Self-aligned field-effect transistor structure and manufacturing method thereof |
WO2010020579A1 (en) | 2008-08-18 | 2010-02-25 | International Business Machines Corporation | Thin body silicon-on-insulator transistor with borderless self-aligned contacts |
Non-Patent Citations (8)
Title |
---|
A. Javey et al., "Self-Aligned 40 nm Channel Carbon Nanotube Field-Effect Transistors With Subthreshold Swings Down to 70mV/decade," Proceedings of SPIE, 2005, pp. 14-18, vol. 5732. |
A. Javey, et al., High Performance n-Type Carbon Nanotube Field-Effect Transistors With Chemically Doped Contacts, Nano Letters, vol. 5, No. 2, 2005, pp. 345-348. |
G.M. Cohen et al., "Nanowire metal-oxide-semiconductor field effect transistor with doped epitaxial contacts for source and drain," Applied Physics Letters, 2007, 3pgs, vol. 90, American Institute of Physics. |
Office Action dated Mar. 23, 2012 corresponding to U.S. Appl. No. 12/817,733, filed Jun. 17, 2010; 20 pages. |
Q. Li et al., "Design, Fabrication and Characterization of High-Performance Silicon Nanowire Transistors," IEEE Explore, 2008, pp. 526-529, IEEE. |
Written Opinion and International Search Report dated Dec. 1, 2011 for Application No. PCT/EP2011/057455; 9 pages. |
Yu-Ming Lin, et al., "High-Performance Carbon Nanotube Field-Effect Transistor With Tunable Polarities", IEEE Transactions on Nanotechnology, vol. 4, No. 5, Sep. 2005, pp. 481-489. |
Z. Zhang, et al., "Self-Aligned Ballistic n-Type Single-Walled Carbon Nanotube Field-Effect Transistors with Adjustable Threshold Voltage", Nano Letters, 2008, vol. 8, No. 11, pp. 3696-3701, American Chemical Society. |
Also Published As
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TWI505375B (en) | 2015-10-21 |
GB2494012B (en) | 2014-07-23 |
CN102906893B (en) | 2015-08-12 |
DE112011101023T5 (en) | 2013-01-17 |
GB201209073D0 (en) | 2012-07-04 |
US8513099B2 (en) | 2013-08-20 |
DE112011101023B4 (en) | 2015-07-02 |
JP2013528952A (en) | 2013-07-11 |
TW201214579A (en) | 2012-04-01 |
JP5852643B2 (en) | 2016-02-03 |
US20110309332A1 (en) | 2011-12-22 |
CN102906893A (en) | 2013-01-30 |
WO2011157487A1 (en) | 2011-12-22 |
US20120292598A1 (en) | 2012-11-22 |
GB2494012A (en) | 2013-02-27 |
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