CN107342320B - Junction-free tunneling field effect transistor and preparation method thereof - Google Patents
Junction-free tunneling field effect transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention provides a junction-free tunneling field effect transistor and a preparation method thereof. The junction-less tunneling field effect transistor includes: an insulating layer; a channel region disposed on the insulating layer; the source electrode and the drain electrode are arranged on two sides of the channel region; the gate dielectric layer is arranged on the channel region; the grid electrode is arranged on the grid dielectric layer and comprises a top grid and an electrostatic modulation grid electrode. Thus, the junction-free tunneling field effect transistor has at least one of the following advantages: the structure is simple, the preparation can be realized by utilizing a simpler process flow, the doping concentration is flexible and adjustable, the power consumption is lower, and the like.
Description
Technical Field
The invention relates to the field of electronics, in particular to a junction-free tunneling field effect transistor and a preparation method thereof.
Background
The subthreshold swing of the tunneling field effect transistor can reach a value lower than 60mV/dec at room temperature, and the limit of the traditional field effect transistor is broken through. Therefore, the method has good application prospect in the field of low-power-consumption integrated circuits in the future. However, the conventional tunnel transistor needs to adopt ion implantation and high temperature annealing process to form tunnel junctions, which has large heat dissipation, complex process, impurity diffusion and difficulty in forming small-sized abrupt junctions. While the jfet does not require ion implantation to form the junction, it still relies on the drift diffusion of carriers to operate, and therefore the subthreshold swing is also limited by 60 mV/dec.
Therefore, the structure and the manufacturing method of the present jfet or the tunnel fet still need to be improved.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
The present invention has been completed based on the following findings of the inventors:
at present, the tunneling field effect transistor based on the traditional semiconductor needs to adopt ion implantation and a high-temperature annealing process to form a tunneling junction, the heat dissipation of the tunneling field effect transistor is large, the process is complex, impurity diffusion exists, and a small-size abrupt junction is difficult to form. While the junctionless transistor does not require ion implantation to form a junction, it still relies on the drift diffusion of carriers to operate, and therefore the subthreshold swing is also limited by 60 mV/dec. In this regard, the inventors have made extensive studies to provide a junction-less tunneling transistor, which can combine the advantages of the junction-less transistor and the tunneling transistor to achieve a sub-threshold swing of less than 60mV/dec with reduced process complexity and heat dissipation.
In one aspect, the present invention provides a junction-free tunneling field effect transistor. The junction-less tunneling field effect transistor includes: an insulating layer; a channel region disposed on the insulating layer; the source electrode and the drain electrode are arranged on two sides of the channel region; the gate dielectric layer is arranged on the channel region; the grid electrode is arranged on the grid dielectric layer and comprises a top grid and an electrostatic modulation grid electrode. Thus, the junction-free tunneling field effect transistor has at least one of the following advantages: the structure is simple, the preparation can be realized by utilizing a simpler process flow, the doping concentration is flexible and adjustable, the power consumption is lower, and the like.
According to an embodiment of the present invention, the channel region is formed of a two-dimensional thin film material having a bipolar on characteristic. Therefore, the junction-free tunneling field effect transistor has better grid control capability, the two-dimensional materials are combined by Van der Waals force, a dangling bond is not formed, trap-assisted tunneling can be effectively avoided, ion doping with different concentrations can be respectively realized under positive and negative grid voltages, and the process is simple, flexible and adjustable.
According to an embodiment of the present invention, the channel region includes at least one of black phosphorus, tungsten diselenide, tungsten disulfide, graphene, and tungsten ditelluride. Therefore, the channel region can be formed by using the easily obtained materials with wide sources, and the production cost can be further saved.
According to an embodiment of the present invention, the channel region has a thickness of 6nm or less. Therefore, a thinner channel can be formed, carriers in the channel can be controlled by a stronger grid, and the junction-free tunneling field effect transistor realized by the channel can be switched on and off better.
According to an embodiment of the invention, the electrostatic modulation gate is arranged close to the source or the drain. Therefore, the doping type of the channel region can be better controlled, and formation of an abrupt junction is facilitated.
According to an embodiment of the invention, the junction-free tunneling field effect transistor comprises two electrostatic modulation gates, and the top gate is arranged between the two electrostatic modulation gates. Therefore, the control of the doping type of the channel region can be better realized.
According to an embodiment of the present invention, the source electrode and the drain electrode are each independently formed of a metal, and the metal forming the source electrode has a different work function from the metal forming the drain electrode. Thus, different doping types can be formed at the source end and the drain end, wherein the metal with low work function is beneficial to the flow of electrons, and the metal with high work function is beneficial to the flow of holes.
According to an embodiment of the present invention, the gate dielectric layer is formed of a high-K dielectric. Therefore, the thickness of the gate oxide can be increased, and the tunneling leakage current of the gate can be inhibited.
According to the embodiment of the invention, the gate dielectric layer is made of HfO2、ZrO2And Al2O3And at least one of HfZrOx. Therefore, the control capability of the device grid electrode on the source end tunneling effect can be enhanced through the high-K dielectric.
According to the embodiment of the invention, the thickness of the gate dielectric layer is 1-5 nm. Therefore, the appropriate thickness of the gate dielectric can keep enough gate control capability, inhibit the tunneling leakage current of the gate and improve the device performance of the junction-free tunneling field effect transistor.
According to an embodiment of the present invention, the top gate and the electrostatic modulation gate are each independently formed of a metal material. Thus, different work functions and voltages applied thereto can adjust the carrier types and concentrations of different regions, respectively.
According to an embodiment of the invention, the two electrostatic modulation gates are arranged to adjust the doping type of the channel region by applying voltages of opposite polarity. Therefore, the adjustment of the doping type of the channel region can be realized by using simpler operation.
According to the embodiment of the invention, when the thickness of the gate dielectric is 1-5nm, the absolute value of the voltage applied to the electrostatic modulation gate is 1-4V, and the absolute value corresponds to different gate dielectric thicknesses, so that the gate control capability of a channel is ensured, and the gate oxide layer is not broken down. Thereby, adjustment of the doping type of the channel region can be achieved.
According to the embodiment of the invention, the subthreshold swing of the junction-free tunneling field effect transistor is less than 60 mV/dec. Thus, the power consumption of the junction-less tunneling field effect transistor can be reduced.
In another aspect of the invention, the invention provides a method of making the junction-free tunneling field effect transistor described above. According to an embodiment of the invention, the method comprises: forming an insulating layer over a substrate; forming a channel region on the insulating layer; forming a source electrode and a drain electrode on the insulating layer; forming a gate dielectric layer on the channel region; and arranging a grid electrode on the grid dielectric layer, wherein the grid electrode comprises a top grid and two electrostatic modulation grid electrodes. The method has at least one of the following advantages: the production process is simple, the doping concentration is flexible and adjustable, and the power consumption of the junction-free tunneling field effect transistor prepared by the junction-free tunneling field effect transistor is low.
According to an embodiment of the present invention, the channel region is formed on the insulating layer by transfer or by chemical vapor deposition. Thus, the channel region can be obtained by a simple production process, and the quality of a deposited film of the channel region can be effectively controlled.
According to an embodiment of the invention, the gate dielectric layer is formed by depositing a high-K dielectric by ALD. Therefore, the gate dielectric layer can be obtained by using a simple production process, and the thickness of the high-K dielectric can be effectively controlled.
Drawings
FIG. 1 shows a schematic structure of a junction-less tunneling field effect transistor according to an embodiment of the present invention;
FIG. 2 shows a schematic structure diagram of a junction-less tunneling field effect transistor according to another embodiment of the present invention;
FIG. 3 shows a schematic structure diagram of a junction-less tunneling field effect transistor according to another embodiment of the present invention; and
fig. 4 shows a flow chart of a method for manufacturing a junction-less tunneling field effect transistor according to an embodiment of the invention.
Description of reference numerals:
100: an insulating layer; 200: a channel region; 300: a source electrode; 400: a drain electrode; 500: a gate dielectric layer; 600: a gate electrode; 610: top gate; 620: an electrostatic modulation gate; 700: a substrate.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
The first feature may be directly on or directly under the second feature or may be indirectly on or directly under the second feature via intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In one aspect of the invention, the invention provides a junction-free tunneling field effect transistor. According to an embodiment of the present invention, referring to fig. 1, the junction-less tunneling field effect transistor includes: an insulating layer 100, a channel region 200, a source 300, a drain 400, a gate dielectric layer 500, and a gate 600. The channel region 200 is disposed on the insulating layer 100, the source 300 and the drain 400 are disposed on two sides of the channel region 200, the gate dielectric layer 500 is disposed on the channel region 200, the gate 600 is disposed on the gate dielectric layer 500, and the gate 600 includes a top gate 610 and an electrostatic modulation gate 620. Thus, the junction-free tunneling field effect transistor has at least one of the following advantages: the structure is simple, the preparation can be realized by utilizing a simpler process flow, the doping concentration is flexible and adjustable, the power consumption is lower, and the like.
The following describes the respective structures of the junction-less tunneling field effect transistor in detail according to the specific embodiment of the present invention:
according to the embodiment of the present invention, the kind of the junction-less tunneling field effect transistor is not particularly limited, and those skilled in the art can design the junction-less tunneling field effect transistor according to the requirements of practical use. The specific material for forming the insulating layer 100 of the junction-less tunneling field effect transistor is also not particularly limited, and may be selected by those skilled in the art according to the actual circumstances. For example, according to an embodiment of the present invention, the insulating layer 100 may be formed of an oxide material. For example, according to an embodiment of the present invention, the insulating layer 100 may be made of SiO2、AlO3And (4) forming.
According to an embodiment of the present invention, referring to fig. 2, the junction-less tunneling field effect transistor may further include a substrate 700. Specifically, the substrate 700 is located on the lower surface of the insulating layer 100. The material for the substrate is not particularly limited, and can be designed by those skilled in the art according to the actual circumstances. For example, substrate 700 may be constructed of conventional semiconductor materials in accordance with a specific embodiment of the present invention. Specifically, the substrate 700 may be formed of Si. Note that the junction-less tunneling field effect transistor may use the insulating layer 100 as a substrate (shown in fig. 1), or the insulating layer 100 may be located over the substrate 700 (shown in fig. 2).
The inventor finds that, through intensive research, the existing tunneling field effect transistor causes a trap-assisted tunneling effect due to defects in a channel and at an interface, so that off-state leakage is obviously increased, the subthreshold swing of the existing tunneling field effect transistor is deteriorated, and the subthreshold swing of the non-junction tunneling field effect transistor manufactured through experiments is far larger than a theoretical value (60 mV/dec). To improve this problem and reduce the power consumption of the junction-less tunneling field effect transistor, the channel region 200 may be formed of a two-dimensional thin film material having a bipolar on characteristic according to an embodiment of the present invention. Because the two-dimensional material has an ultrathin structure, the surface of the two-dimensional material has no dangling bond, and the interface of the two-dimensional material is in Van der Waals contact, the junction-free tunneling field effect transistor realized by the two-dimensional material has better grid control capability, and can effectively relieve or even avoid trap-assisted tunneling. The two-dimensional material with bipolar conduction characteristic can realize N-type doping and P-type doping with different concentrations under positive and negative grid voltages respectively. Therefore, the two-dimensional film material with the bipolar conduction characteristic is adopted to form the channel region, the doping type and the concentration of the channel region can be controlled by adjusting the grid voltage, the junction is not required to be formed by adopting ion implantation, the heat dissipation is reduced, and the process complexity is reduced. Therefore, the flexible and adjustable junction-free tunneling field effect transistor can be obtained. The term "bipolar conduction characteristic" means that electron and hole conduction is exhibited at positive and negative gate voltages, respectively.
According to an embodiment of the present invention, the channel region 200 may be formed of at least one of black phosphorus, tungsten diselenide, tungsten disulfide, graphene, and tungsten ditelluride. The materials all have bipolar conduction characteristics, so that the channel region can be formed by the materials which are wide in source and easy to obtain, and further the production cost can be saved.
The inventors have found through a lot of experiments that the thickness of the channel region 200 cannot be too large, and too thick results in the inability to turn off, thereby affecting the performance of the device. According to an embodiment of the present invention, referring to fig. 2, the thickness of the channel region 500 (D1 shown in the figure) is 6nm or less, and thus the junction-less tunneling field effect transistor realized thereby can achieve turn-off better.
The number and position of the electrostatic modulation gates 620 are not particularly limited according to the embodiment of the present invention, and may be designed by those skilled in the art according to practical circumstances. For example, referring to fig. 1, the junction-less tunneling field effect transistor may include one electrostatic modulation gate 620, and the electrostatic modulation gate 620 may be disposed near the source 300 or the drain 400, according to an embodiment of the present invention. Alternatively, referring to fig. 3, the junction-less tunneling field effect transistor may include two electrostatic modulation gates 620, and the top gate 610 may be disposed between the two electrostatic modulation gates 620, according to other embodiments of the present invention. Therefore, the control of the doping type of the channel region can be better realized.
According to an embodiment of the present invention, the source electrode 300 and the drain electrode 400 are independently formed of a metal, respectively, and the metals forming the source electrode 300 and the drain electrode 400 have different work functions. Therefore, different doping types can be formed at the source end and the drain end. It should be noted that the doping types of the source terminal and the drain terminal are not particularly limited, and those skilled in the art can design the doping types according to actual situations. For example, according to an embodiment of the present invention, for a P-type junction-free tunneling field effect transistor, the metal electrode of the source terminal 300 may be a low work function metal so as to facilitate the transmission of electrons, and the metal electrode of the drain terminal 400 may be a high work function metal so as to facilitate the transmission of holes, so that the performance of the junction-free tunneling field effect transistor may be further improved. Alternatively, for the N-type jfet, the metal electrode of the source terminal 300 may be a high work function metal, and the metal electrode of the drain terminal 400 may be a low work function metal, so as to further improve the performance of the jfet.
According to an embodiment of the present invention, the gate dielectric layer 500 may be formed of a high-K dielectric. Therefore, the thickness of the gate oxide can be increased, and the tunneling leakage current of the gate can be inhibited. For example, according to embodiments of the present invention, the gate dielectric layer 500 may be made of HfO2、ZrO2And Al2O3And at least one of HfZrOx. Therefore, the control capability of the device grid electrode on the source end tunneling effect can be enhanced. The inventor finds that the gate dielectric layer 500 with too thick thickness generates the fringe field effect, and the photolithography depth and the climbing during wiring will occur in the process productionAnd thus, the device performance is deteriorated, and therefore, the thickness of the gate dielectric layer 500 needs to be properly designed. For example, referring to fig. 2, the thickness of the gate dielectric layer 500 (D2 shown in the figure) may be 1-5nm, so that the occurrence of the fringe field effect and the gate tunneling effect may be well suppressed, and at the same time, sufficient gate control capability may be maintained, and the device performance of the jfet may be improved.
In order to further improve the performance of the junction-less tunneling field effect transistor, according to an embodiment of the present invention, the top gate 610 and the electrostatic modulation gate 620 are respectively and independently formed of a metal material. Specifically, the top gate 610 and the electrostatic modulation gate 620 are metal gates that are not connected to each other, and the kind of metal is not particularly limited as long as the function of the jfet can be implemented, and those skilled in the art can design the jfet according to actual situations. For example, according to the embodiment of the present invention, the top gate 610 and the electrostatic modulation gate 620 may be the same metal material or different metal materials. Therefore, good conductivity can be realized, and the signal transmission speed is improved. According to an embodiment of the present invention, the two electrostatic modulation gates 620 may be configured to adjust the doping type of the channel region 200 by applying voltages of opposite polarity. Specifically, the absolute value of the voltage applied to the electrostatic modulation gate 620 is 1-4V when the gate dielectric thickness is 1-5 nm. For example, according to an embodiment of the present invention, for a P-type junction-free tunneling field effect transistor, a source-side metal gate applies a positive voltage to form N-type doping, and a drain-side metal gate applies a negative voltage to form P-type doping. Or, for the N-type junction-free tunneling field effect transistor, a positive voltage is applied to the source end metal gate to form N-type doping, and a negative voltage is applied to the drain end metal gate to form P-type doping. Therefore, the adjustment of the doping type of the channel region can be realized by using simpler operation.
According to the embodiment of the invention, the subthreshold swing of the junction-free tunneling field effect transistor with the structure is less than 60 mV/dec. Thus, the power consumption of the junction-less tunneling field effect transistor can be reduced.
In another aspect of the invention, the invention provides a method of making the junction-free tunneling field effect transistor described above. According to an embodiment of the invention, referring to fig. 4, the method comprises:
s10: forming an insulating layer on a substrate
According to an embodiment of the invention, in this step an insulating layer with a thickness of 90-300nm is formed on the substrate by thermal oxidation or chemical vapor deposition growth. The detailed description of the specific material of the insulating layer has been made above, and is not repeated herein. For example, according to embodiments of the present invention, the insulating layer may be an oxide material. Specifically, the insulating layer may be made of SiO2、AlO3And (4) forming.
S20: forming a channel region on the insulating layer
According to an embodiment of the invention, in this step, a channel region is formed on the previously formed insulating layer. The material and thickness of the channel region have been described in detail above, and are not described again. For example, according to an embodiment of the present invention, the channel region is formed of a two-dimensional thin film material having a bipolar on characteristic. Specifically, the channel region may be formed of at least one of black phosphorus, tungsten diselenide, tungsten disulfide, graphene, and tungsten ditelluride, and has a thickness of 6nm or less. The formation method of the channel region is not particularly limited, and may be designed by those skilled in the art according to specific situations. For example, according to embodiments of the present invention, the channel region may be formed by transferring a two-dimensional thin film material onto the insulating layer or by chemical vapor deposition on the insulating layer.
S30: forming a source and a drain on the insulating layer
According to an embodiment of the present invention, in this step, a source electrode and a drain electrode are formed on the insulating layer. The materials and positions of the source and drain electrodes have been described in detail above, and are not described in detail here. For example, according to an embodiment of the present invention, both the source and the drain are formed of a metal material, the source metal and the drain metal have different work functions, and the source and the drain are disposed at both sides of the channel region. As will be understood by those skilled in the art, when forming the source electrode, a layer of photoresist may be coated on the insulating layer first, then the position of the source metal electrode is determined by electron beam exposure, then the source metal material is deposited by electron beam evaporation or magnetron sputtering, and then the photoresist is stripped and removed by using acetone, thereby forming the source metal electrode. Similarly, when the drain electrode is formed, a layer of photoresist may be coated on the insulating layer first, then the position of the drain metal electrode is determined through electron beam exposure, then the drain metal material is deposited through electron beam evaporation or magnetron sputtering, and then the photoresist is stripped and removed by using acetone, so as to form the drain metal electrode. Therefore, the metal electrode can realize good conductivity and improve the speed of signal transmission.
S40: forming a gate dielectric layer on the channel region
In this step, a gate dielectric layer is formed over the channel region using ALD deposited (atomic layer deposition) high K dielectric, according to an embodiment of the present invention. The material and thickness of the gate dielectric layer have been described in detail above, and are not described in detail here. For example, according to embodiments of the present invention, the gate dielectric layer may be made of HfO2、ZrO2And Al2O3At least one of HfZrOx and HfZrOx, and has a thickness of 1-5 nm.
S50: arranging a grid electrode on the grid dielectric layer
According to an embodiment of the invention, in this step, a gate electrode is disposed on the gate dielectric layer, the gate electrode including a top gate and an electrostatic modulation gate. The materials, the number and the positions of the top gate and the electrostatic modulation gate have been described in detail above, and are not described in detail herein. For example, according to an embodiment of the present invention, the top gate and the electrostatic modulation gate are both formed of a metal material, and the top gate and the electrostatic modulation gate may be the same kind of metal or different kinds of metals. The grid electrodes are not connected with each other, the grid electrodes can comprise a top grid and an electrostatic modulation grid electrode, the top grid is arranged in the middle of the channel region, and the electrostatic modulation grid electrode is arranged on one side close to the source electrode or the drain electrode. Or the grid comprises a top grid and two electrostatic modulation grids, the top grid is arranged in the middle of the channel region, and the two electrostatic modulation grids are respectively and independently arranged at the source end and the drain end. The formation method of the gate is not particularly limited, and a person skilled in the art can design the gate according to the specific situation. For example, according to the embodiment of the invention, in the gate forming process, a layer of photoresist is firstly coated on the gate dielectric layer, then the position of the metal gate is determined through electron beam exposure, then the gate electrode metal material is deposited through electron beam evaporation or magnetron sputtering, and then the photoresist is stripped and removed through acetone, so that the separated gate metal electrode is formed. Alternatively, the separated gate metal electrode may be formed by performing a bulk deposition of a metal material, followed by electron beam exposure and etching. Thus, the gate electrode can be obtained by a simple production process, thereby improving the gate control capability using the gate electrode.
In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (14)
1. A junction-less tunneling field effect transistor, comprising:
an insulating layer;
a channel region disposed on the insulating layer;
the source electrode and the drain electrode are arranged on two sides of the channel region;
the gate dielectric layer is arranged on the channel region;
the grid electrode is arranged on the grid dielectric layer and comprises a top grid and 2 electrostatic modulation grid electrodes, the top grid is arranged between the two electrostatic modulation grid electrodes, and the 2 electrostatic modulation grid electrodes are arranged to apply voltages with opposite polarities.
The channel region is formed of at least one of tungsten diselenide and tungsten ditelluride having a bipolar on characteristic.
2. The junction-free tunneling field effect transistor according to claim 1, wherein the channel region has a thickness of 6nm or less.
3. The junction-free tunneling field effect transistor according to claim 1, wherein the electrostatic modulation gate is disposed near the source or the drain.
4. The junction-less tunneling field effect transistor according to claim 1, wherein the source electrode and the drain electrode are each independently formed of a metal, and the metal forming the source electrode and the metal forming the drain electrode have different work functions.
5. The junction-free tunneling field effect transistor according to claim 1, wherein the gate dielectric layer is formed of a high-K dielectric.
6. The jfet of claim 5 wherein the gate dielectric layer is formed of HfO2、ZrO2And Al2O3And at least one of HfZrOx.
7. The junction-free tunneling field effect transistor according to claim 5, wherein the gate dielectric layer has a thickness of 1-5 nm.
8. The junction-free tunneling field effect transistor according to claim 1, wherein the top gate and the electrostatic modulation gate are each independently formed of a metal material.
9. The junction-free tunneling field effect transistor according to claim 1, wherein the two electrostatic modulation gates are configured to adjust the doping type of the channel region by applying voltages of opposite polarity.
10. The junction-free tunneling field effect transistor according to claim 9, wherein the absolute value of the voltage applied to the electrostatic modulation gate is 1-4V when the gate dielectric thickness is 1-5 nm.
11. The junction-less tunneling field effect transistor of claim 1, wherein the junction-less tunneling field effect transistor has a subthreshold swing of less than 60 mV/dec.
12. A method of manufacturing the junction-less tunneling field effect transistor according to any one of claims 1 to 11, comprising:
forming an insulating layer over a substrate;
forming a channel region on the insulating layer;
forming a source electrode and a drain electrode on the insulating layer;
forming a gate dielectric layer on the channel region; and
and arranging a grid electrode on the grid dielectric layer, wherein the grid electrode comprises a top grid and two electrostatic modulation grid electrodes.
13. The method of claim 12, wherein the channel region is formed on the insulating layer by transfer or by chemical vapor deposition.
14. The method of claim 12, wherein the gate dielectric layer is formed by ALD deposition of a high K dielectric.
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| CN103268889A (en) * | 2013-05-23 | 2013-08-28 | 清华大学 | Junction-free transverse tunneling field effect transistor |
| CN104241284A (en) * | 2013-06-06 | 2014-12-24 | 旺宏电子股份有限公司 | Dual-mode transistor devices and methods for operating same |
| CN105405875A (en) * | 2015-11-18 | 2016-03-16 | 湘潭大学 | Low off-state current tunneling field effect transistor |
| CN105742345A (en) * | 2016-03-09 | 2016-07-06 | 复旦大学 | Tunneling field-effect transistor and preparation method therefor |
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| CN103268889A (en) * | 2013-05-23 | 2013-08-28 | 清华大学 | Junction-free transverse tunneling field effect transistor |
| CN104241284A (en) * | 2013-06-06 | 2014-12-24 | 旺宏电子股份有限公司 | Dual-mode transistor devices and methods for operating same |
| CN105405875A (en) * | 2015-11-18 | 2016-03-16 | 湘潭大学 | Low off-state current tunneling field effect transistor |
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