WO2018094619A1 - Transistor à effet tunnel et son procédé de préparation - Google Patents

Transistor à effet tunnel et son procédé de préparation Download PDF

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WO2018094619A1
WO2018094619A1 PCT/CN2016/106986 CN2016106986W WO2018094619A1 WO 2018094619 A1 WO2018094619 A1 WO 2018094619A1 CN 2016106986 W CN2016106986 W CN 2016106986W WO 2018094619 A1 WO2018094619 A1 WO 2018094619A1
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conductive material
material layer
layer
drain
gate dielectric
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PCT/CN2016/106986
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English (en)
Chinese (zh)
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李伟
徐慧龙
张臣雄
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华为技术有限公司
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Priority to PCT/CN2016/106986 priority Critical patent/WO2018094619A1/fr
Priority to CN201680085756.8A priority patent/CN109155333B/zh
Publication of WO2018094619A1 publication Critical patent/WO2018094619A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a tunneling transistor and a method of fabricating the same.
  • TFETs tunnel transistors
  • their SS can be used at room temperature limits below 60mV/dec, which effectively reduces operating voltage and significantly reduces power consumption.
  • the existing TFET technology is mainly a homojunction TFET with silicon as a channel material and a heterojunction TFET with a III-V material as a channel. Since the silicon material has a large band gap and is an indirect bandgap semiconductor, the silicon-based TFET can obtain an SS of less than 60 mV/dec, but its on-state current is mostly less than 1 ⁇ A/ ⁇ m, which cannot meet the application requirements. Although the III-V material has a small band gap and a small effective mass, a heterojunction TFET based on a III-V material can obtain a large on-state current, but a heterojunction interface defect due to lattice mismatch. Etc. caused it to fail to obtain SS less than 60mV/dec.
  • Embodiments of the present invention provide a tunneling transistor and a method of fabricating the same to improve the conduction performance of a tunneling transistor.
  • Embodiments of the present invention provide a tunneling transistor including: a source, a drain, and a heterojunction; wherein the heterojunction includes a stacked first conductive material layer and a second conductive material layer, the first In the conductive material layer and the second conductive material layer, one conductive material layer is a material layer made of a two-dimensional material, and the other conductive material layer is a two-dimensional material or a three-dimensional material material layer; the source and the A first conductive material layer is electrically connected and insulated from the second conductive material layer, and the drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.
  • the channel material is a two-dimensional material with a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current.
  • two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current.
  • the gate With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.
  • the tunneling transistor further includes a gate dielectric layer and a gate metal layer, wherein the gate dielectric layer is disposed on the heterojunction, and the gate metal layer is disposed on the On the gate dielectric layer.
  • the gate dielectric layer covers the second conductive material layer, and the gate dielectric layer partially covers the first conductive material layer, and the gate dielectric layer covers A portion of the first conductive material layer is interposed between the source and the second conductive material layer. That is, the insulation between the source and the second conductive material layer is achieved by the gate dielectric layer.
  • the tunneling transistor further includes a substrate, and the first conductive material layer is a substrate of the tunneling transistor.
  • the method further includes an insulating layer disposed on the first conductive material layer, and the insulating layer covers a portion of the second conductive material layer, and the drain passes through the insulating layer and the first layer
  • the conductive material layer is insulated.
  • the method further includes an insulating layer, the first conductive material layer is provided with a groove, the insulating layer is disposed in the groove, and the drain is disposed on the insulating layer And partially covering the second conductive material layer.
  • the drain portion is covered on the insulating layer, and the edge of the insulating layer is exposed uncovered, thereby ensuring an insulating effect between the first conductive material layer and the drain.
  • the first conductive material layer and the second conductive material layer are stacked and partially staggered, and the second conductive material layer partially covers the first material layer; the first conductive layer An insulating layer is disposed on the material layer, and the source is insulated from the second conductive material layer by the insulating layer.
  • the substrate is provided with an isolation layer, and the source, the drain, the first conductive material layer, and the second conductive material layer and the first conductive material layer are not interlaced portions. Set in the isolation layer.
  • the two-dimensional material may be tungsten diselenide, tin diselenide or molybdenum telluride; the three-dimensional material may be: indium arsenide or silicon.
  • the embodiment of the invention further provides a method for fabricating the above tunneling transistor, the method comprising the following steps:
  • Forming a second conductive material layer on the first conductive material layer wherein one of the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is made of a two-dimensional material or a three-dimensional material.
  • a drain is formed, and the formed drain is electrically connected to the second conductive material layer and insulated from the first conductive material layer.
  • the channel material is a two-dimensional material of a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current.
  • two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current.
  • the gate With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.
  • the method further includes:
  • the method further includes:
  • Forming a groove on the first conductive material layer providing an insulating layer in the groove; and forming a second conductive material layer covering a portion of the insulating layer; when forming a drain, forming a drain at the second conductive The material layer is covered with a portion of the insulating layer.
  • the method further includes forming an insulating layer on the first conductive material layer, and the insulating layer covers a portion of the source.
  • the method before forming the first conductive material layer, the method further includes:
  • An isolation layer is formed on the substrate.
  • the method further includes: forming a gate dielectric layer on the second conductive material layer; and forming a gate metal layer on the gate dielectric layer.
  • the method further includes: when forming the gate dielectric layer, the gate dielectric layer partially covers the first conductive material layer, and the gate dielectric layer covers the first conductive layer A portion between the material layers is between the source and the second layer of conductive material.
  • FIG. 1 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention.
  • FIG. 1 are flowcharts showing the preparation of the tunneling transistor shown in FIG. 1 according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a tunneling transistor according to an embodiment of the present invention.
  • FIG. 4a to 4g are flowcharts showing the preparation of the tunneling transistor shown in FIG. 1 according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a tunneling transistor according to another embodiment of the present invention.
  • 6a-6f are flowcharts showing the preparation of the tunneling transistor shown in FIG. 5 according to an embodiment of the present invention.
  • FIG. 1 and FIG. 3 show tunneling transistors of different structures according to embodiments of the present invention.
  • the first conductive material layer 1 and the second conductive material layer 3 one conductive material layer is a material layer made of a two-dimensional material, and the other conductive material layer is a material layer made of a two-dimensional material or a three-dimensional material;
  • the source 2 is electrically connected to the first conductive material layer 1 and insulated from the second conductive material layer 3
  • the drain 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.
  • a heterojunction is used as a channel, and the channel material is a two-dimensional material or a three-dimensional material, and the surface of the two-dimensional material has an atomic-scale thin, no dangling bond, and the like, and is formed based on a two-dimensional material.
  • the heterojunction has no interface defects caused by lattice mismatch. Two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3eV), which increases the tunneling probability and increases the tunneling current.
  • tunneling transistors based on two-dimensional materials have stronger gate control, fewer interface defects, can effectively suppress leakage current, have larger tunneling area, and the formation of heterojunction. Simple, which facilitates the fabrication of tunneling transistors.
  • the tunneling transistor has a gate dielectric layer 5 and a gate metal layer 4, wherein the gate dielectric layer 5 is disposed on the heterojunction, and the gate metal layer 4 is disposed on the gate dielectric layer 5.
  • the gate-to-channel control can be enhanced, and the line tunneling structure is adopted, and the tunneling area is large, which can effectively increase the tunneling current.
  • the gate With a local gate structure, the gate only controls the heterojunction tunneling region.
  • the tunneling transistor has a substrate, and the first conductive material layer 1 is a substrate of a tunneling transistor. The use of a two-dimensional material as a substrate simplifies the structure of the tunneling transistor.
  • the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction.
  • the heterojunction acts as a channel structure.
  • the first conductive material layer 1 in the heterojunction acts as a substrate for the entire tunneling transistor.
  • the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is disposed, the insulating layer 6 is disposed at The first conductive material layer 1 is covered, and the insulating layer 6 covers a portion of the second conductive material layer 3 to form a step structure.
  • the drain electrode 7 When the drain electrode 7 is formed on the second conductive material layer 3, the drain electrode 7 partially covers the insulating layer 6.
  • the two-dimensional material (2D material) is tungsten diselenide (WSe 2), two tin selenide (SnSe 2) or molybdenum telluride (MoTe 2); three-dimensional material (3D material) to: arsenic Indium (InAs) or silicon (Si).
  • the two-dimensional material is a layered material having a thickness of 0.5-10 nm, such as: 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm. Any thickness between 10 nm, such as 10 nm.
  • the tunneling transistor is prepared as follows:
  • Step 1 Taking the InAs-WSe 2 heterojunction TFET preparation as an example, an n-doped InAs substrate is provided, which is the first conductive material layer 1, and the substrate is placed at 35% HF: 35% HCl. The oxide layer was removed in about 1:1 at 1:1, and the CVD-grown WSe 2 was transferred onto the InAs substrate to obtain a structure as shown in Fig. 2a.
  • Step 2 spin-coating the photoresist on the sample in step 1, exposing and developing the photoresist, using a photoresist as a mask, removing the exposed WSe 2 by dry etching, patterning the WSe 2 , and removing the light. Engraved mask. As shown in FIG. 2b, the patterned WSe 2 is the second conductive material layer 3.
  • Step 3 Form source 2. Applying a photoresist to the sample of step 2, defining the source 2 region by photolithography, then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form the source 2 contact, and removing the light using a liftoff process. Engraved. Figure 2c.
  • Step 4 Forming the insulating layer 6. Applying photoresist to the sample from step 3, using lithography definition The Oxide insulating layer 6 is then evaporated or ALD grown with an oxide insulating layer 6.
  • the insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide, and the photoresist is removed using a liftoff process. As shown in Fig. 2d, as shown in Fig. 2d, the insulating layer 6 is partially covered on the second conductive material layer 3.
  • Step 5 Prepare the drain 7.
  • a photoresist is applied to the sample of step 4, the drain 7 region is defined by photolithography, and then the metal Ti/Pt/Au (about 5/20/30 nm) is evaporated to form a drain 7 contact connected to WSe 2 .
  • the photoresist is removed using a liftoff process. A sample as shown in Figure 2e was obtained.
  • Step 6 Forming a gate dielectric layer 5 which, when specifically disposed, is a high K material.
  • the specific steps are as follows: applying a photoresist to the sample in step 5, defining a gate region by photolithography, and growing a high-k material yttrium oxide (or high-k material such as alumina or zirconia) by low-temperature atomic layer deposition, and steaming A gate metal (for example, Ti/Au: 5/50 nm) is plated, and the photoresist is removed using a liftoff process to obtain a sample as shown in FIG. 2f, thereby forming a gate metal layer 4 on the gate dielectric layer 5.
  • a gate metal for example, Ti/Au: 5/50 nm
  • the gate dielectric layer 5 and the gate metal layer 4 can be formed by using a long gate dielectric layer 5 and a gate metal layer 4, and then masked by photoresist.
  • the film is obtained by a wet etching method.
  • oxide deposition methods include, but are not limited to, ALD deposition, evaporation coating deposition.
  • FIG. 3 is a schematic structural diagram of another tunneling transistor according to an embodiment of the present invention.
  • the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, and a heterojunction.
  • the heterojunction acts as a channel structure.
  • the first conductive material layer 1 in the heterojunction acts as a substrate for the entire tunneling transistor. The material of each component in the embodiment is the same as that in the embodiment 1, and details are not described herein again.
  • the tunneling transistor in this embodiment further includes an insulating layer 6, and when the insulating layer 6 is disposed, the insulating layer 6 is disposed at On the first conductive material layer 1, specifically, the first conductive material layer 1 is provided with a recess 11 , the insulating layer 6 is disposed in the recess 11 , and the drain 7 is disposed on the second conductive material layer 3 and partially Covering the insulating layer 6, the isolation of the insulating layer 6 prevents the drain 7 and the first conductive material from appearing during processing. In the case where the material layer 1 is electrically connected, the partition between the drain electrode 7 and the first conductive material layer 1 is ensured. In order to ensure the barrier effect, it is preferable that the edge of the insulating layer 6 is not covered by the drain 7, thereby ensuring the effect of insulation.
  • the gate dielectric layer 5 provided in this embodiment covers the second conductive material layer 3, and the gate dielectric layer 5 portion Covering the first conductive material layer 1 , and a portion of the gate dielectric layer 5 covering the first conductive material layer 1 is interposed between the source 2 and the second conductive material layer 3 . That is, when the gate dielectric layer 5 is disposed, the disposed position of one end is located outside the second conductive material layer 3, so that one end of the gate dielectric layer 5 covers the first conductive material layer 1, that is, one end of the gate dielectric layer 5 is interposed. Between the source 2 and the second conductive material layer 3, insulation between the source 2 and the second conductive material layer 3 is achieved by the gate dielectric layer 5. Improved insulation.
  • the tunneling transistor is prepared as follows:
  • Step 1 Forming the insulating layer 6.
  • the substrate is a first conductive material layer 11, applying a photoresist on the InAs substrate, and defining an Oxide insulating layer 6 by photolithography, as shown in FIG. 4a, using the reaction Ion etching (RIE) etches a recess 11 on the InAs substrate.
  • the insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide by vapor deposition or ALD growth, and the photoresist may be removed by a lift off process. This is obtained as shown in Figure 4b.
  • Step 2 Transfer the second conductive material layer 3.
  • the structure shown in Figure 4c is obtained.
  • Step 3 spin-coating the photoresist on the sample in step 2, exposing and developing the photoresist, using a photoresist as a mask, removing the exposed WSe2 by dry etching, patterning the WSe2, and removing the photoresist. Mask. As shown in Figure 4d.
  • Step 4 Forming the source and drain electrodes 7. Applying a photoresist to the sample of step 3, defining the source and drain 7 regions by photolithography, and then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form source-drain 7 contacts, using lift off The process removes the photoresist. As shown in Figure 4e.
  • Step 5 Forming the gate dielectric layer 5. Applying a photoresist to the sample from step 4, using photolithography The gate area. As shown in FIG. 4f, a high-k gate dielectric yttrium oxide (or a high-k material such as alumina or zirconia) is grown by low-temperature atomic layer deposition, and a gate metal layer 4 (for example, Ti/Au: 5/50 nm) is evaporated and used. The lift off process removes the photoresist to give a sample as shown in Figure 4g.
  • a high-k gate dielectric yttrium oxide or a high-k material such as alumina or zirconia
  • a gate metal layer 4 for example, Ti/Au: 5/50 nm
  • one end of the gate dielectric layer 5 covers the first conductive material layer 1 and is interposed between the second conductive material layer 3 and the source 2.
  • the formation of the gate dielectric layer 5 and the gate metal layer 4 can be performed by using a photoresist and a gate metal, and then using a photoresist as a mask for wet etching. The method of etching is obtained.
  • FIG. 5 is a schematic structural diagram of another tunneling transistor according to an embodiment of the present invention.
  • the tunneling transistor includes a source 2, a drain 7, a gate metal layer 4, a gate dielectric layer 5, a heterojunction, a substrate 9, and an isolation layer 8; wherein the heterojunction serves as a channel structure.
  • the tunneling transistor includes a substrate 9 using a silicon substrate 9, a source 2, a drain 7, a first conductive material layer 1, and a second conductive material.
  • a portion of the layer 3 that is not interlaced with the first conductive material layer 1 is disposed on the substrate 9 and insulated from the substrate 9. Thereby, the substrate 9 is insulated from the heterojunction.
  • an isolation layer 8 is formed on the substrate 9, and the above structure is formed on the isolation layer 8, and the isolation layer 8 is oxidized in a specific arrangement. silicon.
  • the first conductive material layer 1 and the second conductive material layer 3 are stacked and partially staggered, and the second conductive material layer 3 partially covers the first material layer; the first conductive material layer 1 is provided with the insulating layer 6 The source 2 is insulated from the second conductive material layer 3 by the insulating layer 6.
  • Step 1 Providing WSe 2 material grown on the target substrate 9, or transferring the grown WSe 2 material onto the isolation layer 8 on the target substrate 9, and then performing WSe 2 by a method similar to that of Embodiment 1. Etching patterning. The result shown in Figure 6a is obtained.
  • Step 2 Prepare source 2. Applying a photoresist to the sample from step 1, using lithography to define the source The pole 2 region is then vapor-deposited with metal Ti/Pt/Au (about 5/20/30 nm) to form a source 2 contact, which is removed using a liftoff process.
  • Figure 6b
  • Step 3 Forming the insulating layer 6.
  • the photoresist is applied to the sample of step 2, the Oxide insulating layer 6 is defined by photolithography, and then the oxide insulating layer 6 is grown by evaporation or ALD.
  • the insulating layer 6 may be an insulating material such as silicon oxide or aluminum oxide. The lift off process removes the photoresist. As shown in Fig. 6c, a portion of the insulating layer 6 covers the source 2 and another portion overlies the first conductive material layer 1.
  • Step 4 Transfer the SnSe 2 material.
  • the grown SnSe 2 material is transferred onto the substrate 9.
  • SnSe 2 is patterned using the aforementioned etching process.
  • the step is a step of generating a second conductive material layer 3, as shown in FIG. 6d, the generated second conductive material layer 3 partially covers the first conductive material layer 1, partially covered in isolation.
  • the layer 8 such that the first conductive material layer 1 and the second conductive material layer 3 are stacked and partially staggered, and as shown in FIG. 6d, the formed second conductive material layer 3 and the source 2 are spaced apart
  • the insulating layer 6 prevents the source 2 and the second conductive material layer 3 from being turned on during processing.
  • Step 5 Form the drain 7. Applying a photoresist to the sample of step 4, defining a drain 7 region by photolithography, and then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form a drain 7 contact connected to SnSe2. The photoresist is removed using a liftoff process. A sample as shown in Figure 6e was obtained.
  • Step 6 Form a gate dielectric layer 5 which is a high-k material. Applying a photoresist to the sample of step 5, defining a gate region by photolithography, and growing a high-k material such as HfO 2 , Al 2 O 3 , ZrO 2 , Y 2 O 3 , etc. by low-temperature atomic layer deposition. Material, vapor-deposited gate metal (eg Ti/Au: 5/50 nm), the photoresist was removed using a lift off process to obtain a sample as shown in Figure 6f.
  • the gate dielectric layer 5 and the gate metal layer 4 can be formed by using a long gate dielectric layer 5 and a gate metal layer 4, and then masked by photoresist.
  • the film is obtained by a wet etching method.
  • oxide deposition methods include, but are not limited to, ALD deposition, evaporation coating deposition.
  • the tunneling transistor provided in this embodiment uses a heterojunction, which may be a heterojunction composed of 2D material and 2D material or 2D material and 3D material.
  • the channel material is controlled by a local gate.
  • the material of the knot is not limited to the above materials, but the following materials can also be used:
  • heterojunction TFET which heterostructure composition WSe 2 -SnSe 2, SnSe 2 -MoSe 2, SnSe 2 -MoTe 2 and the like.
  • the embodiment of the present invention further provides a method for fabricating the tunneling transistor described above, the method comprising the following steps:
  • a second conductive material layer 3 on the first conductive material layer 1, wherein one of the two conductive material layers is a material layer made of a two-dimensional material, and the other conductive material layer is a two-dimensional material or a three-dimensional material.
  • Forming the source 2, and the formed source 2 is electrically connected to the first conductive material layer 1 and insulated from the second conductive material layer 3;
  • the drain electrode 7 is formed, and the formed drain electrode 7 is electrically connected to the second conductive material layer 3 and insulated from the first conductive material layer 1.
  • the channel material is a two-dimensional material with a thin atomic level, which can enhance the control of the gate to the channel, adopts a line tunneling structure, has a large tunneling area, and can effectively increase the tunneling current.
  • two types of heterojunction structures are used, and the heterojunction interface barrier is small (less than 0.3 eV), which increases the tunneling probability and increases the tunneling current.
  • the gate With a local gate structure, the gate only controls the heterojunction tunneling region. The formation of the heterojunction is simple, and the heterojunction has no interface defects caused by lattice mismatch, and the leakage current can be effectively suppressed.
  • the method further includes:
  • the drain electrode 7 formed is located on the second conductive material layer 3 and covers a portion of the insulating layer 6.
  • a gate metal layer 4 is formed on the gate dielectric layer 5.
  • the method further includes:
  • the formed drain is on the second conductive material layer and covers a portion of the insulating layer.
  • the gate dielectric layer 5 When the gate dielectric layer 5 is formed, the gate dielectric layer 5 partially covers the first conductive material layer 1, and the portion of the gate dielectric layer 5 covering the first conductive material layer 1 is interposed The source 2 is between the second conductive material layer 3.
  • the method further includes: before forming the first conductive material layer 1 further comprising:
  • An insulating layer 6 is formed on the substrate.
  • An insulating layer 6 is formed on the first conductive material layer 1, and the insulating layer 6 covers a part of the source 2.
  • a gate metal layer 4 is formed on the gate dielectric layer 5.

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Abstract

L'invention concerne un transistor à effet tunnel et son procédé de préparation. Le transistor comprend une source, un drain et une hétérojonction. L'hétérojonction comprend une première couche de matériau conducteur et une seconde couche de matériau conducteur qui sont empilées. L'une des deux couches de matériau conducteur est constituée d'un matériau bidimensionnel, et l'autre des deux couches de matériau conducteur est une couche de matériau préparée en utilisant un matériau bidimensionnel ou tridimensionnel. La source est électriquement connectée à la première couche de matériau conducteur et est isolée de la seconde couche de matériau conducteur, et le drain est électriquement connecté à la seconde couche de matériau conducteur et est isolé de la première couche de matériau conducteur. Dans la solution technique, un matériau de tranchée est un matériau bidimensionnel, et une barrière d'interface de l'hétérojonction est petite (inférieure à 0,3 eV), ce qui permet d'augmenter la probabilité de tunnellisation, et d'augmenter un courant de tunnel. Une structure de grille locale est utilisée, et la grille commande juste une région de tunnellisation de l'hétérojonction. La formation de l'hétérojonction est simple, et l'hétérojonction ne présente pas de défaut provoqué par un désaccord de réseau, et par conséquent, la fuite d'un courant peut être efficacement limitée.
PCT/CN2016/106986 2016-11-23 2016-11-23 Transistor à effet tunnel et son procédé de préparation WO2018094619A1 (fr)

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