CN103579324A - 一种三面源隧穿场效应晶体管及其制备方法 - Google Patents

一种三面源隧穿场效应晶体管及其制备方法 Download PDF

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CN103579324A
CN103579324A CN201310576433.7A CN201310576433A CN103579324A CN 103579324 A CN103579324 A CN 103579324A CN 201310576433 A CN201310576433 A CN 201310576433A CN 103579324 A CN103579324 A CN 103579324A
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region
channel region
effect transistor
hard mask
source
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CN103579324B (zh
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黄如
黄芊芊
吴春蕾
王佳鑫
王阳元
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Peking University
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Peking University
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Priority to PCT/CN2014/074368 priority patent/WO2015070555A1/zh
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Abstract

本发明公开了一种三面源隧穿场效应晶体管及其制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。本发明利用三面源的强耗尽作用，器件能等效实现陡直的源结掺杂浓度的效果，更加显著地优化TFET器件的亚阈值斜率，并同时提升器件的导通电流，且栅和漏之间存在栅未覆盖区，一方面有效地抑制了器件的双极导通效应，同时能抑制小尺寸下源结边角处的寄生隧穿电流。该器件的制备方法简单且精确可控，利用刻蚀后外延的方法生成沟道能进一步有利于实现陡直的源掺杂浓度梯度和形成异质结，且后栅工艺的制备流程有利于集成形成高质量的高k栅介质/金属栅，进一步提高器件的性能。

Description

一种三面源隧穿场效应晶体管及其制备方法
技术领域
本发明属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域，具体涉及一种三面源隧穿场效应晶体管及其制备方法。 
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经到进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大，同时，传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题。 
为了能将器件应用在超低压低功耗领域，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研究者们提出了一种可能的解决方案，就是采用隧穿场效应晶体管（TFET）。TFET不同于传统MOSFET，其源漏掺杂类型相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，能突破传统MOSFET亚阈值斜率60mV/dec的限制，并且其漏电流非常小。TFET具有低漏电流、低亚阈值斜率、低工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制，TFET面临着开态电流小的问题，远远比不上传统MOSFET器件，极大限制了TFET器件的应用。另外，具有陡直亚阈值斜率的TFET器件在实验上也较难实现，这是因为实验较难在源结处实现陡直的掺杂浓度梯度以致器件开启时隧穿结处的电场不够大，这会导致TFET的亚阈值斜率相对理论值退化。因此，如何在源结实现陡直的掺杂浓度梯度而获得超低的亚阈值斜率，也成为了TFET器件的另一个重要问题。 
发明内容
本发明的目的在于提出一种三面源隧穿场效应晶体管及其制备方法。利用三面源的强耗尽作用，该器件能等效实现陡直的源结掺杂浓度的效果，更加显著地优化TFET器件的亚阈值斜率，并同时提升器件的导通电流，且栅和漏之间存在栅未覆盖区，一方面有效地抑制了器件的双极导通效应，同时能抑制小尺寸下源结边角处的寄生隧穿电流。该器件的制备方法简单且精确可控，利用刻蚀后外延的方法生成沟道能进一步有利于实现陡直的源掺杂浓度梯度和形成异质结，且后栅工艺的制备流程有利于集成形成高质量的高k栅介质/金属栅，进一步提高器件的性能。 
本发明的技术方案如下： 
本发明隧穿场效应晶体管如图1所示，包括一个半导体衬底（1）、一个沟道区（6）、一个高掺杂源区（3）、一个低掺杂漏区（4）、一个栅介质层（7）和一个控制栅（8），其特征在于，沟道区（6）呈长方体状，从水平方向上看，沟道区（6）一侧延伸到高掺杂源区（3）内部，另一侧与低掺杂漏区（4）连接，从垂直方向上看，沟道区（6）位于控制栅（8）和栅介质层（7）的下方，且延伸到高掺杂源区（3）内部的沟道区（6）被高掺杂源区（3）三面包围，未延伸到高掺杂源区（3）内部的沟道区（6）被半导体衬底（1）包围，控制栅（8）和低掺杂漏区（4）之间存在水平间距，控制栅（8）覆盖了高掺杂源区（3）和部分沟道区（6），低掺杂漏区（4）和高掺杂源区（3）掺有不同掺杂类型的杂质，且低掺杂漏区（4）的掺杂浓度在5×1017cm-3至1×1019cm-3之间，高掺杂源区（3）的掺杂浓度在1×1019cm-3至1×1021cm-3之间。半导体衬底（1）和沟道区（6）的掺杂浓度在1×1014cm-3至1×1017cm-3之间。长方体状的沟道区（6）的宽和高相等，且小于一倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um，沟道区（6）的长大于宽和高，沟道区（6）的长度和宽高的比例为1.5:1-5:1。低掺杂漏区（4）和控制栅（8）之间的水平间距为10nm-1μm。 
上述隧穿场效应晶体管的制备方法，包括以下步骤： 
（1）在半导体衬底上通过浅槽隔离定义有源区； 
（2）光刻暴露出源掺杂区，以光刻胶为掩膜，离子注入形成高掺杂源区； 
（3）光刻暴露出漏掺杂区，以光刻胶为掩膜，离子注入形成另一种掺杂类型的低掺杂源区，然后快速高温热退火激活掺杂杂质； 
（4）淀积硬掩膜材料，接着光刻和刻蚀硬掩膜材料，露出沟道区所在的水平图形，图形内包含了部分高掺杂区和部分半导体衬底区； 
（5）在硬掩膜的保护下刻蚀出沟道区所在的长方体区； 
（6）在硬掩膜的保护下进行选择外延，外延生长出轻掺杂沟道区，并以硬掩膜为停止层进行化学机械平坦化（CMP）； 
（7）接着在硬掩膜的保护下刻蚀掉一定厚度的外延材料，厚度和硬掩膜的厚度一致，腐蚀去除硬掩膜层，之后用牺牲氧化或氢气退火的方法减小表面粗糙度； 
（8）生长栅介质层，并淀积控制栅材料，接着光刻和刻蚀，形成控制栅图形，控制栅和低掺杂漏区之间存在一定间距； 
（9）最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得所 述的隧穿场效应晶体管。 
上述的制备方法中，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅（SOI）或绝缘体上的锗（GOI）。 
上述的制备方法中，所述步骤（6）中的外延生长出的沟道区的材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体。 
上述的制备方法中，所述步骤（6）中的外延生长的方法选自同质外延和异质外延。 
上述的制备方法中，所述步骤（8）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。 
上述的制备方法中，所述步骤（8）中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。 
上述的制备方法中，所述步骤（9）中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。 
本发明的技术效果如下： 
一、本发明隧穿场效应晶体管的三面高掺杂源区提供的PN结能有效耗尽沟道区，如图1b所示，能使得栅下表面沟道能带提高，因此当该器件发生带带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度，等效实现了陡直的隧穿结掺杂浓度梯度的效果，从而大幅提高传统TFET的亚阈特性。同时相比平面条形栅的结耗尽型隧穿场效应晶体管，由于平面结构只能靠两边PN结耗尽，因此本发明的三面包围结构能更加有效调制隧穿结，获得更加陡直的亚阈特性。 
二、本发明采用了短栅的设计，即控制栅部分覆盖沟道区，在栅和漏之间存在一定间距的未覆盖区域。这种设计不仅可以有效抑制漏结处的隧穿，即常规TFET中的双极导通效应，还能有效降低栅电极对未覆盖区的影响，因此可以抑制小尺寸下寄生隧穿结的隧穿，寄生隧穿结发生的区域如图1c中C点所示位置。因此能降低器件开启时的亚阈值斜率。另外，漏区掺杂浓度较低也能进一步抑制双极导通效应。 
三、该器件的制备工艺简单可控，利用了刻蚀再外延生长的方法能精确控制沟道区的形貌。相比传统隧穿晶体管中源漏扩散会导致实际的沟长小于栅长定义出来的沟长，该器件采用刻蚀的方法定义出沟道长度和宽度，有利于控制制备出的沟道区的形貌，且在本制备流程中，由于在定义沟长和沟宽之前已经进行了源漏激活退火工艺，因此，源漏扩散并不会对实 际沟道区造成影响。 
四、本器件的制备方法中，外延生长沟道区的方法一方面有利于实现在源结处非常陡峭的掺杂浓度梯度，另一方面如果采用异质外延的方法，可以方便地实现隧穿场效应晶体管异质结的设计。陡峭的掺杂浓度梯度和异质结的设计，都能使得制备得到的隧穿场效应晶体管有更陡的带带隧穿结，更小的隧穿势垒宽度，因此能实现更高的开态电流和更低的亚阈值斜率。 
五、该器件的制备工艺流程中，采用先形成源漏区并高温激活、后形成控制栅的方法，有利于集成形成高质量的高k栅介质/金属栅，防止了高k栅介质/金属栅在前栅工艺中高温激活过程产生的退化，而采用高k栅介质/金属栅的隧穿场效应晶体管能进一步提高器件的性能，获得更有效的栅控以及有更强的等比例缩小能力。且本发明的控制栅并不需要和源区或者漏区的边缘对准，因此使得本制备方法中的后栅工艺相比传统MOSFET的后栅工艺更加简单，工艺要求也更加放宽。 
简而言之，该器件的结构采用高掺杂源区三面包围的沟道区的设计有效调制了源端隧穿结，并且抑制了双极导通效应和小尺寸下的寄生隧穿结的隧穿。且该器件的制备方法简单可控，采用了刻蚀和外延生长沟道区的方法有利于精确控制沟道区，并实现非常陡峭的隧穿结，从而进一步提高了器件的亚阈和开态特性，并采用更加简单的后栅工艺有利于集成高质量的High-k栅介质/金属栅，提升器件的性能。与现有的TFET相比，采用本制备方法的TFET器件可以得到更高的导通电流和更陡直的亚阈值斜率,且能保持低的泄漏电流，有望在低功耗领域得到采用，有较高的实用价值。 
附图说明
图1a是本发明的三面源隧穿场效应晶体管的器件示意图，图1b是沿图1a中AA’方向的器件剖面图，图1c是沿图1a中BB’方向的器件剖面图； 
图2是光刻暴露出源区并离子注入形成高掺杂源区后的器件示意图； 
图3是光刻暴露出漏区并离子注入形成相反类型的低掺杂漏区后的器件示意图； 
图4是淀积硬掩膜层后光刻刻蚀出沟道区所在的水平图形后的器件示意图； 
图5a是在硬掩膜的保护下刻蚀出沟道区所在的长方体后的器件示意图，图5b是沿图5a中AA’方向的器件剖面图； 
图6是外延生长沟道区材料并进行CMP后的器件示意图； 
图7a是刻蚀掉一定厚度的外延材料，并去除硬掩膜层之后的器件示意图，图7b是沿图 7a中AA’方向的器件剖面图； 
图8是生长栅介质层并淀积栅材料后的器件示意图； 
图9是光刻并刻蚀形成控制栅图形后的本发明的三面源隧穿场效应晶体管的器件示意图； 
图中： 
1——半导体衬底                      2——光刻胶 
3——高掺杂源区                      4——低掺杂漏区 
5——硬掩膜层                        6——沟道区 
7——栅介质层                        8——控制栅 
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。 
本发明制备方法的一具体实例包括图2至图9所示的工艺步骤： 
1、在晶向为（100）的体硅硅片硅衬底1上采用浅槽隔离技术制作有源区隔离层，衬底掺杂浓度为轻掺杂；光刻暴露出源掺杂区，以光刻胶2为掩膜进行P+离子注入，形成高掺杂源区3，离子注入的能量为40keV，注入杂质为BF2 +，如图2所示。 
2、光刻暴露出漏掺杂区，以光刻胶2为掩膜，离子注入形成低掺杂N漏区4，离子注入的能量为50keV，注入杂质为As+，如图3所示；进行一次快速高温退火，激活源漏掺杂的杂质。 
3、淀积硬掩膜层5，硬掩膜层为Si3N4，厚度为500nm-1μm；光刻暴露出沟道区所在的水平图形，并刻蚀硬掩膜材料直至露出部分高掺杂源区3和部分半导体衬底区1，如图4所示。 
4、在硬掩膜层5的保护下，各向异性刻蚀硅材料层，刻蚀的厚度和沟道区的宽度一致，为25nm-1.5um，如图5a、5b所示。 
5、在硬掩膜层5的保护下，在暴露出硅的窗口内外延硅，并以硬掩膜5为停止层进行化学机械平坦化（CMP），得到轻掺杂浓度的沟道区6，如图6所示。 
6、在硬掩膜层5的保护下，各向异性刻蚀外延出的硅6，刻蚀厚度和硬掩膜层5的厚度 一致，为500nm-1μm；用湿法腐蚀的方法腐蚀掉硬掩膜层5，之后进行热氧化，漂掉表面生成的SiO2，从而获得较低粗糙度的表面，如图7a、7b所示。 
7、热生长一层栅介质层7，栅介质层为SiO2，厚度为1～5nm；淀积栅材料，栅材料为掺杂多晶硅层，厚度为150～300nm，如图8所示。 
8、光刻暴露出控制栅图形，刻蚀栅材料直到栅介质层7，形成控制栅8，控制栅8和低掺杂漏4之间存在间距，间距大小为10nm-1μm，如图9所示。 
最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得所述的三面源隧穿场效应晶体管。 
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。 

Claims (9)

1.一种隧穿场效应晶体管，包括一个半导体衬底（1）、一个沟道区（6）、一个高掺杂源区（3）、一个低掺杂漏区（4）、一个栅介质层（7）和一个控制栅（8），其特征在于，沟道区（6）呈长方体状，从水平方向上看，沟道区（6）一侧延伸到高掺杂源区（3）内部，另一侧与低掺杂漏区（4）连接，从垂直方向上看，沟道区（6）位于控制栅（8）和栅介质层（7）的下方，且延伸到高掺杂源区（3）内部的沟道区（6）被高掺杂源区（3）三面包围，未延伸到高掺杂源区（3）内部的沟道区（6）被半导体衬底（1）包围，控制栅（8）和低掺杂漏区（4）之间存在水平间距，控制栅（8）覆盖了高掺杂源区（3）和部分沟道区（6），低掺杂漏区（4）和高掺杂源区（3）掺有不同掺杂类型的杂质，且低掺杂漏区（4）的掺杂浓度在5×1017cm-3至1×1019cm-3之间，高掺杂源区（3）的掺杂浓度在1×1019cm-3至1×1021cm-3之间。
2.如权利要求1所述的隧穿场效应晶体管，其特征在于，半导体衬底（1）和沟道区（6）的掺杂浓度在1×1014cm-3至1×1017cm-3之间。
3.如权利要求1所述的隧穿场效应晶体管，其特征在于，长方体状的沟道区（6）的宽和高相等，且小于一倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um，沟道区（6）的长大于宽和高，沟道区（6）的长度和宽高的比例为1.5:1-5:1。
4.如权利要求1所述的隧穿场效应晶体管，其特征在于，低掺杂漏区（4）和控制栅（8）之间的水平间距为10nm-1μm。
5.制备权利要求1所述的隧穿场效应晶体管的方法，包括以下步骤：
（1）在半导体衬底上通过浅槽隔离定义有源区；
（2）光刻暴露出源掺杂区，以光刻胶为掩膜，离子注入形成高掺杂源区；
（3）光刻暴露出漏掺杂区，以光刻胶为掩膜，离子注入形成另一种掺杂类型的低掺杂源区，然后退火激活掺杂杂质；
（4）淀积硬掩膜材料，接着光刻和刻蚀硬掩膜材料，露出沟道区所在的水平图形，图形内包含了部分高掺杂区和部分半导体衬底区；
（5）在硬掩膜的保护下刻蚀出沟道区所在的长方体区；
（6）在硬掩膜的保护下进行选择外延，外延生长出轻掺杂沟道区，并以硬掩膜为停止层进行化学机械平坦化；
（7）接着在硬掩膜的保护下刻蚀掉一定厚度的外延材料，厚度和硬掩膜的厚度一致，腐蚀去除硬掩膜层，之后用牺牲氧化或氢气退火的方法减小表面粗糙度；
（8）生长栅介质层，并淀积控制栅材料，接着光刻和刻蚀，形成控制栅图形，控制栅和低掺杂漏区之间存在一定间距；
（9）最后进入常规CMOS后道工序，即可制得如权利要求1所述的隧穿场效应晶体管。
6.如权利要求5所述的制备方法，其特征在于，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
7.如权利要求5所述的制备方法，其特征在于，所述步骤（6）中的外延生长出的沟道区的材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体。
8.如权利要求5所述的制备方法，其特征在于，所述步骤（8）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
9.如权利要求5所述的制备方法，其特征在于，所述步骤（9）中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
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