TW201236154A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TW201236154A
TW201236154A TW100141577A TW100141577A TW201236154A TW 201236154 A TW201236154 A TW 201236154A TW 100141577 A TW100141577 A TW 100141577A TW 100141577 A TW100141577 A TW 100141577A TW 201236154 A TW201236154 A TW 201236154A
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strain
gate
nanowire
semiconductor material
region
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TW100141577A
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Kirsten Emilie Moselund
Siefried Friedrich Karg
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a semiconductor device (1) comprising: at least a nanowire (2) configured to comprise: at least a source region (3) comprising a corresponding source semiconductor material, at least a drain region (4) comprising a corresponding drain semiconductor material and at least a channel region (5) comprising a corresponding channel semiconductor material, the channel region (5) being arranged between the source region (3) and the drain region (4), at least a gate electrode (6) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of the channel region (5), and at least a strain gate (7) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of a segment of the nanowire (2), the strain gate (7) being configured to apply a strain to the nanowire segment (8), thereby to facilitate at least an alteration of the energy bands corresponding to the source region (3) relative to the energy bands corresponding to the channel region (5).

Description

201236154 、發明說明： 【發明所屬之技術領域】 本發明係關於一半導體裝置及其製造方法。 【先前技術】 穿隨式場效電晶體(FET)可用於多種應用上，包含高速 切換及邏輯電路4同於魏麵的場效電晶體，穿隨式場 效電晶體的反轉次臨界斜率並不限於如費米統計的波兹恩 尾，所決定之室溫下60mV/dec。因此，穿隧式場效電晶； 可忐具有比先前提出的裝置較快的啟動，亦即促進從「 (ON)」（傳導狀態)到「關閉(〇FF)」（非傳導狀態)之轉換的 壓範圍係小於在先前提出裝置㈣況巾，且臨界及操作電壓 兩者皆可降低，而無裝置效能的對應惡化。這使得穿隨 政電晶體特別適合用於需要低功率消耗的應用。 直到最近，MOSFET尺寸的比例調整已經足以達到改盖 的裝置效能。只是最近錢與其侧驗制⑽如次臨二 動）變得明顯而阻礙了進一步的電壓比例調整。因此，相b 於MOSFET具有相對降低的功率消耗之裝置已有研究，且 在這方面，穿隧式場效電晶體已經成為很受看好的選 與基於矽的穿隧式場效電晶體相關的一個問題為相 大的矽能隙所造成之降低的載子帶對帶穿隧效率，此止， 這樣一個裝置之相對低的「開啟」電流，即當襞置在一= 狀態時。這可造成例如在齡邏輯操作(其f 啟電流)上之一增加的延遲。 對n的開 201236154 ^知對半導體的應變應用可能影響其_寬度及/或穿 隨質量。已有研究指出在奈米線上的應變應料能影響 體的能帶結構’其巾相較於若半導體形成例斜面裝置及/ 或結構之基礎，奈米線係製造至更A的細。就此而言 考 Sajjad 等人於 2009 年在 joumal of AppUed physies，1〇5 044307頁所發表，其報告了在珍(刚)奈米線中的能隙係获 由應用張力及魏應力兩者至奈米_大幅崎低，且電^ 等效質量亦由這類動作而降低。在基於三五族緖上的應/變 效應一般研究的範圍係小於例如基於矽系統。就此而言，已 顯示神化嫁(GaA__寬度在2·3%之實際可獲得^應 值下約增加100-200mV。 、 有關穿隧式場效電晶體，已知帶對帶穿隧效率可藉由將 穿隧式場效電晶體所基於之半導體材料系統之能隙^減而 改善。然而，若這遍及穿隧式場效電晶體的整體結構(即針 對穿隧式場效電晶體的源極、汲極、及閘極全部）而實行， 則這可能導致一增加的漏電流(1〇1?1〇，其可例如影響穿隧式 場效電晶體可從一傳導開啟狀態至一非傳導關閉狀態切換 (反之亦然）的可靠度及可控制性，因而使其在高速切換應用 中不受歡迎。特別地，由於穿隧式場效電晶體的主要應用領 域係視作需要降低功率消耗的情況，此一漏電流將不利地增 加整體的功率消耗，因而抵消了穿隧式場效電晶體的潛在^ 勢。 為了改善帶對帶穿隧效率，已經提出基於在異質材料系 統上的穿隧場效電晶體’藉此僅源極由具有比石夕小之能隙^ 一半導體所取代。就此而言，參考Verhulst等人於2008年 在 IEEE Electron Device Letters，29 冊，1-4 頁所發表，其中分 201236154 =揭路了基於奈米線之異質結構n型穿隨場效電晶體及p型 穿隨場效電晶體。針對n型穿隨TFET的改善穿隨效率， ^rliulst等人彳;j;報告在源極通道接面的能帶不連續性應於價 帶9這藉由例如在η型穿隨TFET巾使用石夕錯(siGe)作為針 對源極的半導體材料以及使时針對通道祕得。相反地， 針對P型穿隧TEET ’其純告在祕通道接面的能帶不連 續性應於導帶錢善穿隧效率，這藉由例如自坤化銦録 (InGaAs)製造源極於一基於石夕的通道上而獲得。 雖然從異質結構製造的穿隨場效電晶體理論上在能帶 對齊方面係呈現有利的特性，但構成異質結構之不同材料間 的晶格不匹配可能導致缺陷形成於其介面。若此介面係位於 穿隧接面（即在源極通道介面)附近，則可能惡化穿隧效率， 因為載子很可能參與缺陷協助穿隧而非直接的帶對帶穿隧。 在先前提出的裝置中，穿隧接面係使用雜質摻雜而製 造。在此情況中，技術上的挑戰為使穿隧接面盡可能的陡 峭，此條件係有助於載子橫越穿隧接面之穿隧的發生。可能 促成此一挑戰的一因素為一般用於雜質摻雜的熱處理可能 傾向「抹除(smear out)」發生載子穿隧所橫跨的穿隧接面， 因為熱處理係造成摻雜區域的擴散寬化及製程的不相容。舉 例來說，在穿隧場效電晶體係基於垂直奈米線製程的情況 中，所遭遇到的另一挑戰為產生一陡峭穿隧接面於奈米線基 部。此外，在某些材料中，兩種極性的化學摻雜可能是具有 挑戰性的，其係例如由於相關於在成長過程中一所需摻雜之 併入原子的困難。 現在參考 Lee 等人於 2004 年在 Applied Physics Letters， 201236154 145·147胃所發表’其中報告靜電掺雜可減輕相關於 換雜的某些缺點’_是關於具有相對窄溫度舰的材 丨如三五族魏）’且其帽由雜歸雜及/或其他先前提 法來達成足夠之一或兩種極性之活化摻雜物相較於矽 =情况是具有挑戰性的，而，此文件係關於實施靜電換雜 ^平，裝置’制是MOSFET。其無教示使用靜電摻雜連同 随場效電晶體’制是垂直製程及/或裝置，像是例如垂 直奈米線穿隧場效電晶體。 【發明内容】 根據本發明第一態樣之一具體實施例，提供了一種半導 體，置’其包含：至少—奈米線，組態以包含：含一對應源 極半導體材料之至少—源極區域、含—對應祕半導體材料 之至少一汲極區域、以及含一對應通道半導體材料之至少一 通道區域，通道區域係安排於源極區域與汲極區域之間；至 少一閘極電極’相對奈米線而安排以環狀地圍繞通道區域之 至少一部分；以及至少一應變閘極，相對奈米線而安排以環 狀地圍繞奈米線m段之至少—部分，應變雜係組態以 施加一應變至奈米線區段，藉此而促進對應源極區域之能帶 相對於對應通道區域之能帶的至少一變更。由於在本發明一 具體實施例中的應變應用特性，可促進對應源極區域之能帶 相對於對應通道區域之能帶的一改變。特別地，藉由應變應 用至奈米線區段，與其對應之半導體材料的能隙可調整(更 佳為降低）。這具有改變對應源極區域之能帶與對應通道區 域之能帶的帶對齊之效應，較佳地，源極區域與通道區域之 能帶之間的帶對齊係改變使得源極區域的能隙相對通道區 201236154 域的能隙為降低。如此，可降低源極區域及通道區域之間穿 隧接面的阻障尚度，藉此改善本發明一具體實施例中載子橫 跨穿隨接面之穿隧效待目較於先前提出的裝置）。在藉應變 ，用之源極區域的能隙降低之外(或與其無關），可改變橫越 穿随接面之載子的穿㈣量，其有助於載子橫越穿随接面之 一改良的請速率，藉此而促成本發明具體實侧之-改良 的穿隧效率(相較於先前提出的裝置）。載子的穿隧質量之改 變可藉由改變相對於對應通道區域之能帶的曲率之對應源 極區域之能帶的曲率而促成。 手父狂您*’應變閘極係可組態以施加一 米線區段，藉此而促進奈米線區段的靜電掺雜。本== ，實施例可組態以經由應變閘極而施加—應變閘極偏^ 由適當的選擇應變閘極偏壓，對應奈米線區 t + v體材料可由所需極性的載子所摻雜，此，可 不米線區段的靜電摻雜。相關 靜電摻雜的優點為，摻雜可實f上不需任月何化、 :=:=:虛靜電掺雜的另-優點為其= =⑽有「塗抹(—)」穿_之_= 加寬 為不想要的特徵，因為其可能造成載伟^接面接 =題=::=5= 體材料系統(像是例如三五族化a物半導體;=對某些半導 :相對重要的設計及/或製程優；，因為:)三可呈 統的-或兩種極性之雜質摻雜相較於在“情 8 201236154 的；藉由習知掺雜方法而達到足夠之任—極性的活 統中可能具有挑戰性，且此材料系統具 線區段之極可組態以實施奈米 以眘3地’奈米線係實質地垂直對齊。因為應變閘極可用 万加應變及靜電摻雜之雙功能，本發 =(置特=由垂直對齊奈米線而實施時)相較= 始純置可更料的達成。此外，因為應賴極係於奈米 向延伸’可降低關於空間偈限的問題。相關於本發明 ^實施例之某些尺寸及/或結構可藉由其經由垂直對齊奈 =線(而非平面組態)之實施而有較麵控制。在本發明具體 施例係由垂直奈米線所實施的情況，應賴簡隙壁較佳 係形成於應㈣極之·^鱗徵提供了降低的寄生電容之優 較佳地’至少一閘極介電質係共形地提供於奈米線的外 表面曰上。有助於個別載子侷限於至少源極區域及通道區域中 (使得產生於其paH隨面的㈣度增加)之介電材料可選 擇作為閘極介電質。此條件—般可藉由具有相對於真空在強 度上大於4之介電常數的一介電材料而滿足。此材料的一範 例為·一氧化珍或氧化給。 較佳地，在本發明一具體實施例中，應變閘極包含一金 201236154 屬。在本發明一具體實施例係操作使得應變閘極係用以靜電 地摻雜對應奈米線區段之半導體材料的情況中（其係藉由應 用—應變閘極偏壓至應變閘極而完成），除了施加應變至奈 米線區段，應變閘極係選擇以包含導電材料，像是例如金 屬。就此而言，在本發明一具體實施例中，氮化组(TaN)可 使用作為應變閘極材料。 較佳地，隔離層係提供於閘極電極與應變閘極之間。隔 離層係電性隔離閘極電極與應變閘極，且可例如包含介電材 料。如此，可避免閘極電極及應變閘極的電性短路，且可改 善本發明一具體實施例操作的可靠度。 較佳地，在本發明一具體實施例中，源極半導體材料、 汲極半導體材料及通道半導體材料係相同。此特徵可提供降 低製造複雜度的優點，且無潛在的缺陷於對應這些材料之奈 米線的不同區域之間的介面。就此而言，源極半導體材料、 汲極半導體材料及通道半導體材料可選擇以包含以下之 ’第四族元素及其二兀化合物。 或者，在本發明一具體實施例中，源極半導體材料係不 同於至少通道半導體材料。在此情況中’可能有相關於在源 極區域/通道區域介面處之源極半導體材料及通道半導體 料之間之晶格不匹配的缺陷。然而，與其相關的缺點(特別 是穿隧效率的惡化)可藉由本發明具體實施例之應變應用特 徵而至少部分地抵消。在此情況中，源極半導體材料係選擇 以包含以下之一：三五族材料系統、及其二元、三元及四元 化合物。或者’源極半導體材料可選擇例如包含第四族二_ 化合物’例如SiGe。 凡 201236154 較佳地，本發明一具體實施例包含以下之一：一穿隧場 效電晶體、一金屬氧化物半導體場效電晶體以及一碰撞游離 場效電晶體。本發明一具體實施例的優點（亦即有助於對應 奈米線區段之半導體材料能隙的降低及/或載子之穿隧質量 的降低)可為有益的：針對在奈米線金屬氧化物半導體場效 電晶體(MOSFET)中的源極注入速度；在穿隧場效電晶體中 之穿隧效率以及在碰撞游離場效電晶體中之碰撞游離速度。 亦提供了對應的方法態樣，因此根據本發明第二態樣之 一具體實施例，提供了一種用以製造一半導體裝置之方法， 已含以下步驟：提供至少一奈米線，其係組態以包含：含一 對應源極半導體材料之至少一源極區域、含一對應没極半導 體材料之至少一汲極區域、以及含一對應通道半導體材料之 至少一通道區域’通道區域係安排於源極區域與汲極區域之 間；形成至少一閘極電極，其係相對奈米線而安排以環狀地 圍繞通道區域之至少一部分；形成至少一應變閘極，其係相 對奈米線而安排以環狀地圍繞奈米線之一區段的至少二部 分，以及組態應變閘極以施加一應變至奈米線區段，藉此而 促進對應源極區域之能帶相對於對應通道區域之能^ $ 少一改變。 、 任何裝置特徵可應用於本發明的方法態樣，反之亦然。 本發明一態樣的特徵可應用於本發明另一態樣。任何所揭+ 之具體實施例可與所顯示及/或所描述之一或多個其他具= 實施例組合》這對具體實施例的一或多個特徵亦為可能/的。 【實施方式】 201236154 在描述中，相同的元件符號或記號係用以指示相同的構 件或類似者。 現在參考圖1，其示意性地描述根據本發明一裝置態樣 的一具體實施例。 由圖1中可看出’本發明之具體實施例包含一穿隧式場 效電晶體1，其可藉由一奈米線2而實施。在本發明具體實 施例之此特定範例中，奈米線2係實質地垂直對齊且由一本 質半導體基板所成長/餘刻出。奈米線2係組態以具有至少 三個不同的區域：包含一對應源極半導體材料之至少一源極 區域3、包含一對應汲極半導體材料之至少一汲極區域4、 以及包含一對應通道半導體材料之至少一通道區域5(其係 設置於源極區域3與汲極區域4之間）。由圖】可看出了本 發明一具體實施例可組態使得在源極區域3中的載子具有 與在没極區域4中_子不同之極性，因此若源極區域^ η型摻雜則汲極區域4為p型摻雜，反之亦然。如此，決定 了裝置的極性。因此’圖1所示之本發明具體實施 型穿隧場效電晶體’因為源極區域3係顯示為η型擦雜而没 極區域4鋪示為ρ型摻雜。在本範财，對應通道區域5 的通道抖體材料係組態以實質地具有—本 本發明具财施财也提供了職奈讀2之砰農^域= 電極。源極電極3’及祕電極4，分_合至源極區域3及淡 J區域4，汲極電極4,一般係顯示為圖i : 提供了職通道輯5關㈣極6，且聽=亦2 而安排以環狀地圍繞通道區域5的至小一加、了不木踝 v 一 分或全部。 在本發明一具體實施例中 更提供了至少一應變閘極 12 201236154 7 ,其係相對奈米線2而環狀地圍繞奈米線2之—區段之至 f一if。透過應變閘極7，—應變係施加至由奈米線區段 所圍繞之半導體材料。由圖I中可看出，在本發明-具體 實施例中’奈米線區段8對應通道區域5之-部分，其係實 質地鄰近源極區域3而設置。 、’、 在本發明-具體實施例中，應變閘極7可組態以施加一 二δ間?偏壓至奈•線區段8。如此，可幫麟應奈米線區 ^又之半導體材料的靜電摻雜’因為藉由選擇施加至應變間 極7之應變間極偏壓，對應奈米線區段8的半導體材料可由 極⑨的載子所摻雜。藉由應變的制至奈米線區段8及 ^電地摻雜與其對應的半導體，實質地鄰近源極區域3而設 的通道區域5(其為奈舞區段8所對應)係有效地 變成部分的源極區域3。 、由於在本發明具體實施例中的應變應用特徵，可幫助對 應源極區域3及通道區域5之能帶的帶對齊的變更。特別 地’藉由對奈錄區段8的應變躺，可改變(更佳為可降 其對應之半導體材料的能隙。此整體效應為，源極區 ==能隙她於通道_ 5之能_降低，其具有降低源 益，域^通道區域5之間之穿隧接面之轉高度的效應， 改义了在本發明"'具體實施财之載子橫越穿隧接面 效^她於先前提出的裝置）。在藉應變應用之源極 品讲的月b*隙降低之外(或與其無關），可改變橫越穿随接面 ^、子的穿，質1： ’其有助於載子橫越穿随接面之—改良的 隧速率4此而促成本發明具體實施例之—改良的穿隨效 率(相較於先前提出的裳置）。 13 201236154 體啻3用:徵’可修改在一特定應用中之本發明具 濟之雪轉φ 舉例來說’若需要增加的穿隧式場效電晶 :降低源極半導體材料的能隙寬度以及 導體材料助於增加的穿隧可能性。取決於源極半 以及其結晶方位的選擇’本發明一具體實施例可組 二*㈣應變或—壓縮應變來達到所需的效能。另一 穿隨式場效電晶體之轉消耗需要降低的情況。在此 、*，二況* ’本發明—频實施儀應變應用特徵係組態以 助於以相對較低之祕偏壓(相較於在先前提出的裝 置)來進行穿隧之帶對齊。 本發明具體實施例中，若應變閘極7執行應變應用及 1摻雜之雙重功能，應變係自對齊至接面轉。由於施加 至應變閘極7之由應變閘極7所施加的應變以及由電性偏壓 所引發的摻雜兩者係施加至相同區域(即奈米線區段8)，換 雜輪廟及應變輪廓為自對齊。這提供了以下伽：不需進行 更多製程步驟紐4摻雜輪廓及應變輪靡之間之任何不 ，齊’從可能引起職(其可麟低本發明具體實施例的效 能)的觀點，並不希望有這類的製程步驟。 在本發明一具體實施例中，應變閘極7係選擇以包含提 供一特定應變值至奈米線區段8的材料、以及以具有根據本 發明一具體實施例之一極性的一功函數值。就此而言，應變 閘極7係選擇以包含一金屬(例如TaN),其可藉由原子層沉 積(ALD)而共形地沉積。或者，應變閘極7可包含其他I化 物’例如氮化鈦(TiN)或氮化铪(HfN)。可用於應變閘極7的 其他材料包含碳或非晶碳，這些特定材料具有運用張力應變 的能力。若本發明具體實施例係無靜電摻雜特徵的參與而操 201236154 作’即應變閘極僅實施應變應用的功能至奈米線區段8，奈 米線2的摻雜已由其他摻雜方法(例如佈植或在奈米線2的 成長過程中)所實行’應變閘極7不需包含一導電材料。 應變閘極7係相對奈米線區段8而安排，如此而可實施 應變及靜電摻雜功能。就此而言，應變閘極7可安排以環狀 地圍繞奈米線區段8的至少一部分、或延伸以完全圍繞奈米 線區段8。應變閘極7可不需完全地連續或均勻的，其形式 可為圖案化或具有隨機不連續性。 在本發明一具體實施例中，可使用相同的半導體材料於 源極半導體材料、通辭導騎料、及錄半導體材料，例 如第四族元素或其二元化合物。可用於此情況中之半導體材 料的特定範例包含：碳、⑪、鍺、⑪錯(SixGei_x)、及石夕碳 (SixQ_x)。 在本發明另-具體實施例中，穿隨接面可自異質结構形 ίΓΙΐ極半導體材料不同於至少通道轉體材料，例如源 極半導體材料可選擇為包含以下之一：三五族化合 Ξ里、三元及四元化合物。用於本發明具體實施例 質、，構的-範例為：録化鎵(Gasb)供源極區域3，以及 =_nAS)或坤化銦鎵(InGaAS)供通道區域5/汲極區域 。可用於源極(1域3之材料的其他範例包、 InGaAs、銻化銦_及 GaSb。 AS lnAs 本發明-具體實施朗其簡徵包含 變閘極7形成於其上之 =地質形9成; 不未線2之外表面上。閘極介電層9可例如為二氧化石夕或二 15 201236154 氧化铪。然而，本發明之具體實施例並不限於這類材料的使 用5且事實上有助於個別載子侷限在至少源極區域3及通道 區域5中（其使得於其間所產生之穿隧接面的陡峭度增加)的 任何其他介電材料皆可選擇作為閘極介電質9。一般而言， 在本發明具體實施例中，閘極介電質9係選擇以包含具有相 對於真空在強度上大於4之介電常數的介電材料。如圖j所 示以及本發明一具體實施例係由垂直奈米線製程所實施的 情況下，可提供應變閘極間隙壁層1〇於應變閘極7之下， 亦即位於應變閘極7之下，此特徵提供了降低的寄生電容之 優點。在本發明一具體實施例中，為了電性地隔離閘極電極 6及應變閘極7，隔離層11係提供於其間。隔離層u可例 如，徑向或軸向提供。較理想為閘極電極6相對源極區域3 的設置係能夠致能閘極電極6耦合至源極區域3及通道區域 5之間的介面，亦即其不應實體地自此一介面移開多於數十 奈米，其基本上設定了隔離層U厚度的上限。在本發明一 具體實施例中，在應變閘極7底下之應變閘極間隙壁層 以及在應變閘極7及閘極電極6之間的隔離層丨丨不需要包 含相同的介電材料。事實上，在本發明一具體實施例中，針 對隔離層11沉積7至10奈米的氧化鋁(Al2〇3)。 現在參考圖2A及2B，其係示意地描述在本發明一且體 實施例中之能隙收縮及靜電摻雜的原理。在圖2A中，^變 閘極7並無組態以施加一應變閘極偏壓至奈米線區段/。可 從對應奈米線區段8之能帶圖區域看出，相較於通道區域5 的其他部分(例如閘極電極6呈現於其上處），對應奈米線區 段8之半導體材料的能隙係降低。如此，相較於先前提出的 裝置，在本發明一具體實施例中可改善橫越穿隧接面之 的穿随效率。 201236154 圖2B係示意地描述在本發明一具體實施例中的情境， 其中應變閘極7係組態以實施能隙收縮及靜電摻雜之雙功 能。能隙收縮的原理係參考圖2A描述於上。在圖2B中， 與圖2A所示情境相比，源極區域3係顯示為η型摻雜，其 係藉由在對應源極區域3之能帶圖區域中費米能階Ef移置 為較接近導帶Ec而較不接近價帶Ev。藉由經由應變閘極7 而應用一正應變閘極偏壓至奈米線區段％在應變應用之 外）’可完成源極區域3的η型摻雜。 現在參考圖3Α、3Β及3C ’其係繪示根據本發明一具 體實施例之在不同操作模式中的一 ρ型穿隧場效電晶體^ 其對應的能帶圖。在這些圖式中，由左向右延伸之能帶圖係 對應至根據本發明一具體實施例的「P_i_n」接面，如從底部 向上延伸。在此具體實施例中，應變閘極7係組態以實施經 由應變之能隙收縮以及經由靜電摻雜之源極摻雜的雙功能。 圖3A係繪示根據本發明一具體實施例之p型穿隧場效 電，體於—「關(°FF)」狀態，即實質地無請發生。在 此操作模式巾’沒有偏壓施加於應變_ 7及_電極6上 (即vstrain、vgs=〇)，且施加一逆向偏壓於上(即相對於 極電極3,施加負偏壓於汲㈣極4，上）。由 = =變，7上，根據本發明具體實施例之靜電 去Ί®3Α的能帶圖可看出，應奈米線區段8 體^料之雜寬度為降低，其仙較於例賴極電極6 =米線2的外表面上的情況及/或若無應變閘極 ^ S裝置中的情況）。根據本發明-具體實施例，在奈米 、’、二又8中之半導體材料的能隙寬度之改 ；： 調整經由應變閘極所施加之應變而完成。^籍由相應地 201236154 現在參考圖3B，其繪示根據本發明一具體實施例之除 了在p型穿隧場效電晶體中的應變應用外亦活化靜電摻雜 功能之一情境。在此操作模式中以及在此特定範例中，無施 加偏壓於閘極電極6上，施加負偏壓於Vds上以及施加正偏 壓至應變閘極7〇藉由正vstrain的應用，誘發負電荷於奈米 線區段8的内壁’且依此方式可實行^型摻雜於奈米線區段 8中。奈米線區段8的靜電η型摻雜係繪示於圖3Β的能帶 圖中，其中費米能階係移置以更接近導帶，其係在對應奈米 線區段8之能帶圖的部分<> 對奈米線區段8的應變應用係由 對應奈米線區段8之能帶的能帶寬度之降低所繪示’由於對 奈米線區段8之靜電摻雜及應變應用的雙重應用，此區域係 有效地變成源極區域3的一部分。由於在本範例中Vgs=〇， 無載子穿隧發生於穿隧接面之間（即自源極區域3(n摻雜)至 通道區域5)，因此穿隧式場效電晶體仍處於「關閉」模式。 即使穿隧式場效電晶體為「關閉」模式，仍可致能靜電摻雜。 然而，當在一關閉模式時，在本發明一具體實施例中較佳係 去能靜電摻雜功能，而可獲得增加通道長度的益處且可降低 漏電流Ι〇ρ·ρ·。 現在參考圖3C ’其繪示根據本發明一具體實施例之p 型穿隧場效電晶體於一「開啟(0N)」狀態，即在源極區域 3(n型摻雜)的導帶與通道區域5的價帶之間發生穿隧◊在此 操作模式及此特定範例中，Vstrain為正，Vgs為負，且一負偏 壓施加於Vdsl。針對Vstrain為正以及圖3B所示的情況，負 電荷係誘發於奈米線區段8的内壁上(應變閘極7係呈現於 其上），即促進奈米線區段8的靜電摻雜。負Vgs的應用係有 助於通道區域5中之價帶及源極區域3中之導帶的對齊，藉 此而造成載子於其間的穿隧。由於在源極區域3與通道區域 201236154 5之間的穿隧阻障高度係實質地降低(這是由對應源極區域3 之奈米線區段8中能隙寬度的降低所促成）’本發明具體實 施例中的穿隧效率與先前提出的裝置相比係有所改善。 現在參考圖4A至4D，其示意地繪示根據本發明一方法 態樣之一具體實施例的步驟。 參考圖4A，提供一基板，其係包含半導體材料、且係 摻雜以提供一歐姆接觸並供應載子供靜電摻雜。實質垂直對 齊的奈米線2储由在基板上的「纟τ往上加論哪)」成 長製程或「由上往下(t〇p-d〇wn)」蝕刻製程而製造於基板上^ 在形成奈料2讀，其可料本魏子濃度或可^有在轴 向延伸的摻雜輪廓，使得例如可提供—降低阻值的汲極電極 4’。 參考圖4B，閘極介電質9係共形地沉積於夺米線2 外表面上。應變閘極7接著形成於由在奈米線2之/至少一 段(上文巾稱作奈米_段8)上的_介電f 9所改變之 米線2的表面上。如前所述，形成應變閘極7，藉此而 :應奈米線區段8上’此應變為壓縮應變或為張力 篗。接者應變閘極7係蝕刻至所需的高度及/或圖案化。 了使應變閘極7能夠實施應變應用及靜電摻雜二。 較佳為包含傳導材料，像是例如TaN。雖然圖4 t本f明具體實施例係藉由一垂直奈米線2所實施的； 中，應變閘極間隙壁層10可沉積於應變閘極7 J 以提供降低的寄生電容之優點。 ’藉 如圖4C所示，-平面化層係沉積於應變閉極7上， 201236154 =以U發明具體貫施例之其他特徵的沉積。由圖4C可 出’在本發明具體實施例之一方法態樣的此特定範例中， 閘極電極6係沉積於奈米線2的外表面上，以環狀地圍繞通 道區域5之至少-部分，閘極電極6係設置於應變問極7之 上。雖然未繪示於圖4C中’包含介電材料的隔離層u係設 置於開極電極6與應變_7之間，藉此將其電性地隔離。 或者’閘極雜6可沉積以藉此重疊應賴極7，以避免問 極的未重4。閘極電極6接著係㈣j至所需高度且亦可圖案 化0 現在參考圖4D ’其綠示在閘極電極6上另一個平面化 層的形成’藉此以幫賴於本發明具體實關之其他特徵的 形成。在奈米線2延伸通過在提供閘極電極6之後形成於奈 米線2上的平面化層處，將閘極介電f 9自奈米線2的外表 面移除。若錄區域未摻雜，前接著完成進—步的步驟， 以摻雜對應錄區域4之奈米線2的區域。接著，藉由接觸 金屬的沉積及其圖案化可完成汲極電極4,之形成。在此特定 範例中，在本發明具體實施例之所有或大部分技術特徵已製 造後，汲極區域4的摻雜係實質地完成。然而，較佳地，汲 極區域4的摻雜在本發明之方法態樣之具體實施例的生產 線上係較早完成的，因為為了實施没極區域5的摻雜之在生 產線末端之針對啟動的相、對大的熱預算可能不是特別理想 的。 本發明一具體實施例以參考穿隧式場效電晶體而描述 於上。然而，这並非限制性，且可延伸至其他類型的場效電 晶體’像是例如金屬氧化物半導體場效電晶體以及碰撞游離 場效電晶體。 20 201236154 雖然本發明一具體實施例已參考實質垂直對齊的夺米 線2而描述’但本發明並不限於此，且奈米線2的任何^ 組態可視為包含於本發痛如。料，任何任意形狀的奈 米線係視為包含於本發明範疇内，例如圓形、六角形、三角 =、具有ΚΚ)奈米等級或更少之一直徑、且其在轴向上係實 質上長於(例如至少十倍長)徑向尺寸(例如奈米線的直徑）。 在本發明-具體實施例中，閘極電極6已形成於應變閉 L7二。^本發明並不限於此組態，且相反組態(即 ^變閘極7軸於閘㈣極6之上)魏為包含於本發明範 ^滿足以下條件:應變閘極7形成於奈米線2上以 衣狀地圍繞奈米線區段8，其對應鄰近源極區域3而設置之 通道區域5的部分。 通道考Γ區域之能帶相對於 限於此。在由於-特定應用而需要源極 目對於通道11域之能帶的增加及/或載子之穿隨 質里的增加之情況下’這可由本發明具體實關而促成。 明例的方式描述於上’且可做出在本發 在說月書中所揭露的每一特徵，合主 利乾圍及圖式可獨立地或以任何適當的組合而提供。月 【圖式簡單說明】 現在參考所嗎圖式，其僅作為範例，其中： 21 201236154 圖1係示意性地描述本發明一具體實施例； 圖2A及圖2B係示意地描述在本發明一具體實施例中 之能隙收縮及靜電摻雜的原理； 圖3A、圖3B、及圖3C係示意地描述根據不同操作模 式之本發明一具體實施例；以及 圖4A、圖4B、圖4C、及圖4D係示意地描述根據本發 明一方法態樣之一具體實施例。 【主要元件符號說明】 1 穿隧式場效電晶體 2 奈米線 3 源極區域 源極電極 4 >及極區域 4s 没極電極 5 通道區域 6 閘極電極 7 應變閘極 8 奈米線區段 9 閘極介電質 10 閘極間隙壁層 11 隔離層 22201236154, invention description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method of fabricating the same. [Prior Art] The wear-through field effect transistor (FET) can be used in a variety of applications, including high-speed switching and logic circuit 4 with the field effect transistor of the Wei surface. The reverse sub-critical slope of the wear-through field effect transistor is not Limited to the Pozien tail such as Fermi's statistics, the determined room temperature is 60mV/dec. Therefore, the tunneling field effect transistor can have a faster startup than the previously proposed device, that is, facilitate the conversion from "(ON)" (conducting state) to "off (〇FF)" (non-conducting state). The range of pressure is less than that of the device (4) previously proposed, and both the critical and operating voltages can be reduced without a corresponding deterioration in device performance. This makes the wearable electro-optical transistor particularly suitable for applications requiring low power consumption. Until recently, the scaling of the MOSFET size was sufficient to achieve the performance of the modified device. It is only recently that the money and its side-by-side system (10) become apparent and hinder further voltage ratio adjustment. Therefore, devices with phase MOSFETs with relatively reduced power consumption have been studied, and in this respect, tunneling field effect transistors have become a highly desirable problem associated with germanium-based tunneling field effect transistors. The reduced carrier-to-band tunneling efficiency caused by the large 矽 energy gap, the relatively low "on" current of such a device, that is, when placed in a = state. This can cause an increase in delay, for example, on one of the age logic operations (its f start current). The opening of n 201236154 ^ Know the strain application of the semiconductor may affect its _ width and / or wear quality. It has been pointed out that the strain response on the nanowire can affect the energy band structure of the body. The nanowire is made to a finer A than the base of the semiconductor device forming slope device and/or structure. In this regard, Sajjad et al., published in 2009 by the journal of AppUed physies, pp. 1, 540, 307, reported that the energy gap in the Jane line is obtained from both applied tension and Wei stress. Nano _ is large and low, and the equivalent quality of electricity is also reduced by such actions. The scope of general research on response/variation effects based on the three-five family is less than, for example, based on the 矽 system. In this regard, it has been shown that Shenhua Marriage (GaA__width is about 100-200 mV under the actual available value of 2.3%.) For tunneling field effect transistors, it is known that the belt-to-band tunneling efficiency can be borrowed. It is improved by reducing the energy gap of the semiconductor material system on which the tunneling field effect transistor is based. However, if this is the whole structure of the tunneling field effect transistor (ie, the source of the tunneling field effect transistor, 汲The implementation of the pole and the gate is performed, which may result in an increased leakage current (1〇1?1〇, which may, for example, affect the switching of the tunneling field effect transistor from a conduction-on state to a non-conduction-off state. (and vice versa) reliability and controllability make it unpopular in high-speed switching applications. In particular, since the main application areas of tunneling field-effect transistors are considered to reduce power consumption, A leakage current will unfavorably increase the overall power consumption, thus offsetting the potential potential of the tunneling field effect transistor. In order to improve the band-to-band tunneling efficiency, a tunneling field effect transistor based on a heterogeneous material system has been proposed. 'borrow This source is replaced by a semiconductor having a smaller energy gap than that of Shi Xi. In this regard, reference is made to Verhulst et al. in IEEE Electron Device Letters, 2008, Vol. 29, pp. 1-4, with points 201236154 = Unveiled a heterostructure-based n-type interferometric field-effect transistor and a p-type intervening field-effect transistor based on the nanowire. The improved wear-through efficiency for n-type follow-up TFETs, ^rliulst et al.; The energy band discontinuity of the source channel junction should be at the valence band 9 by using, for example, a sigma-doped TFET towel using SiGe as the semiconductor material for the source and making it clear to the channel. Ground, for the P-type tunneling TEET 'the pure band gap in the junction of the secret channel should be in the conduction band money good tunneling efficiency, which is produced by, for example, the indium-based indium (InGaAs) source Obtained on the channel of Shi Xi. Although the wear-through field-effect transistor fabricated from the heterostructure is theoretically advantageous in terms of band alignment, lattice mismatch between different materials constituting the heterostructure may cause defects. Formed in its interface. If the interface is located in tunneling (ie, near the source channel interface), the tunneling efficiency may be degraded because the carrier is likely to participate in defect-assisted tunneling rather than direct band-to-band tunneling. In the previously proposed device, the tunneling junction is used. Impurity doping is used. In this case, the technical challenge is to make the tunneling junction as steep as possible. This condition is helpful for the tunneling of the carrier across the tunnel junction. This may be facilitated. One of the challenges is that the heat treatment generally used for impurity doping may tend to "smear out" the tunneling junction across the carrier tunneling, because the heat treatment is the diffusion broadening and process of the doped region. Incompatibility. For example, in the case of a tunneling field effect system based on a vertical nanowire process, another challenge encountered is to create a steep tunneling junction at the base of the nanowire. Furthermore, in some materials, chemical doping of two polarities can be challenging, for example due to the difficulty associated with the incorporation of atoms into a desired doping during growth. Reference is now made to Lee et al., 2004, in Applied Physics Letters, 201236154 145. 147 Stomach, which reports that electrostatic doping can alleviate some of the disadvantages associated with miscellaneous's _ is about materials with relatively narrow temperature vessels such as three It is challenging to have a cap of one or two polar activated dopants compared to the 矽 = case, and the cap is made up of heterogeneous and/or other previous formulas. Regarding the implementation of electrostatic switching, the device is a MOSFET. It is not taught that the use of electrostatic doping along with field-effect transistors is a vertical process and/or device, such as, for example, a vertical nanowire tunneling field effect transistor. SUMMARY OF THE INVENTION According to one embodiment of the first aspect of the present invention, a semiconductor is provided that includes: at least a nanowire, configured to include: at least a source including a corresponding source semiconductor material a region, at least one drain region corresponding to the semiconductor material, and at least one channel region including a corresponding channel semiconductor material, the channel region being arranged between the source region and the drain region; at least one gate electrode 'relatively a nanowire arranged to surround at least a portion of the channel region in an annular shape; and at least one strain gate arranged to annularly surround at least a portion of the m segment of the nanowire with respect to the nanowire, the strain hybrid configuration A strain is applied to the nanowire segment, thereby promoting at least one change in the energy band of the corresponding source region relative to the corresponding channel region. Due to the strain application characteristics in a particular embodiment of the invention, a change in the energy band of the corresponding source region relative to the energy band of the corresponding channel region can be promoted. In particular, the energy gap of the semiconductor material corresponding thereto can be adjusted (more preferably reduced) by strain application to the nanowire segment. This has the effect of changing the band alignment of the energy band of the corresponding source region and the energy band of the corresponding channel region. Preferably, the band alignment between the source region and the energy band of the channel region is changed such that the energy band of the source region The energy gap of the relative channel area 201236154 domain is reduced. In this way, the barrier of the tunneling junction between the source region and the channel region can be reduced, thereby improving the tunneling effect of the carrier across the splicing surface in a specific embodiment of the present invention. s installation). In addition to (or not related to) the energy gap of the source region, the amount of wear across the traversing surface can be varied, which helps the carrier to traverse the compliant surface. An improved rate of demand, thereby facilitating the specific side of the invention - improved tunneling efficiency (compared to previously proposed devices). The change in the tunneling quality of the carrier can be facilitated by varying the curvature of the energy band of the corresponding source region relative to the curvature of the energy band of the corresponding channel region. The father's madness*' strain gate is configurable to apply a one-meter section, thereby promoting electrostatic doping of the nanowire section. This == , the embodiment can be configured to be applied via a strain gate - the strain gate bias is biased by a suitable selected strain gate, corresponding to the nanowire region t + v bulk material can be carried by a carrier of the desired polarity Doping, this can be electrostatic doping of the non-rice section. The advantage of the related electrostatic doping is that the doping can be achieved without any monthly, :=:=: another advantage of the virtual electrostatic doping is that ==(10) has "smear (-)" wear__ = widening to an undesired feature, as it may cause a load to be connected to the joint ==::=5= body material system (such as, for example, a tri-five a-material semiconductor; = for some semi-conductors: relatively important The design and / or process is excellent; because:) three can be integrated - or two kinds of impurity doping compared to the "love 8 201236154; by the conventional doping method to achieve enough - polarity The system may be challenging, and the material system has a very configurable line segment to implement the nanowires. The nanowires are essentially vertically aligned. Because the strain gates are available with universal strain and static electricity. The dual function of doping, the present hair = (set = when the vertical alignment of the nanowire is implemented) compared to = the original pure can be achieved more. In addition, because the extension of the line in the nano-direction can be reduced Regarding the problem of spatial limitations, certain sizes and/or structures associated with embodiments of the present invention may be aligned by vertical alignment (rather than planar configuration) by In the case where the specific embodiment of the present invention is implemented by a vertical nanowire, it is preferable that the simple gap is formed in the (four) pole to provide a reduced parasitic capacitance. Preferably, at least one gate dielectric is conformally provided on the outer surface of the nanowire, facilitating the individual carriers to be confined to at least the source region and the channel region (so that it is generated from the paH surface) The dielectric material of (four) degrees can be selected as the gate dielectric. This condition can generally be satisfied by a dielectric material having a dielectric constant greater than 4 with respect to vacuum. For example, in one embodiment of the invention, the strain gate comprises a gold 201236154 genus. In an embodiment of the invention, the strain gate is used to electrostatically In the case of doping the semiconductor material corresponding to the nanowire segment (which is done by applying a strain gate bias to the strain gate), in addition to applying strain to the nanowire segment, the strain gate is selected to Contains conductive materials such as, for example, metal In this regard, in one embodiment of the invention, a nitrided group (TaN) can be used as the strain gate material. Preferably, an isolation layer is provided between the gate electrode and the strain gate. The gate electrode and the strain gate are isolated, and may comprise, for example, a dielectric material. Thus, electrical shorting of the gate electrode and the strain gate can be avoided, and the reliability of operation of an embodiment of the present invention can be improved. In one embodiment of the invention, the source semiconductor material, the drain semiconductor material, and the channel semiconductor material are the same. This feature provides the advantage of reducing manufacturing complexity without potential defects in the nanometer corresponding to these materials. The interface between the different regions of the line. In this regard, the source semiconductor material, the drain semiconductor material, and the channel semiconductor material may be selected to comprise the following 'Group IV elements and their diterpene compounds. Alternatively, in one embodiment of the invention, the source semiconductor material is different from the at least channel semiconductor material. In this case, there may be a defect associated with lattice mismatch between the source semiconductor material and the channel semiconductor material at the source region/channel region interface. However, the disadvantages associated therewith (especially the deterioration of tunneling efficiency) can be at least partially offset by the strain application characteristics of embodiments of the present invention. In this case, the source semiconductor material is selected to comprise one of the following: a Group III material system, and binary, ternary, and quaternary compounds thereof. Alternatively, the 'source semiconductor material may, for example, comprise a Group 4 bis compound' such as SiGe. Preferably, a specific embodiment of the invention comprises one of the following: a tunneling effect transistor, a metal oxide semiconductor field effect transistor, and a collision free field effect transistor. The advantages of an embodiment of the invention (i.e., contributing to a reduction in the energy gap of the semiconductor material corresponding to the nanowire segment and/or a decrease in the tunneling quality of the carrier) may be beneficial: for metal in the nanowire Source injection rate in an oxide semiconductor field effect transistor (MOSFET); tunneling efficiency in a tunneling field effect transistor and collision free speed in a collision free field effect transistor. A corresponding method aspect is also provided. Therefore, in accordance with an embodiment of the second aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the steps of: providing at least one nanowire, the group of which is provided The method includes: at least one source region including a corresponding source semiconductor material, at least one drain region including a corresponding semiconductor material, and at least one channel region including a corresponding channel semiconductor material. Between the source region and the drain region; forming at least one gate electrode arranged to annularly surround at least a portion of the channel region with respect to the nanowire; forming at least one strain gate opposite to the nanowire Arranging at least two portions of a segment of the nanowire in a ring shape, and configuring a strain gate to apply a strain to the nanowire segment, thereby promoting an energy band of the corresponding source region relative to the corresponding channel The ability of the area ^ $ one less change. Any device feature can be applied to the method aspect of the invention, and vice versa. An aspect of the present invention can be applied to another aspect of the present invention. It is also possible that any of the specific embodiments disclosed may be combined with one or more of the other embodiments shown and/or described. [Embodiment] 201236154 In the description, the same component symbols or symbols are used to indicate the same components or the like. Referring now to Figure 1, a specific embodiment of a device aspect in accordance with the present invention is schematically depicted. As can be seen in Figure 1, the embodiment of the present invention comprises a tunneling field effect transistor 1 which can be implemented by a nanowire 2. In this particular example of a particular embodiment of the invention, the nanowires 2 are substantially vertically aligned and grown/remained by a bulk semiconductor substrate. The nanowire 2 is configured to have at least three different regions: at least one source region 3 including a corresponding source semiconductor material, at least one drain region 4 including a corresponding drain semiconductor material, and a corresponding one At least one channel region 5 of the channel semiconductor material (which is disposed between the source region 3 and the drain region 4). It can be seen from the figure that an embodiment of the present invention can be configured such that the carrier in the source region 3 has a different polarity from the neutron in the non-polar region 4, so if the source region is n-type doped Then the drain region 4 is p-type doped and vice versa. Thus, the polarity of the device is determined. Thus, the tunneling field effect transistor of the present invention shown in Fig. 1 is shown in the source region 3 as an n-type erase and the non-polar region 4 as a p-type doping. In the present model, the channel vibrating material corresponding to the channel region 5 is configured to have substantially the same - the present invention provides a financial operation and also provides the electrode of the field. The source electrode 3' and the secret electrode 4 are divided into a source region 3 and a light J region 4, and a drain electrode 4, which is generally shown as a figure i: provides a channel channel 5 (four) pole 6, and listens = Also, it is arranged to surround the passage area 5 in a ring shape to a small one or a whole or a whole. In one embodiment of the invention there is further provided at least one strain gate 12 201236154 7 which is annularly surrounding the nanowire 2 to the section f to if relative to the nanowire 2 . Through the strain gate 7, a strain system is applied to the semiconductor material surrounded by the nanowire segment. As can be seen in Figure 1, in the present invention - the specific embodiment of the nanowire section 8 corresponds to the portion of the channel region 5 which is disposed substantially adjacent to the source region 3. In the present invention-specific embodiment, the strain gate 7 is configurable to apply a two delta-to-negative bias to the nanowire section 8. Thus, the electrostatic doping of the semiconductor material of the lining nanowire region can be assisted because the semiconductor material corresponding to the nanowire segment 8 can be made up of the pole 9 by selecting the strain-to-electrode bias applied to the strained interpole 7 The carrier is doped. By straining the nanowire section 8 and electrically doping the semiconductor corresponding thereto, the channel region 5 (which corresponds to the Neibu segment 8) disposed substantially adjacent to the source region 3 is effectively It becomes part of the source area 3. The alignment of the energy bands of the source region 3 and the channel region 5 can be assisted by the strain application features in the specific embodiment of the present invention. In particular, it can be changed by the strain lying on the Neibu section 8 (more preferably, the energy gap of the corresponding semiconductor material can be lowered. The overall effect is that the source region == energy gap is in the channel _ 5 Energy-reducing, which has the effect of reducing the source and benefit, and the transition height of the tunneling junction between the domains and the channel region 5, and is modified in the present invention. ^ She was previously proposed device). In addition to (or not related to) the monthly b* gap of the source of the strain application, the traversing of the splicing surface can be changed, and the quality is 1: 'It helps the carrier to traverse The junction-modified tunneling rate 4 thus contributes to the improved embodiment of the invention - improved wear efficiency (compared to previously proposed skirting). 13 201236154 啻 3: Use 'can modify the snow of the invention in a specific application φ For example, 'If you need to increase the tunneling field effect transistor: reduce the gap width of the source semiconductor material and Conductor materials contribute to increased tunneling possibilities. Depending on the choice of source half and its crystal orientation, a particular embodiment of the invention may combine two (4) strains or - compressive strains to achieve the desired performance. The consumption of another wear-through field effect transistor needs to be reduced. Here, the *, the second condition * the present invention is configured to assist in the alignment of the tunnel with a relatively low bias (compared to the previously proposed device). In a specific embodiment of the invention, if the strain gate 7 performs the dual function of strain application and 1 doping, the strain system is self-aligned to the junction. Since both the strain applied by the strain gate 7 applied to the strain gate 7 and the doping caused by the electrical bias are applied to the same region (ie, the nanowire segment 8), The strain profile is self aligned. This provides the following gamma: no need to perform more process steps, the New 4 doping profile and any differences between the strain rims, from the point of view that may cause the job, which can lower the performance of the specific embodiment of the invention, It is not desirable to have such a process step. In one embodiment of the invention, the strain gate 7 is selected to include a material that provides a particular strain value to the nanowire segment 8, and a work function value having a polarity in accordance with one embodiment of the present invention. . In this regard, the strain gate 7 is selected to contain a metal (e.g., TaN) that can be conformally deposited by atomic layer deposition (ALD). Alternatively, the strain gate 7 may contain other I compounds such as titanium nitride (TiN) or tantalum nitride (HfN). Other materials that can be used for strain gate 7 include carbon or amorphous carbon, which have the ability to apply tensile strain. If the embodiment of the present invention is involved in the non-electrostatic doping feature, 201236154 is used as the 'strain gate only performs the function of the strain application to the nanowire segment 8, and the doping of the nanowire 2 has been performed by other doping methods. The strain gate 7 does not need to contain a conductive material (for example, implanted or during the growth of the nanowire 2). The strain gate 7 is arranged relative to the nanowire section 8, so that strain and electrostatic doping can be performed. In this regard, the strain gate 7 can be arranged to annularly surround at least a portion of the nanowire section 8, or extend to completely surround the nanowire section 8. The strain gate 7 may not need to be completely continuous or uniform, and may be in the form of patterning or having random discontinuities. In one embodiment of the invention, the same semiconductor material can be used for the source semiconductor material, the singular conductor, and the semiconductor material, such as a Group IV element or a binary compound thereof. Specific examples of semiconductor materials that can be used in this context include: carbon, 11, ruthenium, eleven (SixGei_x), and Shixi carbon (SixQ_x). In another embodiment of the present invention, the wear-and-match surface may be different from the at least channel-transferring material from the hetero-structured semiconductor material, for example, the source semiconductor material may be selected to include one of the following: , ternary and quaternary compounds. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The examples for the present invention are: recording gallium (Gasb for source region 3, and =_nAS) or kinking indium gallium (InGaAS) for channel region 5/drain region. Other example packages that can be used for the source (material of domain 1), InGaAs, indium antimonide _ and GaSb. AS lnAs The present invention - the specific implementation of the singularity includes the formation of the variator 7 on the geological shape The surface of the gate dielectric layer 9 may be, for example, a dioxide dioxide or a bismuth 15 201236154 yttrium oxide. However, embodiments of the invention are not limited to the use of such materials 5 and in fact Any other dielectric material that facilitates the confinement of individual carriers to at least source region 3 and channel region 5 (which increases the steepness of the tunneling junction created therebetween) may be selected as the gate dielectric 9. In general, in a particular embodiment of the invention, the gate dielectric 9 is selected to comprise a dielectric material having a dielectric constant greater than 4 in strength with respect to vacuum. As shown in Figure j and the present invention In a particular embodiment, which is implemented by a vertical nanowire process, a strained gate spacer layer 1 can be provided below the strained gate 7, i.e., below the strained gate 7, which provides a reduction in this feature. Advantage of parasitic capacitance. In a specific embodiment of the invention In order to electrically isolate the gate electrode 6 and the strain gate 7, an isolation layer 11 is provided therebetween. The isolation layer u can be provided, for example, radially or axially. Ideally, the gate electrode 6 is disposed relative to the source region 3. Is capable of enabling the gate electrode 6 to be coupled to the interface between the source region 3 and the channel region 5, that is, it should not physically remove more than tens of nanometers from the interface, which essentially sets the isolation layer The upper limit of the U thickness. In one embodiment of the invention, the strain gate spacer layer under the strain gate 7 and the isolation layer between the strain gate 7 and the gate electrode 6 do not need to contain the same Dielectric material. In fact, in one embodiment of the invention, 7 to 10 nanometers of alumina (Al2〇3) is deposited for the isolation layer 11. Reference is now made to Figures 2A and 2B, which are schematically depicted in the present invention. The principle of energy gap shrinkage and electrostatic doping in the body embodiment. In Figure 2A, the gate 7 is not configured to apply a strain gate bias to the nanowire segment /. The band diagram area of the nanowire segment 8 is seen as compared to other parts of the channel region 5 (eg The gate electrode 6 is present thereon, and the energy gap of the semiconductor material corresponding to the nanowire segment 8 is reduced. Thus, in a particular embodiment of the invention, the cross-over can be improved compared to the previously proposed device. Pass-through efficiency of the tunneling plane 201236154 Figure 2B is a schematic illustration of a scenario in an embodiment of the invention in which the strain gate 7 is configured to perform dual functions of energy gap shrinkage and electrostatic doping. The principle of shrinkage is described above with reference to Figure 2A. In Figure 2B, source region 3 is shown as n-type doping compared to the situation shown in Figure 2A, which is based on the energy band in the corresponding source region 3. In the map region, the Fermi level Ef is displaced closer to the conduction band Ec than to the valence band Ev. By applying a positive strain gate bias to the nanowire segment % through the strain gate 7 in strain application The n-type doping of the source region 3 can be completed. Referring now to Figures 3A, 3B and 3C', there is shown a corresponding energy band diagram of a p-type tunneling field effect transistor in different modes of operation in accordance with an embodiment of the present invention. In these figures, the energy band diagram extending from left to right corresponds to a "P_i_n" junction in accordance with an embodiment of the present invention, such as extending upward from the bottom. In this particular embodiment, the strained gate 7 is configured to perform a dual function of strained energy gap shrinkage and source doping via electrostatic doping. FIG. 3A illustrates a p-type tunneling field effect according to an embodiment of the present invention, in a state of "off (°FF)", that is, substantially no occurrence occurs. In this mode of operation, no bias is applied to the strain_7 and_electrode 6 (i.e., vstrain, vgs = 〇), and a reverse bias is applied thereto (i.e., a negative bias is applied to the pole electrode 3). (4) Extreme 4, top). From == to 7, on the energy band diagram of the electrostatic deuterium®3Α according to the embodiment of the present invention, it can be seen that the width of the body of the nanowire segment 8 is reduced, and the ratio is lower than that of the case. The pole electrode 6 = the condition on the outer surface of the rice noodle 2 and/or if there is no strain gate device. In accordance with the present invention, the change in the energy gap width of the semiconductor material in nanometers, ', 2 and 8 is accomplished by adjusting the strain applied via the strained gate. Referring now to Figure 3B, there is illustrated a scenario in which an electrostatic doping function is activated in addition to strain application in a p-type tunneling field effect transistor in accordance with an embodiment of the present invention. In this mode of operation and in this particular example, no bias is applied to the gate electrode 6, a negative bias is applied to Vds and a positive bias is applied to the strain gate 7 诱发 induced negative by the application of positive vstrain The charge is on the inner wall ' of the nanowire section 8 and in this way can be doped in the nanowire section 8. The electrostatic n-type doping of the nanowire segment 8 is illustrated in the energy band diagram of FIG. 3, in which the Fermi energy system is displaced closer to the conduction band, which is in the corresponding nanowire segment 8 The portion with the map <> The strain application to the nanowire segment 8 is shown by the decrease in the energy band width of the energy band corresponding to the nanowire segment 8 'due to the static electricity to the nanowire segment 8 For dual applications of doping and strain applications, this region effectively becomes part of the source region 3. Since Vgs=〇 in this example, no carrier tunneling occurs between the tunnel junctions (ie, from the source region 3 (n-doping) to the channel region 5), so the tunneling field effect transistor is still " Close mode. Even if the tunneling field effect transistor is in the "off" mode, electrostatic doping can still be achieved. However, when in an off mode, in an embodiment of the invention, the electrostatic doping function is preferably removed, and the benefit of increasing the channel length can be obtained and the leakage current Ι〇ρ·ρ· can be reduced. Referring now to FIG. 3C', a p-type tunneling field effect transistor in an "on (0N)" state, that is, a conduction band in a source region 3 (n-type doping), is illustrated in accordance with an embodiment of the present invention. Tunneling occurs between the valence bands of channel region 5. In this mode of operation and in this particular example, Vstrain is positive, Vgs is negative, and a negative bias is applied to Vdsl. For the case where Vstrain is positive and as shown in Fig. 3B, a negative charge is induced on the inner wall of the nanowire section 8 (on which the strain gate 7 is present), i.e., promotes electrostatic doping of the nanowire section 8. . The application of the negative Vgs assists in the alignment of the valence band in the channel region 5 and the conduction band in the source region 3, thereby causing tunneling of the carrier therebetween. Since the tunneling barrier height between the source region 3 and the channel region 201236154 5 is substantially reduced (this is caused by a decrease in the energy gap width in the nanowire segment 8 corresponding to the source region 3) The tunneling efficiency in the specific embodiments of the invention is improved compared to previously proposed devices. Referring now to Figures 4A through 4D, there are schematically illustrated steps in accordance with one embodiment of a method aspect of the present invention. Referring to Figure 4A, a substrate is provided that is comprised of a semiconductor material and is doped to provide an ohmic contact and to supply a carrier for electrostatic doping. The substantially vertically aligned nanowire 2 is fabricated on the substrate by a "g" on the substrate" growth process or a "up to down (t〇pd〇wn)" etching process. In the second reading, it is possible that the concentration of the present ferrite or the doping profile extending in the axial direction makes it possible, for example, to provide a drain electrode 4' with a reduced resistance. Referring to FIG. 4B, a gate dielectric 9 is conformally deposited on the outer surface of the rice striker 2. The strain gate 7 is then formed on the surface of the rice line 2 which is changed by the dielectric -9 on the at least one of the nanowires 2 (the above is referred to as the nano-segment 8). As described above, the strain gate 7 is formed, whereby the strain on the nanowire section 8 is a compressive strain or a tension 篗. The strainer gate 7 is etched to the desired height and/or pattern. The strain gate 7 is capable of performing strain application and electrostatic doping. It preferably contains a conductive material such as, for example, TaN. Although the embodiment of the present invention is implemented by a vertical nanowire 2, the strain gate spacer layer 10 can be deposited on the strain gate 7 J to provide the advantage of reduced parasitic capacitance. As shown in Fig. 4C, a planarization layer is deposited on the strained closed pole 7, 201236154 = deposition of other features of the specific embodiment by U invention. 4C, in this particular example of a method aspect of one embodiment of the present invention, a gate electrode 6 is deposited on the outer surface of the nanowire 2 to annularly surround at least the channel region 5 - In part, the gate electrode 6 is disposed above the strained pole 7. Although not shown in Fig. 4C, the spacer layer u containing the dielectric material is disposed between the open electrode 6 and the strain_7, thereby electrically isolating it. Alternatively, the gate impurity 6 can be deposited to thereby overlap the poles 7 to avoid the unweighted 4 of the pole. The gate electrode 6 is then tied to the desired height and can also be patterned. Referring now to Figure 4D, 'green shows the formation of another planarization layer on the gate electrode 6' to assist in the specific implementation of the present invention. The formation of other features. The gate dielectric di 9 is removed from the outer surface of the nanowire 2 at the nanowire 2 extending through a planarization layer formed on the nanowire 2 after the gate electrode 6 is provided. If the recorded area is undoped, the next step is followed by doping to the area of the nanowire 2 corresponding to the recorded area 4. Next, the formation of the gate electrode 4 can be completed by deposition of the contact metal and its patterning. In this particular example, the doping of the drain region 4 is substantially completed after all or most of the technical features of the embodiments of the present invention have been fabricated. Preferably, however, the doping of the drain region 4 is performed earlier on the production line of the embodiment of the method aspect of the invention, since the doping at the end of the line is performed in order to carry out the doping of the gate region 5 The phase, the big thermal budget may not be particularly ideal. One embodiment of the invention is described above with reference to a tunneling field effect transistor. However, this is not limiting and can be extended to other types of field effect transistors such as, for example, metal oxide semiconductor field effect transistors and collision free field effect transistors. 20 201236154 Although an embodiment of the invention has been described with reference to substantially vertically aligned rice taper 2, the invention is not limited thereto, and any configuration of the nanowire 2 can be considered to be included in the present invention. Any nanowire of any shape is considered to be included in the scope of the present invention, such as a circle, a hexagon, a triangle =, a diameter of one or less, and a diameter in the axial direction. The upper is longer (eg, at least ten times longer) radial dimension (eg, the diameter of the nanowire). In the present invention - the specific embodiment, the gate electrode 6 has been formed in strain closed L7. The present invention is not limited to this configuration, and the opposite configuration (ie, the gate 7 axis is above the gate (four) pole 6) is included in the present invention: the strain gate 7 is formed in the nanometer. Line 2 surrounds the nanowire section 8 in a garment-like manner, which corresponds to the portion of the channel region 5 which is disposed adjacent to the source region 3. The energy band of the channel test area is relatively limited to this. In the case where an increase in the energy band of the channel 11 domain and/or an increase in carrier wear is required due to the application-specific application, this can be facilitated by the specific implementation of the present invention. The manner of the example is described above and each of the features disclosed in the present disclosure may be made, and the main components and drawings may be provided independently or in any suitable combination. BRIEF DESCRIPTION OF THE DRAWINGS [0009] Reference is now made to the drawings, which are merely by way of example, in which: FIG. 1 is a schematic depiction of one embodiment of the invention; FIG. 2A and FIG. The principle of energy gap shrinkage and electrostatic doping in a specific embodiment; FIGS. 3A, 3B, and 3C schematically depict an embodiment of the present invention according to different modes of operation; and FIGS. 4A, 4B, 4C, And Figure 4D schematically depicts a specific embodiment of a method aspect in accordance with the present invention. [Main component symbol description] 1 tunneling field effect transistor 2 nanowire 3 source region source electrode 4 > and polar region 4s electrodeless electrode 5 channel region 6 gate electrode 7 strain gate 8 nanowire region Section 9 Gate Dielectric 10 Gate Gap Layer 11 Isolation Layer 22

Claims (1)

201236154 七、申請專利範圍： 1. 一種半導體裝置，包含： 至少一奈米線，組態以包含·· 體材料之至少-源極區域、含 極丰導 之至少一v ^ 對應汲極半導體材料 區域、以及3—對應通道半 至少-通道區域，該通道區域俘體材料之 該汲極區域之間； _女排於該源極區域與 至少-間極電極’相對該奈米線而安排以環狀地 園繞該通道區域之至少一部分；以及 靜變閘極，相對該奈米線而安排以環狀地 组：::：二之Τ區段之至少—部分，該應變閘極係 辞:极W 一應變至該奈米線區段，藉此而促進對應 該源極區域之能帶相對於對應該通道區域之能帶的 至少一改變。 • 明求項1所述之半導體裝置，其中該應變閘極 係可組態以施加一應變閘極偏壓至該奈米區段，藉此 促進該奈米區段的靜電摻雜。 3.如请求項1或2所述之半導體裝置，其中該應變 閘極包含一材料，該材料係選擇以提供一特定應變值 至該奈米區段且具有根據該半導體裝置之一極性的 一功函數值。 4· /如請求項1或2所述之半導體裝置，其中該奈米 線係實質地垂直對齊；或者 23 201236154 其中 之下 應變閘極間隙壁層係提供於該應變閘極 5:如請求項i或2所述之半導體， 質係共形地提供於該奈米線之、一“面 上，或者 ㈣極介電質包含一介電質材料，該介電質 =/、有相較於一真空在強度上高於4之一介電常 :=或】;述之半導體裝置，其中該應變 極之間、r或：緣層係提供於該閘極電極及該應變閘 及兮半導體材料、該汲極半導體材料、以 及該通道半導體材料係相同；或者 及兮極半導體材料、該汲極半導體材料、以 材料包含以下之'·-第四族元素及 i導所述之半導^置，其中該源極 +導體材枓係不同於至少該通道半導體材料·或者 # ί I ^ 1元化合物一谢物、一三元化合物、及 24 201236154 8. 如請求項1或2所述之半導體裝置，其中該半導 體裝置包含以下之一：一穿隧式場效電晶體、一金屬 氧化物半導體場效電晶體、及一碰撞游離場效電晶 體。 y· 一種用以製造一半導體裝置之方法，包含以下步 驟： 提供至少一奈米線，組態以包含：含一對應源極 半導體材料之至少一源極區域、含一對應汲極半導體 材料之至少一汲極區域、以及含一對應通道半導體材 料之至少一通道區域，該通道區域係安排於該源極區 域與該汲極區域之間； 形成至少一閘極電極，該閘極電極係相對該奈米 線而安排以環狀地圍繞該通道區域之至少一部分； 形成至少一應變閘極，該至少一應變閘極係相對 該奈米線而安排以環狀地圍繞該奈米線之一區段 至少一部分；以及 組態該應變閘極以施加一應變至該奈米線區 段，藉此而促進對應該源極區域之能帶相對於/對應; 通道區域之能帶的至少一改變。 一乂 10·如請求項9所述之方法，更包含以下步驟：㈣ 該應變閘極以施加-應㈣極偏壓至該奈米區段^ 此促進該奈米區段的靜電摻雜。 9 11.如請求項9或10所述之方法甘士 &lt;万法其中該應變閘極 25 201236154 係選擇以包含一材料，該材料係選擇以提供一特定應 變值至該奈米區段且具有根據該半導體裝置之一極 性的一功函數值。 12.如請求項9或10所述之方法，其中在提供該奈 米線之該步驟中，該奈米線係實質地垂直對齊；或者 更包含提供一應變閘極間隙壁層於該應變閘極 之下的一步驟。 13。如請求項9或1〇所述之方法，更包含共形地提 供至少一閘極介電質於該奈米線之一外表面上之一 步驟；或者 广/其中在提供該閘極介電質之步驟中，該閘極介電 質係選擇以包含—介電質材料，該介電質材料具有相 較於一真空在強度上高於4之一介電常數。、有相 14.如請求項9或10所述之方法，其中該應變閘極 包含一金屬；或者 更包含提供一絕緣層於該閘極電極及該應變 極之間的一步驟；或者 其中在提供該奈米線之該步驟中，該源極半導體 ^料、該汲極半導體材料、以及該通道半導體材料係 選擇為相同；或者 、 、其中該源極半導體材料、該汲極半導體材料、以 及該通道半導體材料係選擇以包含以下之一：一 族元素及其一二元化合物。 7 26 2U1236I54 1：).如請求項9或1〇 轉之步驟中，該源極半導其中在提供該奈 少該通道半導體材料；= 體材料係選擇為不同於至 其中該源極半導體材料係選擇為包含以下之 。 二五族材料系統、以及其一二元化合物、一三 元化合物、及一四元化合物。 27201236154 VII. Patent application scope: 1. A semiconductor device comprising: at least one nanowire, configured to include at least a source region of at least one source region, at least one v ^ corresponding to a drain semiconductor material a region, and a third-corresponding channel, at least a channel region, between the drain regions of the capture material; the female row is arranged in the source region and the at least-interelectrode electrode is aligned with the nanowire Forming at least a portion of the channel region; and a static gate, arranged in an annular group with respect to the nanowire:::: at least a portion of the second segment, the strain gate terminology: The pole W is strained to the nanowire segment, thereby promoting at least one change in the energy band corresponding to the source region relative to the energy band corresponding to the channel region. The semiconductor device of claim 1, wherein the strain gate is configurable to apply a strain gate bias to the nanosection, thereby promoting electrostatic doping of the nanosection. 3. The semiconductor device of claim 1 or 2, wherein the strain gate comprises a material selected to provide a specific strain value to the nano-section and having a polarity according to one of the semiconductor devices Work function value. The semiconductor device of claim 1 or 2, wherein the nanowire system is substantially vertically aligned; or 23 201236154 wherein a strain gate spacer layer is provided to the strain gate 5: as requested The semiconductor of the above, wherein the quality is conformally provided on a "face" of the nanowire, or the (tetra) dielectric comprises a dielectric material, the dielectric = /, compared to A vacuum is higher than 4 in a dielectric constant: = or a semiconductor device, wherein the strain between the r, r: edge layer is provided to the gate electrode and the strain gate and germanium semiconductor material The drain semiconductor material and the channel semiconductor material are the same; or the drain semiconductor material, the drain semiconductor material, and the material comprising the following -·-the fourth group element and the semi-conducting device described in the i-lead Wherein the source + conductor material is different from at least the channel semiconductor material or a compound of a compound, a ternary compound, and 24 201236154 8. The semiconductor of claim 1 or 2 Device, wherein the semiconductor device package One of the following: a tunneling field effect transistor, a metal oxide semiconductor field effect transistor, and a collision free field effect transistor. y · A method for fabricating a semiconductor device, comprising the steps of: providing at least one The nanowire is configured to include: at least one source region including a corresponding source semiconductor material, at least one drain region including a corresponding drain semiconductor material, and at least one channel region including a corresponding channel semiconductor material, The channel region is disposed between the source region and the drain region; forming at least one gate electrode, the gate electrode is arranged to annularly surround at least a portion of the channel region with respect to the nanowire; forming At least one strain gate, the at least one strain gate being arranged to annularly surround at least a portion of one of the nanowires with respect to the nanowire; and configuring the strain gate to apply a strain to the nanometer a rice line segment whereby the energy band corresponding to the source region is promoted relative to/corresponding; at least one change in the energy band of the channel region. The method further includes the following steps: (iv) the strain gate is applied to - the (four) pole bias to the nano-section to promote electrostatic doping of the nano-section. 9 11. If claim 9 or 10 The method of Glyss &lt;RTIgt; </ RTI> wherein the strain gate 25 201236154 is selected to include a material selected to provide a particular strain value to the nano-section and having a polarity according to one of the semiconductor devices The method of claim 9 or 10, wherein in the step of providing the nanowire, the nanowire is substantially vertically aligned; or more comprising providing a strained gate spacer A step below the strain gate. 13. The method of claim 9 or 1 further comprising the step of conformally providing at least one gate dielectric on one of the outer surfaces of the nanowire; or wide/where the gate dielectric is provided In the step of quality, the gate dielectric is selected to comprise a dielectric material having a dielectric constant higher than 4 in strength compared to a vacuum. The method of claim 9 or 10, wherein the strain gate comprises a metal; or further comprising the step of providing an insulating layer between the gate electrode and the strain electrode; or In the step of providing the nanowire, the source semiconductor material, the drain semiconductor material, and the channel semiconductor material are selected to be the same; or, wherein the source semiconductor material, the drain semiconductor material, and The channel semiconductor material is selected to comprise one of the following: a group of elements and a binary compound thereof. 7 26 2U1236I54 1:). In the step of claim 9 or 1, the source semiconductor is in the semiconductor material providing the channel; the bulk material is selected to be different from the source semiconductor material The system is selected to include the following. A Group II material system, and a binary compound, a ternary compound, and a quaternary compound. 27
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