CN105990147B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof and electronic device, the described method includes: providing semiconductor substrate, it is formed with the first nano wire of several suspensions on the semiconductor substrate, and the side wall positioned at first nano wire both ends, source region, drain region are formed in the semiconductor substrate on the outside of the side wall；Form the epitaxial layer around the entire outer surface of the first nano wire；The gate structure of a part of the circular epitaxial layer of radial direction along first nano wire is formed on the semiconductor substrate；The source region, drain region are doped, to be respectively formed source electrode, drain electrode；Remove the side wall；Etching removes first nano wire, retains the epitaxial layer, to form the second nano wire.The loopful gate nano line field effect transistor that production method according to the present invention is formed has hollow nanowire structure, can reduce leakage current, improve electron mobility, and then improve the overall performance and reliability of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technique
Loopful gate device is widely used and is studied due to its excellent short-channel effect and static control ability.So
And as transistor size constantly reduces, severe intrinsic technological fluctuation just becomes the bottleneck of devices/circuits consistency control.It is main
The technological fluctuation wanted includes: discrete incidental impurities fluctuation (RDF), gate edge roughness (GER), line edge roughness
(LER), line width roughness (LWR), metal gates granularity and Random telegraph noise etc..Technique wave main for planar device
Move as discrete incidental impurities fluctuation, the FinFET with undoped fin structure can the influence appropriate that reduce RDF,
However, needing the width of FinFET fin more narrower better to obtain better Electrostatic Control power, this will lead to line side again
Edge roughness (LER) becomes main technique and fluctuates cause.Therefore, performance face is improved by reducing the size of FINFET device
Face some difficulties, and short-channel effect and grid leakage current can also destroy the switch performance of transistor under small size.
Loopful grid (Gate-All-Around, abbreviation GAA) silicon nanowires (nano-wire) field effect transistor is expected to solve
Certainly above-mentioned problem.On the one hand, the channel thickness in loopful grid silicon nanowires field effect transistor and width are all smaller, so that grid
Pole facilitates the grid modulation ability for enhancing transistor closer to the various pieces of channel, and due to using gate-all-around structure,
Grid is modulated channel from multiple directions, further enhances the modulation capability of grid, improves Sub-Threshold Characteristic.Therefore,
Ring gate nano line transistor can inhibit short-channel effect well, and transistor size is enable to further reduce.
On the other hand, loopful grid silicon nanowires field effect transistor improves grid using the rill road and gate-all-around structure of itself
Modulation forces and inhibition short-channel effect, alleviate the requirement of thinned grid medium thickness, so as to reduce grid leakage current.In addition,
Nanowire channel can undope, and reduce the discrete distribution of impurity in channel and Coulomb scattering.For 1-dimention nano wire channel, by
In quantum limitation effect, channel carriers are distributed far from surface, therefore carrier transport is by surface scattering and channel laterally electric field
It influences small, higher mobility can be obtained.
Therefore, device architecture and the technique preparation side of loopful grid silicon nanowires field effect transistor how to be advanced optimized
Method, the advantage for improving device performance, fully demonstrating loopful grid silicon nanowires field effect transistor, exactly present MOSFET in the world
The difficult point and hot spot of area research.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as presently, there are, a kind of production method of semiconductor devices is provided in one embodiment of the invention,
Include:
Semiconductor substrate is provided, is formed with the first nano wire of several suspensions on the semiconductor substrate, and be located at
The side wall at first nano wire both ends is formed with source region, drain region in the semiconductor substrate on the outside of the side wall；
Form the epitaxial layer around the entire outer surface of the first nano wire；
One of the circular epitaxial layer of radial direction along first nano wire is formed on the semiconductor substrate
The gate structure divided；
The source region, drain region are doped, to be respectively formed source electrode, drain electrode；
Remove the side wall；
Etching removes first nano wire, retains the epitaxial layer, to form the second nano wire.
A kind of production method of semiconductor devices is provided in another embodiment of the present invention, comprising:
Semiconductor substrate is provided, is formed with the first nano wire of several suspensions on the semiconductor substrate, and be located at
The side wall at first nano wire both ends is formed with source region, drain region in the semiconductor substrate on the outside of the side wall；
Form the epitaxial layer around the entire outer surface of the first nano wire；
Etching removes first nano wire, retains the epitaxial layer, to form the second nano wire；
The radial direction along second nano wire is formed on the semiconductor substrate around second nano wire
The gate structure of a part；
The source region, drain region are doped, to be respectively formed source electrode, drain electrode；
Remove the side wall.
Further, the method also includes formed in semiconductor substrate before forming the gate structure shallow trench every
From the step of.
Further, which is characterized in that the material of first nano wire includes germanium silicon, wherein the molar ratio range of silicon and germanium
For 10:1 to 1:10.
Further, the etching technics that etching removes first nano wire has the first nano wire high to the epitaxial layer
Etching selectivity.
Further, the gas source that etching removes the etching technics of first nano wire includes HCl or CF4。
Further, the material of the epitaxial layer is selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or III-V
The binary or ternary compound of race.
Further, the thickness range of the epitaxial layer is 1nm~20nm.
Further, the gate structure includes the lamination of gate dielectric from bottom to top and gate material layers.
Further, the gate dielectric is oxide skin(coating), and the gate material layers are polysilicon dummy gate material layer.
Second embodiment of the present invention provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
Hollow Nano cable architecture in the semiconductor substrate；
It is formed in the semiconductor substrate and is located at the source electrode of hollow Nano cable architecture two sides, drain electrode；
Radial direction in the semiconductor substrate, along the hollow Nano cable architecture surrounds the hollow Nano line
The gate structure of a part of structure.
Further, the material of the hollow Nano cable architecture be selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
The binary or ternary compound of AsGa or iii-v.
Further, the wall thickness range of the hollow Nano cable architecture is 1nm~20nm.
Further, the gate structure includes the lamination of gate dielectric from bottom to top and gate material layers.
Further, fleet plough groove isolation structure is also formed in semiconductor substrate.
The embodiment of the present invention three provides a kind of electronic device, including semiconductor devices above-mentioned.
In conclusion the loopful gate nano line field effect transistor that production method according to the present invention is formed, has hollow
Nanowire structure, can reduce leakage current, improve electron mobility, and then improve device overall performance and reliability.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A -1F shows the schematic diagram that production method according to the present invention successively implements obtained device, wherein figure
1A-1B is the 3 dimensional drawing of device, and Fig. 1 C corresponds to the main view direction sectional view of Figure 1B, and Fig. 1 D-1F is sectional view；
Fig. 2 shows the process flow charts of production method according to the present invention successively implementation steps.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
It is described in detail below with reference to production method of Figure 1A -1F and Fig. 2 to semiconductor devices of the invention.
Step 201 is executed, semiconductor substrate is provided, is formed with the nano wire of several suspensions on the semiconductor substrate,
And the side wall positioned at first nano wire both ends, be formed in the semiconductor substrate on the outside of the side wall source region,
Drain region.
With reference to Figure 1A, the semiconductor substrate 100 can be following at least one of the material being previously mentioned: silicon, insulation
Silicon (SOI) on body is laminated silicon (SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx is laminated on insulator on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..In addition, active area can be defined in semiconductor substrate.
It is formed with the first nano wire 101 of several suspensions on the semiconductor substrate, and is located at described first nanometer
The side wall 102 at 101 both ends of line.Optionally, the material of first nano wire includes germanium silicon, wherein the molar ratio range of silicon and germanium
For 10:1 to 1:10.
In one example, the step of forming the first nano wire 101 includes: offer semiconductor substrate, described partly to lead
Body substrate includes substrate, the buried oxide layer in substrate, and the germanium silicon layer on buried oxide layer, wherein germanium silicon
The molar ratio range of silicon and germanium in layer is 10:1 to 1:10, carries out photoetching composition and such as reactive ion etching to germanium silicon layer
(RIE) etch process is patterned to form the first nano wire, is aoxidized later by removing the buried layer being in contact with the first nano wire
Nitride layer makes the suspension of the first nano wire on a semiconductor substrate, further, also first can be made to receive by using such as annealing process
Rice noodles are smoothed, and to form the first nano wire for being suspended at cylindrical shape on semiconductor substrate, also may be selected to execute oxidation work
Skill is to reduce the diameter of the first nano wire 101 to expected size.The above method is only illustratively other any suitable sides
Method is suitable for the present invention.
The cross sectional shape of first nano wire radially can also be ellipse, rectangular or square.
The first nano wire 101 both ends formed composition formed side wall 102, the material of the side wall 102 include oxide,
Nitride, oxynitride or their combination are by depositing and etching formation.It is mainly used in subsequent progress ion note
Fashionable protection nano wire is injury-free and injects, therefore the both ends positioned at nano wire of side wall are respectively close to source region and drain electrode
Region.
Source region, drain region (not shown) are formed in the semiconductor substrate on the outside of the side wall.Namely
It is formed with source region, drain region on the outside of the both ends of one nano wire 101, any side well known to those skilled in the art can be used
Method defines the source region, drain region, such as while forming first nano wire, is defined by photoetching composition
Source region, drain region.
Step 202 is executed, the epitaxial layer around the entire outer surface of the first nano wire is formed.
With reference to Figure 1B and Fig. 1 C, epitaxial layer 103a is formed in the first nano wire appearance.The material of the epitaxial layer 103a
Binary or ternary compound of the material selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or other iii-vs.It is described
The thickness range of epitaxial layer 103a is 1nm~20nm.Above-mentioned thickness value range is only that illustratively, can also be carried out according to technique
Adjustment appropriate.
The method that selective epitaxial growth can be used forms epitaxial layer 103a.Selective epitaxial growth can use low pressure
Learn vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), one of rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).The selective epitaxial is raw
Length can carry out in UHV/CVD reaction chamber.
Step 203 is executed, forms the radial direction along first nano wire on the semiconductor substrate around described
The gate structure of a part of the first nano wire.
Before forming the gate structure, isolation structure can be first formed on the semiconductor substrate, such as described
Shallow trench isolation is formed in semiconductor substrate or localised oxide layer is preferably formed as in a specific embodiment of the invention
The forming method of fleet plough groove isolation structure, the shallow trench isolation can select method commonly used in the prior art.
With reference to Fig. 1 D, the radial direction along first nano wire 101 is formed in the semiconductor substrate 100 around institute
State the gate structure 104 of a part of epitaxial layer 103a.First nano wire 101 and epitaxial layer 103a are located at the grid knot
Under structure 104, the surrounding gate structure 104 controls and reduces shallow channel relative to existing planar transistor, in channel
Effect etc. has more superior performance；Planar gate is set to above the channel, and described in FinFET
Grid is arranged around the channel, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
The gate structure 104 includes the lamination of gate dielectric and gate material layers from bottom to top.In an example
In, the gate structure 104 is dummy gate structure, and the dummy gate is polysilicon gate, is used for that can be removed later
Form metal gates.
In another example, the gate dielectric is oxide skin(coating), and the gate material layers are polysilicon gate material
The bed of material, the method for formation are to form dielectric layer in the nanowire structure first, form gate oxide on the dielectric layer, as
It is preferred that the material of the gate oxide is silica, can be formed by the way of chemical vapor deposition.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon dummy gate material layer.It is formed
It is silane (SiH4) that the process conditions of the polysilicon layer, which include: reaction gas, the range of flow of the silane can for 100~
200 cc/mins (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；In reaction chamber
Pressure can be 250~350 milli millimetress of mercury (mTorr), such as 300mTorr；It may also include buffer gas in the reaction gas,
The buffer gas can be helium (He) or nitrogen, and the range of flow of the helium and nitrogen can be 5~20 liters/min (slm),
Such as 8slm, 10slm or 15slm.Then it is patterned, is formed in the semiconductor substrate 100 along first nano wire
Gate structure 104 of 101 radial direction around a part of the epitaxial layer 103a.
Preferably, in order to further increase the performance of the device, the gate structure 104 be metal gate structure or
High-K metal gate structure, in a specific embodiment of the invention, the forming method of the metal gate structure is first the
Polysilicon gate construction is formed on one nano wire, dummy gate is used as, removes the dummy gate then to form groove,
The bottom and side wall of the groove forms U-shaped gate dielectric, preferably, the gate dielectric comes for high k dielectric layer
The gate dielectric is formed, HfO is used for example in2The middle ratio for introducing the elements such as Si, Al, N, La, Ta and optimizing each element is come
Obtained hafnium etc..The method for forming the high k dielectric layer can be physical gas-phase deposition or atomic layer deposition work
Skill.Then, it fills multiple film stacks on the gate dielectric in the trench to be formed, the film includes work function gold
Belong to layer, barrier layer and conductive layer.The barrier layer includes TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or above-mentioned group
It closes.The deposition barrier layer process non-limiting example includes chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition
(PECVD).Ultimately form high-k/metal gate structure.Etching removal dummy gate is for those skilled in the art with shape
It is that common technical means in the art are not just discussed in detail one by one herein at metal gate structure.
Step 204 is executed, the source region, drain region are doped, to be respectively formed source electrode, drain electrode.
It is doped to be respectively formed source electrode and drain electrode.Illustratively, exposed source electrode can be formed on a semiconductor substrate
Then the photoresist layer in area and drain region executes ion implantation technology to form source electrode and drain electrode.When pre-formed semiconductor device
When part is p-type, dopant is P-type dopant, such as boron (B) and/or indium (In)；When pre-formed semiconductor devices is N-type,
Dopant is N type dopant, such as arsenic (As) and/or phosphorus (P).As a further preference, ion implanting or expansion are being carried out
The step of can further include a thermal annealing after dissipating.
Step 205 is executed, the side wall is removed.
With reference to Fig. 1 E, the side wall is removed.Any method well known to those skilled in the art can be used and remove the side wall,
Such as dry etching or wet-etching technology is selected to remove the side wall.Dry method etch technology includes but is not limited to: reactive ion
Etch (RIE), ion beam milling, plasma etching or laser cutting.It is carried out preferably by one or more RIE step
Dry etching.The etching has to the highly selective of side wall.
Step 206 is executed, etching removes first nano wire, retains the epitaxial layer, to form the second nano wire.
With reference to Fig. 1 F, etching removes first nano wire, retains the epitaxial layer, to form the second nano wire 103.Institute
Stating the second nano wire 103 is hollow structure.The etching technics that etching removes first nano wire has the first nano wire to institute
The high etching selectivity of epitaxial layer is stated, so that etching will not damage epitaxial layer, and being formed has the second hollow nano wire
103.The etching technics can be dry etching or wet etching.Illustratively, it if using dry etch process, can select
Including HCl or CF4The etch gas source of gas.
Later, also metal silicide layer can be formed on source electrode, drain electrode, gate structure.Then, interlayer dielectric layer is formed,
Then contact hole is formed in interlayer dielectric layer, is electrically connected with source electrode, drain electrode, grid.It is specific to form metal silicide layer, shape
It is art technology well-known technique at the method for contact hole, this will not be repeated here.So far it completes and loopful grid of the invention is received
The manufacturing process of rice noodles field effect transistor.
It in another embodiment of the invention, can also be by aforementioned implementation due to the end of the first nano wire of exposure outside side wall
Step 206 in example moves to before step 203 and after step 202, specific steps include: firstly, offer semiconductor substrate,
The first nano wire of several suspensions, and the side wall positioned at first nano wire both ends are formed in the semiconductor substrate,
Source region, drain region are formed in the semiconductor substrate on the outside of the side wall；Then, it is formed around described first nanometer
The epitaxial layer of the entire outer surface of line；Then, etching removes first nano wire, retains the epitaxial layer, is received with forming second
Rice noodles；Then, the radial direction along second nano wire is formed on the semiconductor substrate around second nano wire
A part gate structure；Then, the source region, drain region are doped, to be respectively formed source electrode, drain electrode；
Finally, removing the side wall.Using the method for the present embodiment, loopful gate nano line field effect transistor of the invention also can get
Pipe, it is specifically essentially identical in the implementation process and previous embodiment of every step, it does not repeat one by one no longer herein.
In conclusion the loopful gate nano line field effect transistor that production method according to the present invention is formed, has hollow
Nanowire structure, can reduce leakage current, improve electron mobility, and then improve device overall performance and reliability.In addition
Production method technological fluctuation of the invention is small, compatible well with existing semiconductor technology, while can also improve the short ditch of device
Channel effect, obtained device have good static control ability.
Embodiment two
The present invention also provides a kind of semiconductor devices made of method in previous embodiment, the semiconductor devices is
Loopful gate nano line field effect transistor.
Semiconductor devices includes semiconductor substrate, and the semiconductor substrate can be in the following material being previously mentioned at least
A kind of: silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), absolutely is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on edge body.Shallow trench isolation knot is also formed in semiconductor substrate
Structure.
It further include the hollow Nano cable architecture in the semiconductor substrate.The material of the hollow Nano cable architecture selects
From Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or the binary or ternary compound of other iii-vs.It is described hollow
The wall thickness range of nanowire structure is 1nm~20nm, but is not limited to above-mentioned numberical range, can according to the size of specific device
Select different numerical value.
It further include the source electrode for being formed in the semiconductor substrate and being located at hollow Nano cable architecture two sides, drain electrode；
It further include the radial direction in the semiconductor substrate, along the hollow Nano cable architecture around described hollow
The gate structure of a part of nanowire structure.Gate structure gate dielectric from bottom to top and gate material layers it is folded
Layer.
Gate dielectric may include traditional dielectric substance such as with electric medium constant from about 4 to about 20
Oxide, nitride and the nitrogen oxides of the silicon of (true aerial survety).Alternatively, gate dielectric may include normal with dielectric
Number from about 20 at least about 100 it is usual compared with high dielectric constant dielectric substance.It is this to be electrolysed compared with high dielectric constant
Material can include but is not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and lead zirconate titanate (PZTs).It can
To form gate dielectric using any of the several methods for the material for being suitble to gate dielectric composition of layer.Gate material layers can
To be made of polycrystalline silicon material, it generally can also be used metal, metal nitride, metal silicide or similar compound as grid
The material of material layer.
Illustratively, metal silicide layer and interlayer dielectric layer are also formed on source electrode, drain electrode, gate structure,
Contact hole is formed in interlayer dielectric layer, is electrically connected with source electrode, drain electrode, grid.
In conclusion loopful gate nano line field effect transistor of the invention, has hollow nanowire structure, can reduce
Leakage current improves electron mobility, and device has good static control ability, so that the overall performance of device and reliability are more
It is high.
Embodiment three
In addition the present invention also provides a kind of electronic device comprising semiconductor devices above-mentioned uses previous embodiment one
The semiconductor devices of kind method production.
Since the semiconductor devices for including has higher performance, which is equally had the above advantages.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, are also possible to have
The intermediate products of above-mentioned semiconductor device, such as: the cell phone mainboard etc. with the integrated circuit.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, is formed with the first nano wire of several suspensions on the semiconductor substrate, and is located at described
The side wall at the first nano wire both ends is formed with source region, drain region in the semiconductor substrate on the outside of the side wall；
Form the epitaxial layer around the entire outer surface of the first nano wire；
A part of the circular epitaxial layer of radial direction along first nano wire is formed on the semiconductor substrate
Gate structure；
The source region, drain region are doped, to be respectively formed source electrode, drain electrode；
Remove the side wall；
Etching removes first nano wire, retains the epitaxial layer, to form the second nano wire.
2. a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, is formed with the first nano wire of several suspensions on the semiconductor substrate, and is located at described
The side wall at the first nano wire both ends is formed with source region, drain region in the semiconductor substrate on the outside of the side wall；
Form the epitaxial layer around the entire outer surface of the first nano wire；
Etching removes first nano wire, retains the epitaxial layer, to form the second nano wire；
One of circular second nano wire of radial direction along second nano wire is formed on the semiconductor substrate
The gate structure divided；
The source region, drain region are doped, to be respectively formed source electrode, drain electrode；
Remove the side wall.
3. method according to claim 1 or 2, which is characterized in that the method also includes forming the gate structure
The step of shallow trench isolation is formed in semiconductor substrate before.
4. method according to claim 1 or 2, which is characterized in that the material of first nano wire includes germanium silicon, wherein
The molar ratio range of silicon and germanium is 10:1 to 1:10.
5. method according to claim 1 or 2, which is characterized in that etching removes the etching technics of first nano wire
With the first nano wire etching selectivity high to the epitaxial layer.
6. method according to claim 1 or 2, which is characterized in that etching removes the etching technics of first nano wire
Gas source include HCl or CF4。
7. method according to claim 1 or 2, which is characterized in that the material of the epitaxial layer be selected from Si, SiB, SiGe,
The binary or ternary compound of SiC, SiP, SiGeB, SiCP, AsGa or iii-v.
8. method according to claim 1 or 2, which is characterized in that the thickness range of the epitaxial layer is 1nm~20nm.
9. method according to claim 1 or 2, which is characterized in that the gate structure includes grid Jie from bottom to top
The lamination of electric layer and gate material layers.
10. according to the method described in claim 9, it is characterized in that, the gate dielectric is oxide skin(coating), the grid material
The bed of material is polysilicon dummy gate material layer.
11. a kind of semiconductor devices that the method using as described in any one of claims 1 to 10 prepares, comprising:
Semiconductor substrate；
Hollow Nano cable architecture in the semiconductor substrate；
It is formed in the semiconductor substrate and is located at the source electrode of hollow Nano cable architecture two sides, drain electrode；
Radial direction in the semiconductor substrate, along the hollow Nano cable architecture surrounds the hollow Nano cable architecture
A part gate structure.
12. semiconductor devices according to claim 11, which is characterized in that the material of the hollow Nano cable architecture is selected from
The binary or ternary compound of Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or iii-v.
13. semiconductor devices according to claim 11, which is characterized in that the wall thickness range of the hollow Nano cable architecture
For 1nm~20nm.
14. semiconductor devices according to claim 11, which is characterized in that the gate structure includes grid from bottom to top
The lamination of pole dielectric layer and gate material layers.
15. semiconductor devices according to claim 11, which is characterized in that be also formed with shallow trench in semiconductor substrate
Isolation structure.
16. a kind of electronic device, which is characterized in that including the semiconductor devices as described in any one of claim 11-15.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510089794.8A CN105990147B (en) | 2015-02-27 | 2015-02-27 | A kind of semiconductor devices and preparation method thereof and electronic device |
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| CN101065811A (en) * | 2004-05-25 | 2007-10-31 | 国际商业机器公司 | Method of fabricating a tunneling nanotube field effect transistor |
| CN103915484A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified for a backgate bias and method of fabrication |
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| CN101065811A (en) * | 2004-05-25 | 2007-10-31 | 国际商业机器公司 | Method of fabricating a tunneling nanotube field effect transistor |
| CN103915484A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified for a backgate bias and method of fabrication |
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