CN105990147A - Semiconductor device and manufacturing method thereof and electronic device - Google Patents
Semiconductor device and manufacturing method thereof and electronic device Download PDFInfo
- Publication number
- CN105990147A CN105990147A CN201510089794.8A CN201510089794A CN105990147A CN 105990147 A CN105990147 A CN 105990147A CN 201510089794 A CN201510089794 A CN 201510089794A CN 105990147 A CN105990147 A CN 105990147A
- Authority
- CN
- China
- Prior art keywords
- nano wire
- semiconductor substrate
- nano
- epitaxial layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The present invention provides a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises: providing semiconductor substrates, forming a plurality of suspending first nano wires on the semiconductor substrates and side walls located at two ends of each first nano wire, forming an active pole region and a drain pole region on the semiconductor substrate at the outer side of each side wall; forming an epitaxial layer around the whole external surface of each first nano wire; forming a grid structure surrounding one part of the epitaxial layer with the vertical direction of each nano wire on each semiconductor substrate; doping the active pole region and the drain pole region to respectively form an active pole and a drain pole; and removing the side walls; etching and removing the first nano wires, and maintaining the epitaxial layer to form a second nano wire. The whole-ring grid field effect transistor formed by the manufacturing method of the semiconductor device has a hollow nano wire structure to reduce the leakage current and improve the electron mobility so as to improve the whole performances and reliability of the device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and
Manufacture method and electronic installation.
Background technology
Loopful gate device due to its excellence short-channel effect and static control ability and by extensively
Application and research.Constantly reduce however as transistor size, severe intrinsic technological fluctuation
Just become the bottleneck that devices/circuits concordance controls.Main technological fluctuation includes: discrete
Incidental impurities fluctuation (RDF), gate edge roughness (GER), line edge roughness (LER),
Line width roughness (LWR), metal gates granularity and Random telegraph noise etc..For plane
The main technological fluctuation of device is discrete incidental impurities fluctuation, has undoped fin structure
FinFET can be suitable the impact of reduction RDF, but, the most quiet in order to obtain
Electric control power needs the width of FinFET fin the narrowest more good, and this can cause again line edge
Roughness (LER) becomes main technique fluctuation cause.Therefore, by reducing FINFET device
The size of part improves performance and has faced some difficulties, and short-channel effect and grid under small size
Leakage current also can destroy the switch performance of transistor.
Loopful grid (Gate-All-Around is called for short GAA) silicon nanowires (nano-wire)
Field-effect transistor is expected to solve above-mentioned problem.On the one hand, loopful grid silicon nanowires field effect
Channel thickness and width in transistor are the least so that grid is closer to each portion of raceway groove
Point, contribute to strengthening the grid modulation ability of transistor, and owing to using gate-all-around structure, grid
Raceway groove is modulated by pole from multiple directions, further enhancing the modulation capability of grid, improves
Sub-Threshold Characteristic.Therefore, ring gate nano line transistor can suppress short-channel effect well,
Transistor size is made to be reduced further.
On the other hand, loopful grid silicon nanowires field-effect transistor utilizes rill road and the ring of self
Grid structure improves grid modulation power and suppression short-channel effect, alleviates thinning grid medium thickness
Requirement, thus grid leakage current can be reduced.Additionally, nanowire channel can undope, reduce
Impurity Discrete Distribution and Coulomb scattering in raceway groove.For 1-dimention nano wire channel, due to quantum
Restriction effect, raceway groove carriers away from surface distributed, therefore carrier transport by surface scattering and
The impact of channel laterally electric field is little, it is possible to obtain higher mobility.
Therefore, the device architecture of loopful grid silicon nanowires field-effect transistor is optimized the most further
With its preparation process, improve device performance, to fully demonstrate loopful grid silicon nanowires field effect brilliant
The advantage of body pipe, the just now difficult point of MOSFET area research and focus the most in the world.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, one embodiment of the invention provides a kind of semiconductor device
The manufacture method of part, including:
Semiconductor substrate is provided, is formed with the first of some suspensions on the semiconductor substrate and receives
Rice noodle, and it is positioned at the side wall at described first nano wire two ends, partly leading outside described side wall
Source region, drain region it is formed with on body substrate；
Form the epitaxial layer around the described first whole outer surface of nano wire；
Form the radial direction along described first nano wire on the semiconductor substrate around institute
State the grid structure of a part for epitaxial layer；
Described source region, drain region are doped, to form source electrode, drain electrode respectively；
Remove described side wall；
Etching removes described first nano wire, retains described epitaxial layer, to form the second nano wire.
Another embodiment of the present invention provides the manufacture method of a kind of semiconductor device, including:
Semiconductor substrate is provided, is formed with the first of some suspensions on the semiconductor substrate and receives
Rice noodle, and it is positioned at the side wall at described first nano wire two ends, partly leading outside described side wall
Source region, drain region it is formed with on body substrate；
Form the epitaxial layer around the described first whole outer surface of nano wire；
Etching removes described first nano wire, retains described epitaxial layer, to form the second nano wire；
Form the radial direction along described second nano wire on the semiconductor substrate around institute
State the grid structure of a part for the second nano wire；
Described source region, drain region are doped, to form source electrode, drain electrode respectively；
Remove described side wall.
Further, in Semiconductor substrate before described method is additionally included in the described grid structure of formation
The step of interior formation shallow trench isolation.
Further, it is characterised in that the material of described first nano wire includes germanium silicon, wherein silicon
It is 10:1 to 1:10 with the molar ratio range of germanium.
Further, the etching technics of described first nano wire of etching removal has the first nano wire pair
The etching selectivity of described extension floor height.
Further, the gas source of the etching technics that etching removes described first nano wire includes HCl
Or CF4。
Further, the material of described epitaxial layer selected from Si, SiB, SiGe, SiC, SiP, SiGeB,
SiCP, AsGa or the binary of iii-v or ternary compound.
Further, the thickness range of described epitaxial layer is 1nm～20nm.
Further, described grid structure includes gate dielectric from bottom to top and gate material layers
Lamination.
Further, described gate dielectric is oxide skin(coating), and described gate material layers is polysilicon
Dummy gate material layer.
The embodiment of the present invention two provides a kind of semiconductor device, including:
Semiconductor substrate；
The hollow Nano line structure being positioned in described Semiconductor substrate；
It is formed in described Semiconductor substrate and is positioned at the source of described hollow Nano line structure both sides
Pole, drain electrode；
Be positioned in described Semiconductor substrate, along described hollow Nano line structure radial direction around
The grid structure of a part for described hollow Nano line structure.
Further, the material of described hollow Nano line structure selected from Si, SiB, SiGe, SiC,
SiP, SiGeB, SiCP, AsGa or the binary of iii-v or ternary compound.
Further, the wall thickness range of described hollow Nano line structure is 1nm～20nm.
Further, described grid structure includes gate dielectric from bottom to top and gate material layers
Lamination.
Further, in Semiconductor substrate, fleet plough groove isolation structure it is also formed with.
The embodiment of the present invention three provides a kind of electronic installation, including aforesaid semiconductor device.
In sum, the loopful gate nano line field effect formed according to the manufacture method of the present invention is brilliant
Body pipe, has hollow nano thread structure, can reduce leakage current, improve electron mobility, enter
And improve overall performance and the reliability of device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-1F shows that the manufacture method according to the present invention implements obtained device successively
Schematic diagram, wherein, Figure 1A-1B is the 3 dimensional drawing of device, and Fig. 1 C corresponds to Figure 1B
Main apparent direction profile, Fig. 1 D-1F is profile；
Fig. 2 shows that the manufacture method according to the present invention implements the process chart of step successively.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " connect
To " or " being coupled to " other element or during layer, its can directly on other element or layer,
Adjacent thereto, be connected or coupled to other element or layer, or can exist element between two parties or
Layer.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " directly connect
Receive " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.
Although it should be understood that and term first, second, third, etc. can being used to describe various element, portion
Part, district, floor and/or part, these elements, parts, district, floor and/or part the most should be by
These terms limit.These terms are used merely to distinguish an element, parts, district, floor or portion
Divide and another element, parts, district, floor or part.Therefore, without departing from present invention teach that
Under, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ...
Under ", " ... on ", " above " etc., here can describe for convenience and be used
Thus shown in figure a element or feature and other element or the relation of feature are described.Should
Understanding, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and grasping
The different orientation of the device in work.Such as, if the device upset in accompanying drawing, then, describe
To take for " below other element " or " under it " or " under it " element or feature
To for other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention describes in detail
As follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Embodiment one
Below with reference to Figure 1A-1F and Fig. 2, the manufacture method of the semiconductor device of the present invention is done
Describe in detail.
Perform step 201, it is provided that Semiconductor substrate, if being formed with on the semiconductor substrate
The nano wire of dry suspension, and it is positioned at the side wall at described first nano wire two ends, at described side wall
It is formed with source region, drain region in the Semiconductor substrate in outside.
With reference to Figure 1A, described Semiconductor substrate 100 can be in the following material being previously mentioned
At least one: stacking silicon (SSOI) on silicon, silicon-on-insulator (SOI), insulator,
Stacking SiGe (S-SiGeOI) on insulator, germanium on insulator SiClx (SiGeOI) with
And germanium on insulator (GeOI) etc..Additionally, can be defined active in Semiconductor substrate
District.
It is formed with the first nano wire 101 of some suspensions on the semiconductor substrate, and
It is positioned at the side wall 102 at described first nano wire 101 two ends.Alternatively, described first nano wire
Material include germanium silicon, wherein silicon is 10:1 to 1:10 with the molar ratio range of germanium.
In one example, the step forming described first nano wire 101 includes: provides and partly leads
Body substrate, described Semiconductor substrate includes substrate, is positioned at suprabasil buried oxide layer, and
The germanium silicon layer being positioned on buried oxide layer, the wherein silicon in germanium silicon layer and the molar ratio range of germanium
For 10:1 to 1:10, germanium silicon layer is carried out photoetching composition and such as reactive ion etching (RIE)
Etch process be patterned to form the first nano wire, connect with the first nano wire by removing afterwards
The buried oxide layer touched, makes the first nano wire suspend on a semiconductor substrate, further,
Also by using such as annealing process to make the first nano wire be smoothed, partly lead to be formed to be suspended at
First nano wire of body substrate cylindrical shape, the also optional oxidation technology that performs is to reduce the
The diameter of one nano wire 101 is to intended size.Said method is only exemplarily, other
The method what is suitable for all is applicable to the present invention.
Described first nano wire cross sectional shape radially can also be oval, rectangle or pros
Shape.
Form composition at the two ends of the first nano wire 101 and form side wall 102, described side wall 102
Material include oxide, nitride, oxynitride or combinations thereof, be by deposition and
Etching is formed.It is mainly used in follow-up carry out ion implanting time protection nano wire injury-free
And injection, therefore the two ends being positioned at nano wire of side wall are respectively close to source region and drain region
Territory.
Source region, drain region it is formed with (not in Semiconductor substrate outside described side wall
Illustrate).Namely it is formed with source region, drain region outside the two ends of the first nano wire 101
Territory, can use any method well known to those skilled in the art to define described source region, drain electrode
Region, such as, while forming described first nano wire, define source electrode by photoetching composition
Region, drain region.
Perform step 202, form the epitaxial layer around the described first whole outer surface of nano wire.
With reference to Figure 1B and Fig. 1 C, form epitaxial layer 103a in described first nano wire appearance.
The material of described epitaxial layer 103a selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or the binary of other iii-v or ternary compound.The thickness of described epitaxial layer 103a
Scope is 1nm～20nm.Above-mentioned thickness value scope is only exemplarily, also can be according to technique
Carry out suitable adjustment.
The method that can use selective epitaxial growth forms epitaxial layer 103a.Selective epitaxial is raw
Length can use low-pressure chemical vapor deposition (LPCVD), PECVD heavy
Long-pending (PECVD), ultra-high vacuum CVD (UHVCVD), rapid heat chemical gas
Deposit the one in (RTCVD) and molecular beam epitaxy (MBE) mutually.Outside described selectivity
Epitaxial growth can be carried out in UHV/CVD reaction chamber.
Perform step 203, form the footpath along described first nano wire on the semiconductor substrate
To direction around the grid structure of a part of described first nano wire.
Before forming described grid structure, isolation junction can be formed the most on the semiconductor substrate
Structure, forms shallow trench isolation or localised oxide layer, the most on the semiconductor substrate at this
Invention a detailed description of the invention in, be preferably formed as fleet plough groove isolation structure, described shallow trench every
From forming method can select method commonly used in the prior art.
With reference to Fig. 1 D, described Semiconductor substrate 100 is formed along described first nano wire 101
Radial direction around the grid structure 104 of a part of described epitaxial layer 103a.Described
One nano wire 101 and epitaxial layer 103a are positioned under described grid structure 104, described cincture
Grid structure 104 is relative to existing planar transistor, in raceway groove control and reduction shallow channel
The aspects such as effect have more superior performance；Planar gate is arranged on described raceway groove
Side, and arrange around described raceway groove at grid described in FinFET, therefore can come from three faces
Controlling electrostatic, the performance in terms of Electrostatic Control is the most prominent.
Described grid structure 104 includes gate dielectric from bottom to top and gate material layers
Lamination.In one example, described grid structure 104 is dummy gate structure, described virtual
Grid is polysilicon gate, can be removed for forming metal gates later.
In another example, described gate dielectric is oxide skin(coating), described gate material layers
For polysilicon gate material layer, the method for formation is first to be formed to be situated between on described nano thread structure
Electric layer, forms gate oxide on the dielectric layer, and as preferably, the material of described gate oxide is
Silicon dioxide, can be formed in the way of using chemical gaseous phase deposition.
The forming method of polysilicon dummy gate material layer can be selected for low-pressure chemical vapor phase deposition
(LPCVD) technique.The process conditions forming described polysilicon layer include: reacting gas is silane
(SiH4), the range of flow of described silane can be 100～200 cc/min (sccm),
Such as 150sccm；In reaction chamber, temperature range can be 700～750 degrees Celsius；Reaction chamber is intrinsic pressure
Power can be 250～350 millis millimetres of mercury (mTorr), such as 300mTorr；In described reacting gas
May also include buffer gas, described buffer gas can be helium (He) or nitrogen, described helium and
The range of flow of nitrogen can be 5～20 liters/min (slm), such as 8slm, 10slm or 15slm.
Then pattern, described Semiconductor substrate 100 is formed along described first nano wire
The radial direction of 101 is around the grid structure 104 of a part of described epitaxial layer 103a.
As preferably, in order to improve the performance of described device further, described grid structure 104
For metal gate structure or high-K metal gate electrode structure, in a detailed description of the invention of the present invention
In, the forming method of described metal gate structure is first to form polysilicon gate on the first nano wire
Electrode structure, it is as dummy gate, then removes described dummy gate to form groove, in institute
Bottom and the sidewall of stating groove form U-shaped gate dielectric, as preferably, and described grid
Dielectric layer be high k dielectric layer to form described gate dielectric, be used for example in HfO2Middle introducing
The elements such as Si, Al, N, La, Ta also optimize the hafnium etc. that the ratio of each element obtains.
The method forming described high k dielectric layer can be physical gas-phase deposition or ald
Technique.Then, the most described gate dielectric is filled multiple film stack and is formed,
Described thin film includes workfunction layers, barrier layer and conductive layer.Described barrier layer include TaN,
TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above.Described deposition stops
Layer method limiting examples includes chemical vapour deposition technique (CVD), as low temperature chemical vapor sinks
Long-pending (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition
(LTCVD), plasma activated chemical vapour deposition (PECVD).Ultimately form high-k/metal gate
Structure.Etching removes dummy gate to form metal gates for a person skilled in the art
Structure is that any technique commonly known means are discussed in detail the most one by one at this.
Perform step 204, described source region, drain region are doped, with shape respectively
Become source electrode, drain electrode.
It is doped to form source electrode and drain electrode respectively.Exemplarily, can be in Semiconductor substrate
Upper formation source of exposure polar region and the photoresist layer of drain region, then perform ion implantation technology with shape
Become source electrode and drain electrode.When preformed semiconductor device is p-type, adulterant is p-type doping
Agent, such as boron (B) and/or indium (In)；When preformed semiconductor device is N-type, mix
Miscellaneous dose is N type dopant, such as arsenic (As) and/or phosphorus (P).As the most preferred,
The step of a thermal annealing is can further include after carrying out ion implanting or diffusion.
Perform step 205, remove described side wall.
With reference to Fig. 1 E, remove described side wall.Can use well known to those skilled in the art any
Method removes described side wall, such as, select dry etching or wet-etching technology to remove described side
Wall.Dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling,
Plasma etching or cut.Do preferably by one or more RIE step
Method etches.Described etching has the high selectivity to side wall.
Performing step 206, etching is removed described first nano wire, is retained described epitaxial layer, with
Form the second nano wire.
With reference to Fig. 1 F, etching is removed described first nano wire, is retained described epitaxial layer, with shape
Become the second nano wire 103.Described second nano wire 103 is hollow-core construction.Etching is removed described
The etching technics of the first nano wire has the first nano wire and selects the etching of described extension floor height
Ratio, so that etching will not damage epitaxial layer, and is formed and has the second hollow nano wire 103.
Described etching technics can be dry etching or wet etching.Exemplarily, if using dry method to carve
Etching technique, can select and include HCl or CF4The etch gas source of gas.
Afterwards, metal silicide layer can also be formed on source electrode, drain electrode, grid structure.Then,
Formed interlayer dielectric layer, then in interlayer dielectric layer formed contact hole, with source electrode, drain electrode,
Grid electrically connects.Concrete formation metal silicide layer, the method for formation contact hole are this area
Technology known technology, does not repeats at this.So far the loopful gate nano line to the present invention is completed
The manufacturing process of field-effect transistor.
In another embodiment of the invention, owing to exposing the end of the first nano wire outside side wall,
Before step 206 in previous embodiment also can be moved to step 203 and after step 202,
Concrete steps include: first, it is provided that Semiconductor substrate, are formed on the semiconductor substrate
First nano wire of some suspensions, and it is positioned at the side wall at described first nano wire two ends, in institute
State and in the Semiconductor substrate outside side wall, be formed with source region, drain region；Then, formed
Epitaxial layer around the described first whole outer surface of nano wire；Then, etching removes described first
Nano wire, retains described epitaxial layer, to form the second nano wire；Then, at described quasiconductor
The radial direction along described second nano wire is formed around the one of described second nano wire on substrate
The grid structure of part；Then, described source region, drain region are doped, to divide
Do not form source electrode, drain electrode；Finally, described side wall is removed.The method using the present embodiment, also
Can obtain the loopful gate nano line field-effect transistor of the present invention, the implementation process the most often walked with
In previous embodiment essentially identical, repeat the most one by one at this.
In sum, the loopful gate nano line field effect formed according to the manufacture method of the present invention is brilliant
Body pipe, has hollow nano thread structure, can reduce leakage current, improve electron mobility, enter
And improve overall performance and the reliability of device.The additionally manufacture method technological fluctuation of the present invention
Little, the most compatible with existing semiconductor technology, the most also can improve the short-channel effect of device,
Obtained device has good static control ability.
Embodiment two
The present invention also provides for a kind of semiconductor device using method in previous embodiment to make, institute
Stating semiconductor device is loopful gate nano line field-effect transistor.
Semiconductor device includes that Semiconductor substrate, described Semiconductor substrate can be following being carried
To material at least one: stacking silicon on silicon, silicon-on-insulator (SOI), insulator
(SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).It is also formed with in Semiconductor substrate
Fleet plough groove isolation structure.
Also include the hollow Nano line structure being positioned in described Semiconductor substrate.Described hollow Nano
The material of line structure is selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa
Or the binary of other iii-v or ternary compound.The wall thickness model of described hollow Nano line structure
Enclose for 1nm～20nm, but be not limited to above-mentioned numerical range, according to the size of concrete device
Optional different numerical value.
Also include being formed in described Semiconductor substrate and be positioned at described hollow Nano line structure two
The source electrode of side, drain electrode；
Also include being positioned in described Semiconductor substrate, along the radial direction side of described hollow Nano line structure
Grid structure to the part around described hollow Nano line structure.Described grid structure under
Gate dielectric on and and the lamination of gate material layers.
Gate dielectric can include traditional dielectric substance such as have electric medium constant from
The oxide of silicon, nitride and the nitrogen oxides of about 4 to about 20 (true aerial surveties).Or
Person, gate dielectric can include having electric medium constant from about 20 at least about 100
Usual relatively high dielectric constant dielectric substance.This relatively high dielectric constant electrolyte
Can include but not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and zirconium
Lead titanates (PZTs).Can use the material of applicable gate dielectric composition of layer several methods appoint
What a kind of formation gate dielectric.Gate material layers can be made up of polycrystalline silicon material, the most also
Metal, metal nitride, metal silicide or similar compound can be used as gate material layers
Material.
Exemplarily, source electrode, drain electrode, grid structure are also formed with metal silicide layer with
And interlayer dielectric layer, interlayer dielectric layer forms contact hole, with source electrode, drain electrode, grid
Electrical connection.
In sum, the loopful gate nano line field-effect transistor of the present invention, there is hollow receiving
Nanowire structure, can reduce leakage current, improve electron mobility, and device has good electrostatic control
Ability processed so that overall performance and the reliability of device are higher.
Embodiment three
The present invention additionally also provides for a kind of electronic installation, and it includes aforesaid semiconductor device or adopts
The semiconductor device made by a kind of method of previous embodiment.
Semiconductor device owing to including has higher performance, on this electronic installation has equally
State advantage.
This electronic installation, can be mobile phone, panel computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment, it is also possible to be that there is above-mentioned quasiconductor
The intermediate products of device, such as: there is the cell phone mainboard etc. of this integrated circuit.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for semiconductor device, including:
Semiconductor substrate is provided, is formed with the first of some suspensions on the semiconductor substrate and receives
Rice noodle, and it is positioned at the side wall at described first nano wire two ends, partly leading outside described side wall
Source region, drain region it is formed with on body substrate；
Form the epitaxial layer around the described first whole outer surface of nano wire；
Form the radial direction along described first nano wire on the semiconductor substrate around institute
State the grid structure of a part for epitaxial layer；
Described source region, drain region are doped, to form source electrode, drain electrode respectively；
Remove described side wall；
Etching removes described first nano wire, retains described epitaxial layer, to form the second nano wire.
2. a manufacture method for semiconductor device, including:
Semiconductor substrate is provided, is formed with the first of some suspensions on the semiconductor substrate and receives
Rice noodle, and it is positioned at the side wall at described first nano wire two ends, partly leading outside described side wall
Source region, drain region it is formed with on body substrate；
Form the epitaxial layer around the described first whole outer surface of nano wire；
Etching removes described first nano wire, retains described epitaxial layer, to form the second nano wire；
Form the radial direction along described second nano wire on the semiconductor substrate around institute
State the grid structure of a part for the second nano wire；
Described source region, drain region are doped, to form source electrode, drain electrode respectively；
Remove described side wall.
Method the most according to claim 1 and 2, it is characterised in that described method is also
It is included in the step forming shallow trench isolation before forming described grid structure in Semiconductor substrate
Suddenly.
Method the most according to claim 1 and 2, it is characterised in that described first receives
The material of rice noodle includes germanium silicon, and wherein silicon is 10:1 to 1:10 with the molar ratio range of germanium.
Method the most according to claim 1 and 2, it is characterised in that etching removes institute
The etching technics stating the first nano wire has the etching choosing to described extension floor height of first nano wire
Select ratio.
Method the most according to claim 1 and 2, it is characterised in that etching removes institute
The gas source of the etching technics stating the first nano wire includes HCl or CF4。
Method the most according to claim 1 and 2, it is characterised in that described epitaxial layer
Material selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or III-V
The binary of race or ternary compound.
Method the most according to claim 1 and 2, it is characterised in that described epitaxial layer
Thickness range be 1nm～20nm.
Method the most according to claim 1 and 2, it is characterised in that described grid is tied
Structure includes the lamination of gate dielectric from bottom to top and gate material layers.
Method the most according to claim 9, it is characterised in that described gate dielectric
For oxide skin(coating), described gate material layers is polysilicon dummy gate material layer.
11. 1 kinds of semiconductor device, including:
Semiconductor substrate；
The hollow Nano line structure being positioned in described Semiconductor substrate；
It is formed in described Semiconductor substrate and is positioned at the source of described hollow Nano line structure both sides
Pole, drain electrode；
Be positioned in described Semiconductor substrate, along described hollow Nano line structure radial direction around
The grid structure of a part for described hollow Nano line structure.
12. semiconductor device according to claim 11, it is characterised in that described sky
The material of heart nano thread structure selected from Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or the binary of iii-v or ternary compound.
13. semiconductor device according to claim 11, it is characterised in that described sky
The wall thickness range of heart nano thread structure is 1nm～20nm.
14. semiconductor device according to claim 11, it is characterised in that described grid
Electrode structure includes the lamination of gate dielectric from bottom to top and gate material layers.
15. semiconductor device according to claim 11, it is characterised in that partly leading
It is also formed with fleet plough groove isolation structure in body substrate.
16. 1 kinds of electronic installations, it is characterised in that include as arbitrary in claim 11-15
Semiconductor device described in Xiang.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510089794.8A CN105990147B (en) | 2015-02-27 | 2015-02-27 | A kind of semiconductor devices and preparation method thereof and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510089794.8A CN105990147B (en) | 2015-02-27 | 2015-02-27 | A kind of semiconductor devices and preparation method thereof and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990147A true CN105990147A (en) | 2016-10-05 |
| CN105990147B CN105990147B (en) | 2019-01-22 |
Family
ID=57038747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510089794.8A Active CN105990147B (en) | 2015-02-27 | 2015-02-27 | A kind of semiconductor devices and preparation method thereof and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990147B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101065811A (en) * | 2004-05-25 | 2007-10-31 | 国际商业机器公司 | Method of fabricating a tunneling nanotube field effect transistor |
| US20110168982A1 (en) * | 2010-01-08 | 2011-07-14 | International Business Machines Corporation | Nanowire pin tunnel field effect devices |
| CN103915484A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified for a backgate bias and method of fabrication |
-
2015
- 2015-02-27 CN CN201510089794.8A patent/CN105990147B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101065811A (en) * | 2004-05-25 | 2007-10-31 | 国际商业机器公司 | Method of fabricating a tunneling nanotube field effect transistor |
| US20110168982A1 (en) * | 2010-01-08 | 2011-07-14 | International Business Machines Corporation | Nanowire pin tunnel field effect devices |
| CN103915484A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified for a backgate bias and method of fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990147B (en) | 2019-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8455334B2 (en) | Planar and nanowire field effect transistors | |
| KR101891458B1 (en) | Semiconductor device having iii-v semiconductor material layer | |
| KR102216424B1 (en) | Techniques for improving gate control over transistor channel by increasing effective gate length | |
| US11756956B2 (en) | Semiconductor device, manufacturing method thereof, and electronic apparatus including the same | |
| US20150132908A1 (en) | Method for fabricating semiconductor device | |
| US20190115479A1 (en) | Vertical Tunnel FET with Self-Aligned Heterojunction | |
| US9960233B2 (en) | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor | |
| CN104183487A (en) | FinTFET semiconductor device and manufacturing method thereof | |
| US11120991B2 (en) | Lateral semiconductor nanotube with hexagonal shape | |
| CN109473398B (en) | Semiconductor device and method for manufacturing the same | |
| TW201906161A (en) | Gate-all-around field effect transistor having ultra-thin-body and method of fabricating the same | |
| CN106972057A (en) | Semiconductor devices and its manufacture method | |
| KR20220052288A (en) | Formation of gate all around device | |
| CN108091569A (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| CN107424994A (en) | Ring grid III-V quantum well transistors and germanium nodeless mesh body pipe and its manufacture method | |
| CN105990147B (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| US20240038553A1 (en) | Processing methods and cluster tools for forming semiconductor devices | |
| TWI817704B (en) | Semiconductor device and method for forming the same | |
| CN102646624A (en) | Three-dimensional array type back grid type Si-NWFET (Nano Wire Field Effect Transistor) manufacturing method based on SOI (Silicon On Insulator) | |
| US20230067331A1 (en) | Source drain formation in gate all around transistor | |
| CN102646598A (en) | Vertically-overlapped back grid type Si-NWFET (Nano Wire Field Effect Transistor) manufacturing method based on SOI (Silicon On Insulator) | |
| US20230402536A1 (en) | Field effect transistor with gate isolation structure and method | |
| US20220246742A1 (en) | Gate all around device with fully-depleted silicon-on-insulator | |
| US20230040606A1 (en) | Template for nanosheet source drain formation with bottom dielectric | |
| CN104282558A (en) | Knot-free nanowire FinFET and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |