CN102646624A - Three-dimensional array type back grid type Si-NWFET (Nano Wire Field Effect Transistor) manufacturing method based on SOI (Silicon On Insulator) - Google Patents
Three-dimensional array type back grid type Si-NWFET (Nano Wire Field Effect Transistor) manufacturing method based on SOI (Silicon On Insulator) Download PDFInfo
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Abstract
The invention provides a three-dimensional array type back grid type Si-NWFET (Nano Wire Field Effect Transistor) manufacturing method based on an SOI (Silicon On Insulator). The manufacturing method comprises the following steps of: alternatively depositing a silicon layer and a germanium-silicon layer on the SOI to form a fin-shaped active region, and forming a silicon nano wire in the fin-shaped active region, wherein the silicon nano wire is a three-dimensional array type; then, forming an isolating medium layer between source drain regions; forming a grid electrode oxidization layer on the surface of the silicon nano wire; and finally, forming a grid electrode on an SOI substrate in the fin-shaped active region. Due to the presence of an insulator layer in the SOI, the isolation effect between the grid electrode and the SOI substrate is effectively increased; a process for forming the grid electrode oxidization layer on the silicon nano wire is independently carried out so that the conventional grid electrode oxidization layer is adopted; and the grid electrode is formed after ions are injected into the source drain regions, namely a back grid electrode process is adopted, so that the preparation method is good for controlling an outline of the grid electrode and an electrical property of a device. Furthermore, a silicon nano wire field effect transistor structure is designed by a three-dimensional array type back grid type silicon nano wire structure; and the quantity of nano wires is increased and the current driving capability of the device can be increased.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly a kind of based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI.
Background technology
Through dwindle transistorized size improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in the microelectronics industry development always.Current; The physical gate of field-effect transistor is long near 20nm; Gate medium also only has the thickness of several oxygen atomic layers; Improve performance through the size of dwindling conventional field effect transistor and faced some difficulties, this mainly is to have destroyed transistorized switch performance because of short-channel effect under the small size and grid leakage current.
Nano-wire field effect transistor (NWFET, Nano-Wire MOSFET) is expected to solve the problem of short-channel effect and grid leakage current.On the one hand; Channel thickness among the NWFET and width are all less, make grid more approach the various piece of raceway groove, help enhance transistor grid modulation capability; And most of transistors all adopt and enclose the grid structure; Grid is modulated raceway groove from a plurality of directions, has further strengthened the modulation capability of grid, improves the subthreshold value characteristic.Therefore, NWFET can suppress short-channel effect well, makes transistor size be able to further dwindle.On the other hand, NWFET utilizes the rill road of self and encloses the grid structure and improve the grid modulation forces and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced impurity discrete distribution and Coulomb scattering in the raceway groove.For the 1-dimention nano wire channel, because quantum limitation effect, charge carrier so carrier transport receives surface scattering and channel laterally influence little, can obtain higher mobility away from surface distributed in the raceway groove.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Because Si material and technology are occupied dominant position in semi-conductor industry, compare the easier and current process compatible of the making of silicon nanowires field-effect transistor (Si-NWFET) with other materials.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of Si nano wire, top-down making mainly utilizes photoetching and etching technics, and making from bottom to top is mainly based on the gas-liquid-solid growth mechanism of metal catalytic, in the growth course with catalyst granules as nucleating point.At present, the silicon nanowires of process route preparation from bottom to top not too is fit to the preparation of Si-NWFET owing to its randomness, and the Si-NW in the therefore present silicon nanowires field-effect transistor mainly is through top-down process route preparation.
A kind of process that approach from top to bottom realizes the bulk silicon nano line structure of passing through based on body silicon that application number is 200710098812.4 disclosure of the Invention has effectively suppressed the self-heating effect of device.A kind of MOSFET preparation method based on silicon nanowires is disclosed in the paper " Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon " (based on the preparation and the characteristic of enclosing grid shape silicon nanowires of body silicon); But along with dwindling of silicon nanowires sectional area; The current driving ability of device can receive the restriction of nano wire sectional area; Make the application of Si-NWFET in simulation or radio circuit be restricted; Therefore, the someone begins one's study and adopts many nano wires as transporting raceway groove, to address this problem.
Proposed in the paper " Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MO SFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching " (mobility strengthens phenomenon in strained silicon in the Donna rice noodles raceway groove that is formed by the hydrogen hot corrosion and the germanium silicon 3 D field-effect transistor) that a kind of many integrated nano wires conducts transport the NWFET device of passage based on strained silicon and germanium silicon; But, cause its integration density to have a greatly reduced quality because the Donna rice noodles channel structure in the device is laterally preparation.
In the paper " Vertically Stacked S iGe Nanowire Array Channel CMO S Transistors " (arrangement of vertical stacking formula germanium silicon nanowires in the CMOS transistor channel) a kind of vertical method for preparing silicon nanowires has been proposed; Make the Si-NWFET device at vertical integrated many silicon nanowires; Thereby make the current driving ability of device increase exponentially; Integration density is unaffected simultaneously, has so not only kept the advantage of planar structure FET but also has strengthened the grid modulation capability.
Its process is on SOI (silicon-on-insulator), alternately grow germanium or germanium silicon layer and silicon layer; And definition fin-shaped (Fin) structure; Then carry out 750 ℃ of dry-oxygen oxidations; Because the germanium silicon layer has faster oxidation rate so that germanium silicon layer oxidized fully than silicon layer, germanium gets into contiguous silicon surface and forms germanium-silicon alloy in the oxidizing process, erodes and obtains three-dimensional pile up, silicon nanowires that the surface is wrapped with germanium-silicon alloy behind the oxidized fully germanium silicon layer.Carry out thermal oxidation then, form Si on the Si-NW surface
1-XGe
XO
2As grid oxic horizon, unformed silicon of deposit or polysilicon form grid through photoetching and etching at last again.
This method can realize vertical stack type silicon nanowires field-effect transistor structure, but has a shortcoming: in germanium silicon layer oxidizing process, germanium can be concentrated to the surface of silicon layer, removes SiO
2After, be wrapped with the germanium-silicon alloy after one deck concentrates on the Si-NW surface.Because germanium dioxide is water-soluble, makes subsequent technique face huge inconvenience, in addition, the permittivity ratio silicon dioxide of germanium dioxide is little, and the interfacial state of germanium dioxide and silicon is bigger, is not suitable for the gate oxide as MOSFET.
Summary of the invention
It is a kind of based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI that the present invention provides, can effectively control gate profile and device electrically, increase the integrated level of field-effect transistor, and realize conventional gate oxidation process.
Provide based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI for solving the problems of the technologies described above the present invention, comprising:
SOI is provided substrate, and said SOI substrate comprises silicon lining, insulator layer and top layer silicon from the bottom to top successively;
Said SOI substrate surface is handled, the top layer of said SOI substrate is converted into initial germanium silicon layer;
On said SOI substrate, alternately form silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and follow-up germanium silicon layer constitute the germanium silicon layer jointly;
To said germanium silicon layer and silicon layer etching processing, form the fin-shaped active area, remaining areas is as source-drain area;
In said fin-shaped active area, form silicon nanowires, said silicon nanowires three-dimensional array type vertical stack;
Outside the fin-shaped active area, form the spacer medium layer and source-drain area is carried out the ion injection;
Form grid on the SOI substrate in the fin-shaped active area.
Preferable, said SOI substrate surface to be handled, the step that said SOI substrate top layer is converted into initial germanium silicon layer comprises: deposit a germanium layer or germanium silicon layer at said SOI substrate surface; To said germanium layer or germanium silicon layer oxidation processes, in said germanium layer or the germanium silicon layer germanium oxidation concentrate with said SOI substrate top layer in silicon form initial germanium silicon layer, the upper surface of said initial germanium silicon layer is SiO
2Layer; Wet method is removed said SiO
2Layer.
Preferable, said silicon layer is at least one deck, and said germanium silicon layer manys one deck than silicon layer.
Preferable, the diameter of said silicon nanowires is between 1 nanometer～1 micron.
Preferable, the cross sectional shape of said silicon nanowires is circular, horizontal track shape or vertical track shape.
Preferable, before said surface of silicon nanowires forms grid oxic horizon, also comprise: said silicon nanowires is carried out thermal oxidation; Etch away the silicon dioxide that said thermal oxidation forms.
Preferable, the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
Preferable, said high K medium is HfO
2, Al
2O
3, ZrO
2In a kind of or its combination in any.
Preferable, the material of said grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
Preferable, the material of said spacer medium layer is a silicon dioxide.
Preferable, said etching adopts time normal pressure chemical gas phase etching method.
Preferable, said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, and wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
Compared with prior art, grid type silicon nanowires field-effect transistor structure has the following advantages behind the three-dimensional array type of the present invention:
1,, effectively increased the isolation effect between grid and the SOI substrate based on the SOI substrate;
2, forming the gate oxidation layer process at surface of silicon nanowires is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
3, form grid at the fin-shaped active area, the profile of control grid, thus make active area and gate upper surface at same horizontal plane, be beneficial to follow-up contact hole technology;
4, grid type silicon nanowire structure is come design of Si nano-wire field effect transistor (Si-NWFET) structure behind the employing three-dimensional array type, and the nanometer number of lines increases, and the current driving ability of device increases;
5, grid is formed on after injection of source-drain area ion and the annealing process step, promptly adopts the back grid technology, is beneficial to the electrical control of gate profile and device.
Description of drawings
Fig. 1 for SOI substrate X-X ' in the present invention's one specific embodiment to generalized section;
Fig. 2 for deposition germanium layer or germanium silicon layer in the present invention's one specific embodiment after X-X ' to generalized section;
Fig. 3 for germanium layer in the present invention's one specific embodiment or the oxidation of germanium silicon layer after X-X ' to generalized section;
Fig. 4 for X-X ' after removing silicon dioxide in the present invention's one specific embodiment to generalized section;
Fig. 5 for alternating deposit silicon layer in the present invention's one specific embodiment and follow-up germanium silicon layer after X-X ' to generalized section;
Fig. 6 when raceway groove being carried out ion implantation technology in the present invention's one specific embodiment X-X ' to generalized section;
Fig. 7 is for forming Y-Y ' behind the fin-shaped active area in the present invention's one specific embodiment to generalized section;
Fig. 8 A～8B be respectively X-X ' that etching in the present invention's one specific embodiment removes device behind the germanium silicon layer to and Y-Y ' to generalized section;
Fig. 8 C is for forming the schematic perspective view of device behind the silicon nanowires in the present invention's one specific embodiment;
Fig. 9 is silicon nanowires cross sectional shape sketch map in the present invention's one specific embodiment;
Figure 10 A～10B for deposit dielectric layer technology in the present invention's one specific embodiment after the X-X ' of device to generalized section and stereogram;
Figure 11 A～11B be respectively in the present invention's one specific embodiment remove behind the unnecessary spacer medium layer device X-X ' to and Y-Y ' to generalized section;
Figure 12 injects back device X-X ' to generalized section for source-drain area ion in the present invention's one specific embodiment;
Figure 13 A～13B be respectively in the present invention's one specific embodiment remove the outer unnecessary spacer medium layer of fin-shaped active area form behind the grid groove device X-X ' to and Y-Y ' to generalized section;
Device X-X ' was to generalized section and schematic perspective view after Figure 14 A～14B was respectively and deposits grid oxic horizon in the present invention's one specific embodiment;
Figure 15 A～15B be respectively in the present invention's one specific embodiment form behind the grid material device X-X ' to and Y-Y ' to generalized section;
Figure 16 A～16C for remove in the present invention's one specific embodiment behind the unnecessary grid material device X-X ' to and Y-Y ' to generalized section, and schematic perspective view;
Figure 17 A～17B for autoregistration silicon, germanium silicon metal alloy (Salicidation) technology in the present invention's one specific embodiment after device X-X ' to and Y-Y ' to generalized section;
Figure 18 is silicon nanowires field-effect transistor perspective view in the present invention's one specific embodiment;
Figure 19 is silicon nanowires field-effect transistor schematic top plan view in the present invention's one specific embodiment.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
At first, please with reference to Figure 19, for clearer description present embodiment, the length direction of the silicon nanowires of definition fin-shaped active area or follow-up formation is X-X ' to, X-X ' to running through grid and source-drain area, perpendicular to X-X ' to be Y-Y ' to.The manufacture method based on the three-dimensional array type Si-NWFET of SOI below in conjunction with the detailed description one embodiment of the invention of Fig. 1 to 19 specifically comprises:
Please with reference to Fig. 1, SOI is provided substrate, the bottom of SOI substrate is the silicon lining 11 that is used to provide mechanical support; Upwards be followed successively by insulator layer and top layer, the present invention adopts oxygen buried layer 12 (BOX) as insulator layer, silicon layer 13; The top layer of SOI just, the silicon in the top layer is monocrystalline silicon;
Then, said SOI substrate surface is handled, the top layer of said SOI substrate is converted into initial germanium silicon layer 15 '; Embodiment comprises: at first, please with reference to Fig. 2, form a germanium layer 14 (germanium layer can be substituted by the germanium silicon layer) at substrate surface; Then, please with reference to Fig. 3, the SOI substrate surface is carried out oxidation processes; Germanium layer 14 is seeped in the silicon layer 13 because oxidation concentrates; Form initial germanium silicon layer 15 ', the silicon of initial germanium silicon layer 15 ' upper surface is oxidized, forms silicon dioxide layer (SiO
2) 16; Then, please with reference to Fig. 4, adopt wet etching to remove the silicon dioxide layer 16 of SOI substrate surface, at this moment, the top layer of SOI substrate is converted into initial germanium silicon layer 15 ' by silicon layer 13.
Then,, alternately form silicon layer 13 and follow-up germanium silicon layer 15 at substrate surface please with reference to Fig. 5 ", epitaxial growth silicon layer 13 on substrate at first; the follow-up germanium silicon layer 15 of epitaxial growth again ", be convenient the description, with initial germanium silicon layer 15 ' and follow-up germanium silicon layer 15 " be referred to as germanium silicon layer 15; by that analogy, wherein the number of silicon layer 13 is at least one deck, and germanium silicon layer 15 is than silicon layer one deck more than 13; promptly, and the below is initial germanium silicon layer 15 ', the top be follow-up germanium silicon layer 15 ".The present invention is an example with three layers silicon layer 13.
Please with reference to Fig. 6; Channel region to the SOI substrate carries out the ion injection, and ion carries out photoetching process before injecting; Make photoresist 20 cover the zone that is used for follow-up formation source electrode 203 (please with reference to Figure 19) and drain electrode 204 (please with reference to Figure 19), ion is removed photoresist 20 after injecting and accomplishing.Need to prove that this step is an optional step, can omit under the situation that device electrically requires to allow.
Please with reference to Fig. 7, to germanium silicon layer 15 and silicon layer 13 etching processing, form fin-shaped active area 201 (please with reference to Figure 19), fin-shaped active area 201 be a three-dimensional array type, remaining areas is as source-drain area, i.e. the source electrode 203 and 204 zones that drain.Optical lithography or electron beam lithography be can adopt, fin-shaped active area unnecessary germanium silicon layer 15 and silicon layer 13 etched away on every side, until exposing oxygen buried layer 12 surfaces.
Then, please with reference to Fig. 8 A～8B, in said fin-shaped active area, form silicon nanowires 131, said silicon nanowires 131 three-dimensional array types pile up; Be specially, selective etch is removed the germanium silicon layer 15 in the fin-shaped active area 201, and is optional, utilizes time normal pressure chemical gas phase etching method to carry out selective etch, can adopt the H under 600～800 degrees centigrade
2With the HCL mist, wherein the dividing potential drop of HCL is greater than 300Torr, till the germanium silicon layer 15 of selective etch step in fin-shaped active area 201 all removed;
Then, fin-shaped active area 201, substrate, source electrode 203 and 204 region surface that drain are carried out oxidation, the controlled oxidation time, utilize wet processing to remove the SiO on fin-shaped active area 201 and substrate and source and drain areas surface
2Thereby, form silicon nanowires 202.Further, if described thermal oxidation is furnace oxidation (FurnaceOxidation), then the oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), then the oxidization time scope is 1 second to 30 minutes.Remove the silicon dioxide that above-mentioned steps forms through wet processing on silicon nanowires 131 and oxygen buried layer 12 and source-drain area surface then.Silicon nanowires 131 diameters that form at last are between 1 nanometer～1 micron.
Because the thickness and fin-shaped active area 201 lateral dimensions of silicon layer 13 vary in size; The cross sectional shape of silicon nanowires 202 is also different; Please with reference to Fig. 9; The cross sectional shape of silicon nanowires 202 comprises circle 301, and laterally track shape 302 and vertical track shape 303 preferred cross-sections of the present invention are shaped as circular 301 silicon nanowires 131.Through more advanced figure transfer technology, can more accurately control fin-shaped active area (Fin) physical dimension, thereby more help the Shape optimization of silicon nanowires 131 and the diameter of accurately controlling silicon nanowires 131.
Please, outside the fin-shaped active area, form spacer medium layer 17 with reference to Figure 10 A～13B; Be specially; Shown in Figure 10 A～10B, the SOI substrate in the fin-shaped active area, the source electrode 203 and the 204 region surface deposit dielectric layers 17 that drain; Then; Please with reference to Figure 11 A～11B, remove fin-shaped active area 201, source electrode 203 and the unnecessary spacer medium layer 17 of 204 region surface that drain, make the spacer medium layer 17 after the etching be in same horizontal plane with the source-drain electrode upper surface.Spacer medium layer 17 among the present invention is SiO
2
Please with reference to Figure 12, carry out the source-drain area ion implantation technology, be specially: at first photoetching process makes photoresist 20 ' covering source electrode 203 and drain electrode 204 zones with exterior portions; Then, carry out ion implantation technology to dissimilar MOS transistors; Finally, remove photoresist 20 ' and source-drain area annealed.
Please with reference to Figure 13 A～13B, photoetching and selective etch are removed unnecessary spacer medium layer 17 between the source-drain area, form gate trench, and said gate trench is used for follow-up formation grid 202.
Please with reference to Figure 14 A～14B, silicon nanowires 131 surfaces in fin-shaped active area 201 form grid oxic horizon 18; Need to prove that the grid oxic horizon material of the routine that grid oxic horizon 18 adopts comprises: furnace oxidation, chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD), the SiO that forms of rapid thermal oxidation or ald
2Or the high K medium layer (high dielectric radio medium) of SiON (silicon oxynitride) and employing technique for atomic layer deposition deposition, SiON need be under the nitrogen atmosphere; Because the existence of the oxygen buried layer 12 among grid oxic horizon 18 and the SOI makes subsequent gate 202 better with the isolation effect of SOI substrate.
Then, please with reference to Figure 15 A～17B, form grid 205 at fin-shaped active area 201; At first, please with reference to Figure 15 A～15B, in fin-shaped active area 201, source electrode 203 and the 204 region surface deposition of gate material 19 that drain; Grid material 19 can be polysilicon; Amorphous silicon, metal or its combination, wherein metal is preferably the metallic compound of aluminium, titanium or tantalum.
Please with reference to Figure 16 A～16C; Adopt cmp to remove fin-shaped active area 201, source electrode 203 and the unnecessary grid material 19 of 204 region surface that drain; Form grid 202; The profile of control grid 202, thus make source-drain area and grid 202 upper surfaces at same horizontal plane, be beneficial to follow-up contact hole technology.
At last; Please with reference to Figure 17 A～18; Autoregistration alloy (Salicidation) technology forms silicon, germanium silicon metal alloy layer, and draws each port of CMOSFET through the metal interconnected technology in road, back; Said port comprises drain electrode port 22, gate port 23 and source electrode port 24, and source electrode 203, grid 202, drain electrode 204 region surface are coated with silicon alloy 21.
Finally, please refer to Figure 18 and Figure 19, it is schematic perspective view and schematic top plan view based on grid type Si-NWFET behind the three-dimensional array type of SOI after last the completion.
In sum, compared with prior art, three-dimensional array type silicon nanowires field-effect transistor structure of the present invention has the following advantages:
1,, effectively increased the isolation effect between grid and the SOI substrate based on the SOI substrate;
2, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
3, form grid at the fin-shaped active area, the profile of control grid, thus make active area and gate upper surface at same horizontal plane, be beneficial to follow-up contact hole technology;
4, grid type silicon nanowire structure is come design of Si nano-wire field effect transistor (Si-NWFET) structure behind the employing three-dimensional array type, makes the nanometer number of lines increase, and the device current driving force increases exponentially.
5, grid is formed on after injection of source-drain area ion and the annealing process step, promptly adopts the back grid technology, is beneficial to the electrical control of gate profile and device.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (12)
1. one kind based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI, comprising:
SOI is provided substrate, and said SOI substrate comprises silicon lining, insulator layer and top layer silicon from the bottom to top successively;
Said SOI substrate surface is handled, said SOI substrate top layer silicon is converted into initial germanium silicon layer;
On said SOI substrate, alternately form silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and follow-up germanium silicon layer constitute the germanium silicon layer jointly;
To said germanium silicon layer and silicon layer etching processing, form the fin-shaped active area, said fin-shaped active area three-dimensional array type piles up, and remaining areas is as source-drain area;
In said fin-shaped active area, form silicon nanowires, said silicon nanowires three-dimensional array type piles up;
Form grid oxic horizon at said surface of silicon nanowires;
Outside the fin-shaped active area, form the spacer medium layer and source-drain area is carried out ion injection and annealing process;
Form grid on the SOI substrate in the fin-shaped active area.
2. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI said SOI substrate surface is handled, and the step that said SOI substrate top layer silicon is converted into initial germanium silicon layer comprises:
Deposit a germanium layer or germanium silicon layer at said SOI substrate surface;
To said germanium layer or germanium silicon layer oxidation processes, in said germanium layer or the germanium silicon layer germanium oxidation concentrate with said SOI substrate top layer in silicon form initial germanium silicon layer, the upper surface of said initial germanium silicon layer is SiO
2Layer;
Wet method is removed said SiO
2Layer.
3. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI said silicon layer is at least one deck, said germanium silicon layer manys one deck than silicon layer.
4. as claimed in claim 1ly it is characterized in that the diameter of said silicon nanowires is between 1 nanometer～1 micron based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI.
5. as claimed in claim 1ly it is characterized in that the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertical track shape based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI.
6. as claimed in claim 1ly it is characterized in that, before said surface of silicon nanowires forms grid oxic horizon, also comprise based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI:
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
7. as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI, it is characterized in that the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
8. as claimed in claim 7 based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI, it is characterized in that said high K medium is HfO
2, Al
2O
3, ZrO
2In a kind of or its combination in any.
9. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI the material of said grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
10. as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI, it is characterized in that the material of said spacer medium layer is a silicon dioxide.
11. as claimed in claim 1ly it is characterized in that said etching adopts time normal pressure chemical gas phase etching method based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI.
12. it is as claimed in claim 11 based on grid type Si-NWFET manufacturing approach behind the three-dimensional array type of SOI; It is characterized in that; Said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body; Wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
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| CN108074983A (en) * | 2016-11-18 | 2018-05-25 | 台湾积体电路制造股份有限公司 | Multiple gate semiconductor device and its manufacturing method |
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