CN102623321B - Manufacture method of longitudinal stacking type rear-grid type SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon - Google Patents
Manufacture method of longitudinal stacking type rear-grid type SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon Download PDFInfo
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Abstract
The invention discloses a manufacture method of a longitudinal stacking type rear-grid type SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon. The manufacture method comprises the following steps of: providing a bulk-silicon substrate, and growing SiGe layers and Si layers on the bulk-silicon substrate alternatively; photoetching and etching the SiGe layers and the Si layers, forming a fin-shaped active region and using the remaining SiGe layers and the remaining Si layers as source-drain regions; removing the SiGe layers in the fin-shaped active region by selective etching, and forming silicon nano wires which are longitudinally stacked; forming an isolating dielectric layer on the silicon substrate among the source-drain regions; photoetching and etching the isolating dielectric layer and forming a grid groove; forming a grid oxidation layer on the silicon nanowires; and forming a grid in the grid groove. According to the manufacture method disclosed by the invention, the adoption of the grid-last process is beneficial to control of the profile of the grid and the electrical property of a device; the conventional grid oxidation layer is adopted; and the longitudinal stacking of the silicon nanowires is beneficial to increase of the integration of the device and the current driving capability of the device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of endwise piling stacked silicon nanowires field-effect transistor (SiNWFET) preparation method based on body silicon.
Background technology
In prior art, improve the operating rate of chip by the size reducing transistor and integrated level, reduction chip power-consumption density are that microelectronics industry develops the target pursued always.In in the past 40 years, microelectronics industry development follows Moore's Law always.Current, the physical gate of field-effect transistor is long close to 20nm, gate medium also only has several oxygen atom thickness, improve performance by the size reducing conventional field effect transistor and faced some difficulties, this is mainly because short-channel effect and grid leakage current make the switch performance of transistor degenerate under small size.
Nano-wire field effect transistor (Nanowire MOSFET, NWFET) is expected to address this problem.On the one hand, little channel thickness and width make the various piece of grid closer to raceway groove of nano-wire field effect transistor, contribute to the enhancing of transistor gate modulation capability, and their most employings enclose grid structure, grid is modulated from multiple directions raceway groove, can enhanced modulation ability further, improve Sub-Threshold Characteristic.Therefore, nano-wire field effect transistor can suppress short-channel effect well, and transistor size is reduced further.On the other hand, nano-wire field effect transistor utilize self rill road and enclose grid structure improve grid modulation power and suppress short-channel effect, alleviate the requirement of thinning grid medium thickness, be expected to reduce grid leakage current.In addition, nanowire channel can undope, and decreases the discrete distribution of impurity in raceway groove and Coulomb scattering.For 1-dimention nano wire channel, due to quantum limitation effect, raceway groove carriers away from surface distributed, therefore carrier transport by surface scattering and channel laterally electric field influence little, higher mobility can be obtained.Based on above advantage, nano-wire field effect transistor more and more receives the concern of scientific research personnel.Because silicon materials and technique occupy dominant position in the semiconductor industry, compared with other materials, the making of silicon nanowires field-effect transistor (SiNWFET) is easier and current process is compatible.
The critical process of nano-wire field effect transistor is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of silicon nanowires, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technique, the latter mainly based on gas-liquid-solid (VLS) growth mechanism of metal catalytic, using catalyst granules as nucleating point in growth course.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of silicon nanowires field-effect transistor due to its randomness, the silicon nanowires in therefore current silicon nanowires field-effect transistor is mainly prepared by top-down process route.
At present, field-effect transistor (MOSFET) its preparation process research based on single silicon nanowires is more popular, if application number is 200710098812.4, denomination of invention is the Chinese patent of " a kind of preparation method of bulk silicon nano line transistor device ", disclose a kind of process being realized bulk silicon nano line structure by top-down approach based on body silicon, because it is based on the process characteristic of body silicon, can the self-heating effect of effective suppression device.
But along with reducing of silicon nanowires sectional area, the current driving ability of device can be subject to the restriction of nano wire sectional area, the application of silicon nanowires field-effect transistor in simulation or radio circuit is restricted, therefore, someone begins one's study and adopts many nano wires as transporting raceway groove, to solve this problem.But because many nanowire channel structures are laterally preparations, its integration density will be had a greatly reduced quality.
The people such as W.W.Fang are at IEEE ELECTRON DEVICE LETTERS, VOL.28, NO.3, a kind of method that longitudinal direction prepares silicon nanowires is proposed in the paper " Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors " that MARCH 2007 delivers, make silicon nanowires FET device at Top-down design many silicon nanowires, thus the current driving ability of device is increased exponentially, integration density is unaffected simultaneously.Both the advantage of planar structure field-effect transistor (FET) can have been kept in turn enhance grid modulation ability.Its process is at upper alternating growth (Ge/Si Ge)/Si/ (the Ge/SiGe)/Si layer of SOI (Silicon on Insulator), and define fin-shaped (Fin) structure thereon, then 750 DEG C of dry-oxygen oxidations are carried out, because SiGe layer has oxidation rate so that SiGe layer faster completely oxidized compared with Si layer, in oxidizing process, Ge enters contiguous Si layer surface and forms SiGe alloy, obtains three-dimensional that pile up, that surface is wrapped with SiGe alloy Si nano wire after eroding completely oxidized SiGe layer.Then carry out thermal oxidation, form Si on silicon nanowires (SiNW) surface
1-Xge
xo
2as grid oxic horizon, the more unformed silicon of deposit or polysilicon, form grid finally by chemical etching.The method can realize endwise piling stack-type silicon nanowires field-effect transistor structure, but there is a shortcoming: when in SiGe layer oxidizing process, Ge can be concentrated to the surface of Si layer, removes SiO
2after, surface of silicon nanowires be wrapped with one deck concentrate after SiGe alloy.Due to GeO
2water-soluble, it makes subsequent technique face huge inconvenience, in addition, and GeO
2dielectric constant comparatively SiO
2little, GeO
2comparatively large with the interfacial state of Si, be not suitable as the gate oxide of field-effect transistor (FET).
Summary of the invention
The object of the present invention is to provide a kind of based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, can effectively control gate profile and device electric, the integrated level of effective increase SiNWFET and device current driving force, and realize the regular grid oxide layer structure of silicon nanowires field-effect transistor.
For solving the problems of the technologies described above, the invention provides a kind of based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, comprising the following steps:
There is provided one silicon substrate, on described body silicon substrate, alternating growth has SiGe layer and Si layer;
Carry out photoetching and etching to described SiGe layer and Si layer, form fin-shaped active area, remaining SiGe layer and Si layer are as source-drain area;
Remove the SiGe layer in described fin-shaped active area by selective etch, form silicon nanowires, described silicon nanowires vertical stack;
Body silicon substrate between described source-drain area forms spacer medium layer;
Photoetching and etching are carried out to described spacer medium layer, forms gate trench;
Described silicon nanowires forms grid oxic horizon;
Grid is formed in described gate trench.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, one deck nearest apart from described body silicon substrate is SiGe layer, and distance body silicon substrate one deck farthest is also SiGe layer.
Optionally, described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, before photoetching and etching are carried out to described SiGe layer and Si layer, ion implantation is carried out to the region between described source-drain area.
Optionally, described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, before described SiGe layer and Si layer being carried out to photoetching and etching, ion implantation is carried out to described source-drain area.
Optionally, described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, after the body silicon substrate between described source-drain area forms spacer medium layer, ion implantation is carried out to described source-drain area.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, described selective etch adopts time atmospheric chemical vapor etching method.
Optionally, described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, described time atmospheric chemical vapor etching method adopts hydrogen and chlorine hydride mixed gas body, wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 DEG C ~ 800 DEG C, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, described silicon nanowires diameter is between 1 nanometer ~ 1 micron.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, the cross sectional shape of described silicon nanowires is circular, horizontal track type or longitudinal track type.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, before the body silicon substrate between described source-drain area forms spacer medium layer, also comprise:
Thermal oxidation is carried out to described silicon nanowires;
Etch away the silicon dioxide that described thermal oxidation is formed.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, the material of described grid oxic horizon is silicon dioxide, silicon oxynitride or high-k dielectric layer.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, described high-K dielectric layer is HfO
2, Al
2o
3, ZrO
2in one or its combination in any.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, the material of described grid is one in polysilicon, amorphous silicon, metal or its combination in any.
Described based on the endwise piling stacked of body silicon after in grid-type SiNWFET preparation method, the material of described spacer medium layer is silicon dioxide.
After the present invention is based on the endwise piling stacked of body silicon, grid-type silicon nanowires field-effect transistor structure has the following advantages:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area is connected with body silicon substrate, and the amount of heat that device produces in the course of the work effectively can be passed to body silicon substrate by source-drain area and shed, thus without self-heating effect.
2, finally carrying out grid formation process, is post tensioned unbonded prestressed concrete technique, thus is conducive to gate profile control and device electric control, and without side wall technique, simplifies flow process.
3, on silicon nanowires, form gate oxidation layer process is independently carry out, thus can adopt conventional grid oxic horizon, as silicon dioxide.
4, adopt endwise piling stacked silicon nanowire structure to design silicon nanowires field-effect transistor (SiNWFET) structure, endwise piling stacked structure makes device integration increase, and nano wire number increases, thus device current driving force is also increased.
Accompanying drawing explanation
Fig. 1 is based on grid-type SiNWFET preparation method flow chart after the endwise piling stacked of body silicon in one embodiment of the invention;
Fig. 2 is that the X-X ' of body silicon substrate in one embodiment of the invention is to generalized section;
Fig. 3 carries out the X-X ' of ion implantation technology to generalized section to the region between source-drain area in one embodiment of the invention;
Fig. 4 a and Fig. 4 b to be respectively in one embodiment of the invention fin-shaped active area X-X ' to and Y-Y ' to generalized section;
Fin-shaped active area X-X ' after Fig. 5 a and Fig. 5 b is respectively in one embodiment of the invention and removes SiGe layer to and Y-Y ' to generalized section;
Fig. 6 is the schematic perspective view forming nano wire in one embodiment of the invention;
Fig. 7 is the cross sectional shape schematic diagram of silicon nanowires in one embodiment of the invention;
Fig. 8 a and Fig. 8 b be to deposit in one embodiment of the invention after spacer medium X-X ' to and Y-Y ' generalized section;
Fig. 9 a and Fig. 9 b be respectively in one embodiment of the invention to spacer medium carry out the X-X ' after cmp to and Y-Y ' to generalized section;
Figure 10 carries out the X-X ' of ion implantation technology to generalized section to source-drain area in one embodiment of the invention;
Figure 11 a and Figure 11 b be respectively in one embodiment of the invention the X-X ' after forming gate trench to and Y-Y ' to generalized section;
Figure 12 is the schematic perspective view after forming gate trench in one embodiment of the invention;
Figure 13 a and Figure 13 b be respectively in one embodiment of the invention the X-X ' after forming grid oxic horizon to and Y-Y ' to generalized section;
Figure 14 a and Figure 14 b be respectively X-X ' in one embodiment of the invention after deposition of gate material to and Y-Y ' to generalized section;
Figure 15 a and Figure 15 b be respectively in one embodiment of the invention to grid material carry out the X-X ' after cmp to and Y-Y ' to generalized section;
Figure 16 be carry out in one embodiment of the invention autocollimation silicon, germanium silicon metal alloy (Salicidation) technique X-X ' to generalized section;
Figure 17 a and Figure 17 b be respectively in one embodiment of the invention by the X-X ' after the metal interconnected technique in rear road to and Y-Y ' to generalized section;
Figure 18 is the schematic perspective view after forming source electrode connector, gate plug and drain plug in one embodiment of the invention;
Figure 19 is endwise piling stacked silicon nanowires field-effect transistor structure schematic top plan view in one embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First, as shown in figure 19, in order to clearer description the present embodiment, the length direction of silicon nanowires 6 of definition fin-shaped active area 5 or follow-up formation is X-X ' to, X-X ' to running through grid 10 and source-drain area 15, perpendicular to X-X ' to for Y-Y ' to.Below in conjunction with the manufacture method based on grid-type SiNWFET after the endwise piling stacked of body silicon of the detailed description one embodiment of the invention of Fig. 1 to Figure 19.
As shown in Figure 1, the manufacture method based on grid-type SiNWFET after the endwise piling stacked of body silicon of one embodiment of the invention, comprises the steps:
As shown in Figure 2, one silicon substrate 1 is provided, on body silicon substrate 1, alternating growth has SiGe layer 3 and Si layer 2, suppose that the quantity of Si layer 2 is n layer, then the quantity of SiGe layer 3 is n+1 layer, wherein, n >=1, that is, (bottom) epitaxial loayer that distance body silicon substrate 1 is nearest is SiGe layer 3, and distance body silicon substrate 1 (the top) epitaxial loayer farthest is also SiGe layer 3.Owing to the present invention is based on body silicon, silicon nanowires field-effect transistor source-drain area 15 is connected with body silicon substrate 1, and the amount of heat that device produces in the course of the work effectively can be passed to body silicon substrate 1 by source-drain area 15 and shed, thus without self-heating effect.In the present embodiment, for alternating growth four layers of SiGe layer and three layers of Si layer.
As shown in Figure 3, ion implantation is carried out to the region between source-drain area 15, be and adulterated in the channel region of field-effect transistor.Concrete, this step is by following process implementation: first in SiGe layer 3, form patterned photoresist layer 4 by photoetching (Photo) technique, then with patterned photoresist layer 4 for mask carries out ion implantation (Imp) technique, then, remove described patterned photoresist layer 4 (PR Strip), carry out trap annealing (Well Anneal) technique subsequently.It should be noted that, this step is optional step, can omit under requiring permission situation according to device electric.
As shown in Figs. 4a and 4b, carry out photoetching and etching to SiGe layer 3 and Si layer 2, form fin-shaped active area 5, remaining SiGe layer 3 and Si layer 2 are as source-drain area 15.Preferably, can adopt optical lithography (Photolithography) or electron beam lithography (electron beam lithography), etching runs through all epitaxial sige layer 3 and Si layer 2, until expose the surface of body silicon substrate 1.
As shown in figure 5a and 5b, the SiGe layer 3 in fin-shaped active area 5 is removed by selective etch; Preferably, utilize time atmospheric chemical vapor etching method to carry out selective etch, temperature can adopt 600 DEG C ~ 800 DEG C, and etching gas selects the mist of H2 and HCl, and wherein the dividing potential drop of HCl is greater than 300Torr.This selective etch step is till all etching away the SiGe layer 3 between the Si layer 2 along Y-Y ' direction, remaining Si layer 2 is as silicon nanowires 6, silicon nanowires 6 vertical stack, and SiGe layer 3 part in X-X ' direction is retained, using as source-drain area 15.Optionally, before this step, also first ion implantation technology can be carried out to source-drain area 15.
As shown in Figure 6, silicon nanowires 6 be optimized and subtract thin.This step can pass through thermal oxidation technology, is oxidized silicon nanowires 6, body silicon substrate 1 and source-drain area 15 surface.Further, if described thermal oxidation is furnace oxidation (Furnace Oxidation), then oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), then oxidization time scope is 1 second to 30 minutes.Then the silicon dioxide that formed on the surface at silicon nanowires 6, body silicon substrate 1 and source-drain area 15 of above-mentioned steps is removed by wet-etching technology.Silicon nanowires 6 diameter finally formed is between 1 nanometer ~ 1 micron.Be understandable that, vary in size according to the thickness of Si layer 2 and fin-shaped active area 5 lateral dimension, silicon nanowires 6 cross sectional shape also can be different, such as, silicon nanowires 6 cross sectional shape can be the circle as shown in the leftmost side in Fig. 7, the horizontal track type shown in centre or the longitudinal track type shown in the rightmost side.If by more advanced Graphic transitions technology, so more accurately can control fin-shaped active area 5 (Fin) physical dimension, thus be more conducive to the shape optimum of silicon nanowires 6 and subtract thin, and accurately can control the diameter of silicon nanowires 6.
As figures 8 a and 8 b show, the body silicon substrate 1 between SiGe layer 3 upper surface and source-drain area 15 of source-drain area 15 deposits spacer medium 7 ', and described spacer medium 7 ' is generally silicon dioxide.
As shown in figures 9 a and 9b, adopt chemical mechanical milling tech, remove unnecessary spacer medium 7 ', remaining spacer medium 7 ' is as spacer medium layer 7; And make the upper surface of spacer medium layer 7 and SiGe layer 3 in same level.The present invention generally adopts silicon dioxide as spacer medium layer 7, thus without the need to carrying out side wall technique.
As shown in Figure 10, with patterned photoresist layer 4 for mask, ion implantation technology is carried out to source-drain area 15; Concrete, this step is by following process implementation: first in SiGe layer 3 and spacer medium layer 7 upper surface, form patterned photoresist layer 4 by photoetching (Photo) technique, then with patterned photoresist layer 4 for mask carries out ion implantation (Imp) technique, then, remove described patterned photoresist layer 4 (PR Strip), carry out source-drain electrode annealing (S/D Anneal) technique subsequently.It should be noted that, this step can be carried out before the figure Shape definition of fin-shaped active area 5, also can carry out after cmp (CMP) at spacer medium 7 '.
As shown in Figure 11 a, Figure 11 b and Figure 12, photoetching and etching technics are carried out to spacer medium layer 7, form gate trench 8.Concrete, hard mask or photo-resistive mask can be adopted in described photoetching process.By photoetching and etching technics, the profile of control gate groove 8, thus be conducive to grid 10 profile and the device electric that control follow-up formation, and retain a spacer medium thin layer on the body silicon substrate 1 between source-drain area 15, as the separator between subsequent gate 10 and body silicon substrate 1.
As shown in figures 13a andb, silicon nanowires 6 forms grid oxic horizon 9, described grid oxic horizon 9 can be SiO
2, SiON or high-K dielectric layer, described high-K dielectric layer is such as HfO
2, Al
2o
3, ZrO
2in one or its combination in any.Generally oxidation technology is adopted in formation grid oxic horizon 9 step, described oxidation technology can adopt furnace oxidation (Furnace Oxidation), rapid thermal oxidation (RTO), chemical vapor deposition (Chemical Vapor Deposition, CVD) one in, to form silicon dioxide on silicon nanowires 6 surface, thus define conventional grid oxic horizon 9.Be understandable that, also can form SiON adding in nitrogen atmosphere situation; Or, also can adopt ald (ALD) deposition techniques high-K dielectric layer.
As shown in figure 14 a and 14b, deposition of gate material 10 ' in SiGe layer 3 upper surface and gate trench 8, described grid material 10 ' can be polysilicon, one in amorphous silicon, metal (being preferably the metallic compound of aluminium or titanium or tantalum) or its combination in any.
As Figure 15 a and as illustrated in fig. 15b, adopt chemical mechanical milling tech, remove unnecessary grid material 10 ', remaining grid material 10 ' is as grid 10; And make the upper surface of grid 10 and spacer medium layer 7 and SiGe layer 3 in same level.After source-drain area 15 carries out ion implantation and spacer medium layer 7 is formed, then carrying out the formation process of grid 10, is post tensioned unbonded prestressed concrete technique, thus is conducive to the control of grid 10 profile and device electric control.
As shown in figure 16, carry out autoregistration alloy (Salicidation) technique, form silicon, germanium silicon metal alloy layer 11.
As shown in Figure 17 a, 17b and 18, form source electrode connector 12, gate plug 13 and drain plug 14 by the metal interconnected technique in rear road, to draw the source electrode of field-effect transistor (FET), grid and drain electrode respectively.
Finally, please refer to Figure 18 and Figure 19, it is the schematic perspective view based on grid-type SiNWFET after the endwise piling stacked of body silicon after finally completing and schematic top plan view.
In sum, after the present invention is based on the endwise piling stacked of body silicon, grid-type silicon nanowires field-effect transistor structure has the following advantages:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area 15 is connected with body silicon substrate 1, and the amount of heat that device produces in the course of the work effectively can be passed to body silicon substrate 1 by source-drain area 15 and shed, thus without self-heating effect.
2, the ion implantation technology of source-drain area 15 has first been carried out, gate trench 8 is formed again in spacer medium layer 7, finally in gate trench 8, form grid 10, for post tensioned unbonded prestressed concrete technique, thus be conducive to the control of grid 10 profile and device electric control, and without side wall technique, simplify flow process, and make source-drain area 15 and spacer medium layer 7 and grid 10 upper surface in same level, be beneficial to subsequent touch hole technique.
3, on silicon nanowires 6, form grid oxic horizon 9 technique is independently carry out, thus can adopt conventional grid oxic horizon 9, as silicon dioxide;
4, adopt endwise piling stacked silicon nanowire structure to design silicon nanowires field-effect transistor (SiNWFET) structure, endwise piling stacked structure makes device integration increase, and nano wire number increases, thus device current driving force is also increased.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (13)
1., based on a grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, comprising:
There is provided one silicon substrate, on described body silicon substrate, alternating growth has SiGe layer and Si layer;
Carry out photoetching and etching to described SiGe layer and Si layer, form fin-shaped active area, remaining SiGe layer and Si layer are as source-drain area;
Remove the SiGe layer in described fin-shaped active area by selective etch, form silicon nanowires, described silicon nanowires vertical stack;
Thermal oxidation is carried out to described silicon nanowires;
Etch away the silicon dioxide that described thermal oxidation is formed;
Body silicon substrate between described source-drain area forms spacer medium layer;
Photoetching and etching are carried out to described spacer medium layer, forms gate trench;
Described silicon nanowires forms grid oxic horizon;
Grid is formed in described gate trench.
2. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, one deck nearest apart from described body silicon substrate is SiGe layer, and distance body silicon substrate one deck farthest is also SiGe layer.
3. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, before photoetching and etching are carried out to described SiGe layer and Si layer, ion implantation is carried out to the region between described source-drain area.
4. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, before photoetching and etching are carried out to described SiGe layer and Si layer, ion implantation is carried out to described source-drain area.
5. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, after the body silicon substrate between described source-drain area forms spacer medium layer, ion implantation is carried out to described source-drain area.
6. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, described selective etch adopts time atmospheric chemical vapor etching method.
7. as claimed in claim 6 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, described time atmospheric chemical vapor etching method adopts hydrogen and chlorine hydride mixed gas body, wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 DEG C ~ 800 DEG C, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
8. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, described silicon nanowires diameter is between 1 nanometer ~ 1 micron.
9. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, the cross sectional shape of described silicon nanowires is circle, horizontal track type or longitudinal track type.
10. as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, the material of described grid oxic horizon is silicon dioxide or high K dielectric.
11. is as claimed in claim 10 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, and it is characterized in that, described high-K dielectric layer is HfO
2, Al
2o
3, ZrO
2in one or its combination in any.
12. is as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, it is characterized in that, the material of described grid is one in polysilicon, amorphous silicon, metal or its combination in any.
13. is as claimed in claim 1 based on grid-type SiNWFET preparation method after the endwise piling stacked of body silicon, and it is characterized in that, the material of described spacer medium layer is silicon dioxide.
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| CN108231589B (en) * | 2016-12-09 | 2020-06-05 | Imec 非营利协会 | Formation of internal spacers in nanowire semiconductor devices |
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