CN103915316B - Stacked nanowire fabrication method - Google Patents
Stacked nanowire fabrication method Download PDFInfo
- Publication number
- CN103915316B CN103915316B CN201310007063.5A CN201310007063A CN103915316B CN 103915316 B CN103915316 B CN 103915316B CN 201310007063 A CN201310007063 A CN 201310007063A CN 103915316 B CN103915316 B CN 103915316B
- Authority
- CN
- China
- Prior art keywords
- groove
- nano wire
- substrate
- fin
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 238000004064 recycling Methods 0.000 claims 1
- 238000005260 corrosion Methods 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000001720 carbohydrates Chemical class 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000013268 sustained release Methods 0.000 description 1
- 239000012730 sustained-release form Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a stacked nanowire manufacturing method, which comprises the following steps: step a, forming a hard mask on a substrate; step b, anisotropically etching the substrate to form a first groove and a fin; step c, corroding the fins and the lower substrate by a wet method, and forming a second groove on the side surface of the first groove; repeating the steps b to c for multiple times to form a plurality of fins stacked up and down; and d, rounding the fins to form stacked nanowires. According to the manufacturing method of the stacked nanowire, the dry etching and the wet etching are combined, the high-precision stacked nanowire is formed by utilizing double internal cutting corrosion, the miniaturization of a device is facilitated, and the cost is reduced.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing methods, more particularly to a kind of manufacturing method stacking nano wire.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can inhibit short compared with traditional single grid body Si or SOI MOSFET
Channelling effect (SCE) and leakage cause induced barrier to reduce (DIBL) effect, have lower junction capacity, can realize that raceway groove is gently mixed
Miscellaneous, work function that can be by the way that metal gates are arranged can obtain about 2 times of driving current, reduce come adjusting threshold voltage
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.
In loopful in the manufacturing process of nano wire multi-gate device, it is known that a kind of method it is as follows：It is formed on a si substrate
Hard mask, using SF6The isotropic plasma of etching gas, which is dry-etched in hard mask lower substrate, to be formed in slightly
Recessed first groove, there are substrate materials to constitute fin structure between opposite first groove；Using high density CxF (carbon fluorine ratios
It is higher) plasma etching of etching gas, on substrate and first groove side wall forms passivation layer；SF again6Respectively to different
Property etching, remove substrate on passivation layer, leave the passivation layer of first groove madial wall；SF6Isotropic etching continues etching lining
Bottom forms second groove below first groove；And so on, form multiple grooves and fin structure；Between oxidation groove
Fin structure removes oxide, leaves nano-wire array.This method technology controlling and process is difficult, and nanowire density is smaller, consistency compared with
Difference.
Method known to another kind includes：It is formed epitaxially one after the other the overlapping epitaxial layer of Si and Ge/SiGe on soi substrates,
Hard mask layer is formed in top layer, etching forms grid lines, and selective etch removes the Ge/SiGe layers between i layers of adjacent S, stays
Lower Si nano wires.This method is limited to the bed boundarys Ge/SiGe poor performance, and process costs are high, it is difficult to universal.
In view of the trench fabrication methods in contrast simple process of Σ shape sections, as long as can relatively good control anisotropy quarter
Erosion, then be expected to form uniform, highdensity stacking nano wire.
Invention content
From the above mentioned, inexpensive, efficient nano wire manufacturing method can be stacked the purpose of the present invention is to provide a kind of.
For this purpose, the present invention provides a kind of stacking nano wire manufacturing methods, including：Step a is formed cover firmly on substrate
Mould；Step b, anisotropic etching substrate form first groove and fin；Step c, wet etching fin and lower substrate,
First groove side forms second groove；Wherein, step b to step c is repeated several times, forms multiple fins stacked on top of one another；Step
Rapid d, mellow and fullization fin form and stack nano wire.
Wherein, substrate is body Si or SOI.
Wherein, substrate is (100) crystal face.
Wherein, the anisotropic etching of step b is dry etching.Wherein, dry etching RIE.Wherein, etching gas packet
Include fluorine base gas.
Wherein, further include after step c, before step d：Step c1, anisotropic etching substrate form another group first
Groove and fin；Step c2, isotropic etching fin and lower substrate form third groove in first groove side；Its
In, step b, step c, step c1, step c2 is repeated several times, forms multiple fins stacked on top of one another.
Wherein, the first groove of formation has vertical sidewall.
Wherein, first groove side wall is (110) face, and substrate is (100) face.
Wherein, wet etching liquid includes TMAH.
Wherein, step d further comprises：Oxide layer is formed on fin surface；Removing oxide layer is removed, fin is exposed；In hydrogen
It anneals under atmosphere so that fin mellow and fullization forms and stack nano wire.
Wherein, first groove side wall is (110) face, and substrate is (100) face.
Wherein, second groove side wall is (111) face.
Wherein, third trenched side-wall is (110) face.
According to the stacking nano wire manufacturing method of the present invention, dry etching and wet etching are combined, dual inscribe is utilized
Corrosion forms high-precision and stacks nano wire, is conducive to device miniaturization, reduces cost.
Description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 to Fig. 8 is the cut-away view according to each step of manufacturing method of first embodiment of the invention；
Fig. 9 to Figure 15 is the sectional view according to each step of manufacturing method of second embodiment of the invention；
Figure 16 is the schematic flow chart according to first embodiment of the present invention manufacturing method；And
Figure 17 is the schematic flow chart according to second embodiment of the present invention manufacturing method.
Specific implementation mode
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect, disclosing can low cost, efficient stacking nano wire manufacturing method.It should be pointed out that similar reference numeral table
Show that similar structure, term use herein " first ", " second ", "upper", "lower" etc. can be used for modifying various devices
Structure or manufacturing process.These modifications do not imply that the space, secondary of modified device architecture or manufacturing process unless stated otherwise
Sequence or hierarchical relationship.
First, below with reference to the flow chart of Figure 16 and referring to figs. 1 to the diagrammatic cross-section of Fig. 8 come be described in detail according to
Each step of method, semi-conductor device manufacturing method of first embodiment of the invention.
As shown in Figure 1, providing substrate 1.Substrate 1 is needed according to device application and is reasonably selected, it may include monocrystalline silicon
(Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon
, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (SiGe) or compound semiconductor materials
(InSb) and carbon-based semiconductors such as graphene, SiC, carbon nanotube etc..Preferably, substrate 1 be body Si so as to CMOS works
Skill is compatible and is used to make large scale integrated circuit.It is highly preferred that substrate 1 is (100) crystal face.
As shown in Fig. 2, forming hard mask 2 on substrate 1.By LPCVD, PECVD, UHVCVD, HDPCVD, thermal oxide,
The conventional methods such as chemical oxidation, MBE, ALD, evaporation, sputtering form hard mask layer on substrate 1, and utilize already known processes light
Quarter/etching forms hard mask figure 2.The material of hard mask 2 can be silica, silicon nitride, silicon oxynitride and combinations thereof.
As shown in figure 3, etched substrate 1 forms first groove 1G, 1 remainder of substrate that 2 lower section of hard mask leaves is constituted
First fin 1F.Etching is preferably anisotropic etching, so that the side wall of first groove 1G is that (basic) is vertical.Anisotropy
Etching preferably fluorine base gas (such as carbon fluorine base gas CxHyFz, it be 0~8, z is 1~8, xyz three's numbers that wherein x, which is 1~4, y,
Magnitude relation meets so that above-mentioned chemical formula constitutes fluoro (saturation is either unsaturated) alkene or alkane；In addition can also be SF6、
NF3) plasma dry etch, in order to accurately control etching depth d by controlling etching conditionE, and then control final nanometer
Line height/thickness.Etching is so that the side wall of first groove 1G is (110) face, and 1 surface of substrate remains as (100) face.
As shown in figure 4, executing wet etching, fin 1F and substrate 1 are etched, the second ditch is formed in the sides first groove 1G
Slot 1G '.The corrosive liquid of wet etching is tetramethylammonium hydroxide (TMAH), etches the first fin 1F between first groove 1G,
(sides first groove 1G) forms second groove 1G ' in fin 1F.In wet etching course, (111) face of Si materials is rotten
It loses rate and is substantially less than (100) face and (110) face, therefore etching eventually terminates on (111) face.It in addition can be wet by controlling
The velocity and time of method corrosion so that the profile morphology of second groove 1G ' is substantially triangle.As shown in figure 4, in the present invention the
In one embodiment, second groove 1G ' does not make fin 1F break-through, but is connected there are a small amount of between opposite second groove
Part.Certainly, alternatively, second groove 1G ' can also break-through so that fin 1F and lower substrate (or follow-up fin) point
From.It is worth noting that, in the process, since side wall is (110) face, and substrate is (100) face, therefore TMAH is for side wall
Corrosion rate be slightly less than substrate do not exist so that second groove 1G ' bottom widths are more than top width namely groove endpoint
On vertical line.Subsequently to execute further technique makes second groove endpoint be distributed on vertical line.
As shown in figure 5, executing anisotropic etching, etched substrate 1 so that the substrate portions of fin 1F inclined downward side walls
It is etched to form another group of fin 1F ' with vertical sidewall, the groove between fin 1F ', which is then another group, has vertical sidewall
First groove 1G.Anisotropic etching can be above-mentioned dry etching, such as plasma etching or reactive ion are carved
It loses (RIE), the side wall for etching the fin 1F ' of formation is (110) crystal face, and substrate is still (100) crystal face.It is worth noting that, Fig. 4
The V-groove on 1 surface of middle substrate is still conformally formed in Figure 5, and the sloped sidewall of fin 1F section below is then etched
It is modified to vertical sidewall, therefore endpoint is finally distributed on a vertical line second groove 1G ' up and down.In this way, by each to same
Property the etching and blocked operation of anisotropic etching, Σ type profile grooves can be made to can be used for forming uniformly neat nanometer
Line stacks.
As shown in fig. 6, it is similar with technique shown in Fig. 4, wet etching is executed, continues to etch another group of fin 1F ', wherein
Form another group of second groove 1G '.Correspondingly, second groove 11G ' at this time up and down endpoint not on a vertical line.
As shown in fig. 7, it is similar with technique shown in Fig. 5, anisotropic etching is executed, is eliminated prominent below second groove 1G '
The part gone out so that another group of fin 1F ' has vertical sidewall.
As shown in figure 8, it is similar with technique shown in Fig. 4 or Fig. 6, TMAH wet etchings are executed, another group of fin 1F " is formed
And second groove 1G ".
Hereafter, subsequent technique processing can be carried out so that fin structure is thinned.Common method includes using thermal oxide, chemistry
The method of oxidation forms oxide layer (being not shown, such as silica) on fin structure 1F/1F '/surfaces 1F ", and makes remaining
Fin structure 1F/1F '/1F " constitutes nano wire 1NW.Preferably, it can further anneal in atmosphere of hydrogen so that remaining ground
Fin structure the 1F/1F '/surfaces 1F " mellow and fullization, forms circular nano wire 1NW.Then, the oxide layer for removing surface, leaves and receives
Rice noodles 1NW.Minimizing technology is, for example, that entire device wafer immerses HF bases corrosive liquid (dHF or dBOE (sustained release etching agent)), rotten
The oxide layer of etching off silicon material only leaves multiple nano wire 1NW and stacks the grid line array constituted.
Fig. 9 to Figure 15 show each step sectional view of process according to second embodiment of the invention, and Figure 17 shows for it
Meaning property flow chart.
It is similar or identical with Fig. 1 of embodiment 1 to Fig. 5 as shown in Fig. 9~Figure 13, form hard mask on substrate 1
2, anisotropic etching substrate 1 formed fin 1F and vertical sidewall first groove 1G, TMAH wet etching fin 1F and
Substrate 1 forms the second groove 1G ' of indent, and anisotropic etching fin 1F lower substrates make second groove 1G ' endpoints up and down
On vertical line, namely so that another group of fin 1F ' has vertical sidewall below fin 1F.Wherein, etching can shown in Figure 13
To be reactive ion etching (RIE), etching gas can be above-mentioned carbon fluorine base gas, (such as be reduced by adjusting gas mixing ratio
Fluorine content improves carbohydrate content and can improve isotropism, and anisotropy can be improved by improving fluorine content) so that RIE be it is each to
It is anisotropic.Remaining processing step is similar or identical, therefore repeats no more.
As different from Example 1, embodiment 2 is foring first group of fin 1F, first groove 1G and is modifying
Two groove 1G ' make its upper and lower side on vertical line after, be not the cycle as shown in FIG. 6 for continuing next TMAH wet etchings
Step, but as shown in figure 14, third groove 1G " is formed using isotropic RIE.It can be by adjusting gas mixing ratio
(such as reduction fluorine content, raising carbohydrate content can improve isotropism, and anisotropy can be improved by improving fluorine content) makes
This RIE is isotropism.It is worth noting that, although third groove 1G " profile morphologies are circular arc as shown in the figure, actually
On can not be all various rational shapes according to etching condition, such as semicircle (D types), large semicircle (c-type), ellipse, parabola,
Hyperbola etc. and combinations thereof.Third groove 1G " lower widths herein are still likely larger than or are equal to upper width, but can lead to
Adjustment RIE technological parameters are crossed so that finally to make that third groove 1G " is wide up and down.
As shown in figure 15, processing step shown in Fig. 9 to Figure 14 is repeated, etches to form multiple second using isotropism RIE
Groove 1G ' and multiple third groove 1G ".
Finally, it is referred to embodiment 1, continues subsequent technique, nano wire is completed and stacks.
According to the stacking nano wire manufacturing method of the present invention, dry etching and wet etching are combined, dual inscribe is utilized
Corrosion forms high-precision and stacks nano wire, is conducive to device miniaturization, reduces cost.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the preferred forms for realizing the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacturing method is by all embodiments including falling within the scope of the present invention.
Claims (11)
1. a kind of stacking nano wire manufacturing method, including：
Step a, forms hard mask on substrate；
Step b, anisotropic etching substrate form first groove and fin；
Step c, wet etching fin and lower substrate form the second groove of triangle, the second ditch in first groove side
Endpoint is not on the straight line perpendicular to substrate above and below slot；
Wherein, step b to step c is repeated several times, forms multiple fins stacked on top of one another, wherein the step b in recycling every time
Endpoint is distributed in a straight line perpendicular to substrate to the second groove of step c up and down in one cycle before anisotropic etching makes
On；
Step d, mellow and fullization fin form and stack nano wire.
2. stacking nano wire manufacturing method as claimed in claim 1, wherein substrate is body Si or SOI.
3. stacking nano wire manufacturing method as claimed in claim 1, wherein substrate is (100) crystal face.
4. stacking nano wire manufacturing method as claimed in claim 1, wherein the anisotropic etching of step b is dry etching.
5. stacking nano wire manufacturing method as claimed in claim 4, wherein dry etching RIE.
6. stacking nano wire manufacturing method as claimed in claim 5, wherein etching gas includes fluorine base gas.
7. stacking nano wire manufacturing method as claimed in claim 1, wherein further include after step c, before step d：Step c1,
Anisotropic etching substrate forms another group of first groove and fin；Step c2, isotropic etching fin and lower substrate,
Third groove is formed in first groove side；Wherein, step b, step c, step c1, step c2 is repeated several times, forms levels
Folded multiple fins.
8. stacking nano wire manufacturing method as claimed in claim 1, wherein the first groove of formation has vertical sidewall.
9. stacking nano wire manufacturing method as claimed in claim 6, wherein first groove side wall is (110) face, and substrate is (100)
Face.
10. stacking nano wire manufacturing method as claimed in claim 1, wherein wet etching liquid includes tetramethylammonium hydroxide.
11. stacking nano wire manufacturing method as claimed in claim 1, wherein step d further comprises：Oxygen is formed on fin surface
Change layer；Removing oxide layer is removed, fin is exposed；It anneals under an atmosphere of hydrogen so that fin mellow and fullization forms and stack nano wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310007063.5A CN103915316B (en) | 2013-01-09 | 2013-01-09 | Stacked nanowire fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310007063.5A CN103915316B (en) | 2013-01-09 | 2013-01-09 | Stacked nanowire fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103915316A CN103915316A (en) | 2014-07-09 |
| CN103915316B true CN103915316B (en) | 2018-07-27 |
Family
ID=51040913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310007063.5A Active CN103915316B (en) | 2013-01-09 | 2013-01-09 | Stacked nanowire fabrication method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103915316B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742153B (en) * | 2014-12-11 | 2019-09-24 | 中国科学院微电子研究所 | Method of forming cascaded nanowires |
| CN105742232B (en) * | 2014-12-11 | 2019-01-18 | 中国科学院微电子研究所 | Method for forming nanowire array |
| CN105742175B (en) * | 2014-12-11 | 2019-09-24 | 中国科学院微电子研究所 | Method for forming nanowire array |
| CN105742231B (en) * | 2014-12-11 | 2020-04-24 | 中国科学院微电子研究所 | Method for forming nanowire array |
| CN105742239B (en) * | 2014-12-11 | 2018-12-11 | 中国科学院微电子研究所 | Method for forming nanowire array |
| US9564489B2 (en) * | 2015-06-29 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple gate field-effect transistors having oxygen-scavenged gate stack |
| CN105590845A (en) * | 2015-12-25 | 2016-05-18 | 中国科学院微电子研究所 | Method for manufacturing stacked fence nanowire |
| CN105719961B (en) * | 2016-02-04 | 2018-08-10 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN107437556A (en) * | 2016-05-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | GAA structures MOSFET forming method |
| CN107871666B (en) * | 2017-09-25 | 2020-08-21 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing vertical stacking integrated semiconductor nano-wire and field effect transistor thereof |
| CN109888014B (en) * | 2017-12-06 | 2022-03-22 | 中芯国际集成电路制造(上海)有限公司 | Nanowire device and method of forming the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7034361B1 (en) * | 2003-09-03 | 2006-04-25 | Advanced Micro Devices, Inc. | Narrow body raised source/drain metal gate MOSFET |
| US7736954B2 (en) * | 2005-08-26 | 2010-06-15 | Sematech, Inc. | Methods for nanoscale feature imprint molding |
| CN101960570A (en) * | 2008-02-26 | 2011-01-26 | Nxp股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| US8759943B2 (en) * | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
| CN102623321B (en) * | 2012-03-31 | 2015-01-28 | 上海华力微电子有限公司 | Manufacture method of longitudinal stacking type rear-grid type SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon |
-
2013
- 2013-01-09 CN CN201310007063.5A patent/CN103915316B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103915316A (en) | 2014-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103915316B (en) | Stacked nanowire fabrication method | |
| CN104078324B (en) | Stacked nanowire fabrication method | |
| US10326021B2 (en) | Source/drain profile for FinFeT | |
| US10727351B2 (en) | Semiconductor structures and methods with high mobility and high energy bandgap materials | |
| CN103730366B (en) | Method for manufacturing stacked nanowire MOS transistor | |
| KR101633225B1 (en) | FIN STRUCTURE FOR A FinFET DEVICE | |
| CN104282561B (en) | FinFET device and manufacturing method thereof | |
| CN104282560B (en) | Method for manufacturing cascade stacked nanowire MOS transistor | |
| CN103839816B (en) | Semiconductor device and method for manufacturing the same | |
| CN102446972B (en) | There is transistor and the manufacture method thereof of the fin structure of band recess | |
| CN103367441B (en) | There is MOSFET of unsettled raceway groove and forming method thereof | |
| CN107403835A (en) | Semiconductor device and its manufacture craft | |
| CN104253048B (en) | Stacked nanowire fabrication method | |
| CN104282559A (en) | Stacked nanowire MOS transistor and manufacturing method thereof | |
| CN103839820B (en) | Semiconductor device manufacturing method | |
| CN107464846A (en) | Field-effect transistor and semiconductor structure | |
| CN111029406A (en) | Semiconductor device and preparation method thereof | |
| CN109473398B (en) | Semiconductor device and method for manufacturing the same | |
| CN103915324B (en) | Stacked nanowire fabrication method | |
| CN103579001A (en) | Fin type field effect transistor and forming method thereof | |
| CN104425346A (en) | Method for manufacturing fin on insulator | |
| CN103579315B (en) | Semiconductor device and method for manufacturing the same | |
| CN105336786B (en) | Semiconductor device and method for manufacturing the same | |
| CN105405881B (en) | Semiconductor device and method for manufacturing the same | |
| CN104064465B (en) | The forming method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |