CN105742175B - Method for forming nanowire array - Google Patents
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- CN105742175B CN105742175B CN201410768407.9A CN201410768407A CN105742175B CN 105742175 B CN105742175 B CN 105742175B CN 201410768407 A CN201410768407 A CN 201410768407A CN 105742175 B CN105742175 B CN 105742175B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000002070 nanowire Substances 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 54
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 239000011241 protective layer Substances 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 13
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000000243 solution Substances 0.000 claims description 4
- 125000001246 bromo group Chemical group Br* 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 2
- 238000010790 dilution Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 238000005121 nitriding Methods 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 125000001820 oxy group Chemical group [*:1]O[*:2] 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 125000001309 chloro group Chemical group Cl* 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 241000700605 Viruses Species 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- GDKWXCWTFCPDFQ-UHFFFAOYSA-N [Si].OP(O)(O)=O Chemical compound [Si].OP(O)(O)=O GDKWXCWTFCPDFQ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- MZJUGRUTVANEDW-UHFFFAOYSA-N bromine fluoride Chemical compound BrF MZJUGRUTVANEDW-UHFFFAOYSA-N 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000005543 nano-size silicon particle Substances 0.000 description 1
- 150000007523 nucleic acids Chemical class 0.000 description 1
- 102000039446 nucleic acids Human genes 0.000 description 1
- 108020004707 nucleic acids Proteins 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000006213 oxygenation reaction Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000013268 sustained release Methods 0.000 description 1
- 239000012730 sustained-release form Substances 0.000 description 1
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Abstract
A method of forming an array of nanowires, comprising: step 1, forming a plurality of hard mask patterns on a substrate; step 2, taking the plurality of hard mask patterns as masks, and performing an etching process on the substrate to form a plurality of concave parts and protruding parts; step 3, performing an oxidation or nitridation process to form a protective layer of oxide on the plurality of recesses and the plurality of protrusions; step 4, circularly executing the step 2 and the step 3 for multiple times, and forming a plurality of nanowires on the left protruding parts; and 5, cleaning and removing the hard mask patterns. According to the method for forming the nanowire array, the plasma etching and the oxygen plasma oxidation are alternately carried out in the same cavity, the method is compatible with the existing CMOS process, an additional self-limiting oxidation process is not needed, the cost is reduced, and the efficiency is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly, to a kind of side for forming nano-wire array
Method.
Background technique
As integrated circuit device continues miniature and consumption market to the need of more advanced device according to the requirement of Moore's Law
It asks, current advanced logic CMOS devices technology has reached 22nm node, and is expected to enter 14/16nm node on time.This is right
Many technologies propose challenge, especially lithographic technique, since it forms the figure especially active area lines of device,
So that integrated circuit is manufactured as possibility.Wherein, it is CMOS super large that etching, which forms the nano wire as source-drain area and channel region,
The key technology of scale integrated circuit.In addition, using three-dimensional stacked " grid surround entirely " (gate all around) nanowire channel
Nano-wire transistor, have ultra low quiescent power consumption and higher driving current, be 22 nm technology generation of integrated circuit or less pole
Potential device architecture.
In addition, the fine nano wire that etching is formed can be not only used for new technology integrated circuit, and in biomedicine etc.
Aspect has broad application prospects.For example, nanowire crystal tube sensor can be used for the Molecular Detection of no label, such as albumen
Matter, nucleic acid and virus.It has many advantages, such as that sensitivity is higher compared to traditional biological detecting method, speed faster, by grinding
The person's of studying carefully pursues.
Existing nano-wire transistor manufacture in, the companies such as intel use epitaxial silicon/Germanium silicon lamination, dry etching, it
Reselection erodes silicon layer or germanium silicon layer to form nano-wire array afterwards.This method can pass through multiple overlapping layerings
Between Etch selectivity and accurately control the width of nano wire, but disadvantage is mainly incompatible with traditional IC processing procedure, because needing
It deposits different multilayer materials and (such as introduces using additional different etching technics and be different from other etchings of Si etching
Mechanism).Another scheme is after Lausanne, SUI Institute of Technology etc. uses BOSCH technique to etch nanoscale sugarcoated haws shape silicon strip
Nano-wire array is formed using from limitation oxidation.But it is generally taken a long time from limitation oxidation technology, influences efficiency.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of nano wire lithographic methods of novelty, in patterned silicon
Nano wire is directly formed by etching on substrate, simple process is high-efficient.
Realize above-mentioned purpose of the invention, be by provide it is a kind of formed nano-wire array method, comprising: step 1,
Multiple hard mask patterns are formed on substrate；Step 2, using the multiple hard mask pattern as exposure mask, to substrate execute etching technics,
Form multiple recessed portions and protruding portion；Step 3 executes oxidation technology, and oxide is formed on multiple recessed portions and protruding portion
Protective layer；Step 2 and step 3 is performed a plurality of times in step 4, circulation, and adjacent protruding portion forms multiple nano wires；Step 5, cleaning are simultaneously
Remove multiple hard mask patterns.
Wherein, etching technics further comprises in step 2: a1, the protective layer for removing top surface；A2, anisotropic etching shape
At the groove with vertical sidewall；A3, isotropic etching form recessed portion and protruding portion.
Wherein, the width of nano wire is less than the width of protruding portion.
Wherein, the width of protruding portion is less than the width of each hard mask pattern.
Wherein, step a1 carries out dry plasma etch using the fluorine-based etching gas of carbon.
Wherein, step a2 carries out plasma dry etch using chloro or bromo etching gas.
Wherein, step a3 carries out plasma dry etch using fluorine-based etching gas.
Wherein, step 3 carries out plasma oxidation process using oxidizing gas.
Wherein, the fluorine-based etching gas of carbon uses the gas selected from He, Ar or combinations thereof to be diluted.
Wherein, step 3 carries out wet-cleaning using solution such as DHF, BOE, HF.
According to the method for formation nano-wire array of the invention, in the same chamber alternately plasma etching with
Oxygen plasma oxidation, it is compatible with existing CMOS technology and without additional from oxidation technology is limited, reduce costs, mention
High efficiency.
Detailed description of the invention
Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:
Fig. 1 to Fig. 7 is the diagrammatic cross-section according to each step of method of formation nano-wire array of the invention；And
Fig. 8 is the flow chart according to the method for formation nano-wire array of the invention.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect.It should be pointed out that similar appended drawing reference indicates similar structure, term " first " use herein, "
Two ", "upper", "lower", " thickness ", " thin " etc. can be used for modifying various device architectures.These modifications are not dark unless stated otherwise
Show space, order or the hierarchical relationship of modified device architecture.
Referring to Fig. 8 and Fig. 1, hard mask figure 2 is formed on substrate 1.Substrate 1 is provided, can be body Si, SOI, body
Ge, GeOI, SiGe, GeSb, are also possible to iii-v or II-VI group compound semiconductor substrate, such as GaAs, GaN,
InP, InSb etc..It is manufactured in order to compatible with existing CMOS technology with being applied to large-scale digital ic, substrate is preferred
Ground is body Si or SOI.Pass through rapid thermal oxidation (RTO), SACVD, LPCVD, PECVD, HDPCVD, spin coating, spray on substrate 1
Painting, silk-screen printing, sputtering, evaporation etc. technique formed hard mask layer, material can be silica, silicon nitride, silicon oxynitride,
Diamond-like agraphitic carbon (DLC), and combinations thereof (combination can be stacking and be also possible to mix).Using conventional rotation
The methods of apply, expose, develop, the soft mask graph (not shown) being made of photoresist layer is formd on hard mask layer.?
In a preferred embodiment of the invention, the accuracy of figure is improved using the fine lithography glue for being suitable for electron beam lithography.
In addition, in other embodiments of the present invention, it can also be using suitable for immersion 193nm photoetching process, i line, g linear light carving technology
Common photoresist photoresist is coated on hard mask layer.Using soft mask graph as mask, etch hard mask layer forms hard mask
Figure 2.As shown in Figure 1, hard mask pattern 2 is multiple nanometer lines of parallelly distribute on, width be, for example, 10~500nm,
Preferably 20~300nm and best 30~100nm, such as 40nm.
It is exposure mask with hard mask pattern 2 in first etching period referring to Fig. 8 and Fig. 2, multi-section is executed to substrate 1
Etching forms protrusion clamped by the recessed portion 1R and recessed portion 1R of indent below the hard mask pattern 2 in remaining substrate 1
Portion 1P.Etching apparatus is for example, by using capacitance coupling plasma (CCP) or inductively coupled plasma body (ICP, TCP) cavity, tool
There is Double RF.High frequency power is the plasma for being mainly used to generate high concentration, for adjusting plasma density；Low frequency system
For enhancing ion energy and bombardment intensity, etching directionality is promoted.It is independent from each other between radio frequency, in order to avoid influence each other.
This allows to carry out different optimization according to the specific feature of etachable material and structure.Such as obtained by adjusting Frequency Modulated radio power supply
More highdensity plasma is obtained, etching speed is increased.Also low frequency radio frequency power supply is adjusted and obtains suitable bombardment intensity, control
The pattern and degree of injury of etching.
Specifically, inside an etching period, it is divided into following three steps etch step:
A1, structure top surface (namely in horizontal direction) is removed using the fluorine-based etching gas plasma dry etch of carbon
Oxide layer.The fluorine-based etching gas of carbon such as CF4、CHF3, etc. the smaller etching gas of carbon fluorine, most preferably CF4.Etching gas is adopted
With gas dilutions such as He, Ar.
A2, with chlorine element or bromo etching gas plasma dry etch, execute anisotropic etching.It is mainly used for vertical
Downward etched substrate 1 forms the groove of vertical sidewall (as shown by the dash line in figure 2), and etching gas selects HBr, Cl2、Br2, HCl etc. and
A combination thereof, and can optionally increase small amounts gas such as O2To increase by 1 speed of etched substrate and sidewall steepness.
A3, with fluorine-based etching gas dry plasma etch, execute isotropic etching.It is mainly used in hard mask pattern
2 lower sections form the protruding portion 1P of 1 surplus material of substrate clamped by recessed portion 1R and recessed portion.Etching gas such as NF3、
SF6、F2、COF2Equal atomic weight it is larger and/or and fluorine-containing bigger gas, so enable to lateral/vertical etch speed it
It is bigger, such as close to 1, such as 0.7~1.1, best 0.93, to obtain the recessed portion 1R side wall of approximate circular arc.
Later, temporary protective material 3 is formed referring to Fig. 8 and Fig. 3, oxidation or nitride structure surface.Preferably, same
In processing chamber housing in (such as plasma dry etch equipment used in step a1~a3), stopping is passed through etching gas, only leads to
Enter oxidation or nitriability gas, with oxidation or nitriability gas to the bottom and side wall of structure, such as recessed portion 1R and prominent
The top of portion 1P and side wall are aoxidized or are nitrogenized, and form temporary protective material 3 on surface.As shown in figure 3, the temporary protective material 3
Also it is formed simultaneously on the top surface of 1 remainder of substrate.Oxidizing gas such as O2、O3、CO2, nitriability gas such as N2、NO、
NO2Deng and combinations thereof, so that the material of temporary protective material 3 is the corresponding oxide or nitride of 1 material of substrate, such as aoxidize
Silicon, silicon nitride.In addition it is also possible to form oxidation using other oxidation technologies such as rapid thermal oxidation, chemical oxidations in different chamber
The temporary protective material 3 of object.Above-mentioned oxidation to a certain extent because consume recessed portion 1P and protruding portion 1P part material and
Reduce the width that its width namely recessed portion 1P and protruding portion 1P will be less than hard mask pattern 2.Such as adjustable etching work
Skill parameter and oxidation technology parameter, so that protruding portion 1P width is about 0.68~0.95 times of hard 2 width of mask pattern, preferably
0.75~0.8 times.Protection recessed portion 1R and protruding portion 1P is no longer influenced by respectively by the temporary protective material 3 in subsequent etching process
To the same sex or anisotropic erosion, the side wall of nano wire and silicon trench is protected, avoids lines deformation, improves etching essence
Degree.
Then, referring to Fig. 8 and Fig. 4, second etching period is executed.It is similar with technique shown in Fig. 2 and the step, it adopts
With three sub-steps a1~a3, continue to form the second row recessed portion 1R and protruding portion 1P, each quarter below structure shown in Fig. 2
Erosion period remaining protruding portion 1P constitutes a nano wire, and the nano wire that multiple etching periods are formed constitutes array 1N.?
During this, since step a1 first uses the biggish small carbon fluorine of vertical etch rate to eliminate than etching gas the oxygen of structural top
Compound or nitride-temporary protective material 3, therefore can continue to etch downwards and obtain subsequent recessed portion and protruding portion；But it is same
When due to above-mentioned chloro, bromo, fluorine-based etching gas it is smaller for oxide or nitride etch rate, temporary protective material
3 can guarantee the nano wire 1N not constriction by the lateral corrasion of isotropic etching in step a3, so that upper and lower Multilayered Nanowires
Equivalent width, improve the accuracy of manufacture.
Then, referring to Fig. 8 and Fig. 5, second oxidation or nitridation period are executed.With technique shown in Fig. 3 and the step
Similar, each exposed surface of oxidation or nitridation existing structure continuously forms temporary protective material 3.Finally continue to be alternately performed quarter
Period and oxide/nitride period are lost, the array of multilayer as shown in FIG. 6 (every layer multiple) nano wire 1N has been obtained.It is worth noting
Although the application, which only lists four alternate cycles namely upper and lower four layers of nano wire 1N, the application, to be increased
Or reduce the nano wire number of plies, such as execute 2~20, preferably 3~15, more preferable 5~12, best 8 etchings-oxidation cycle week
Phase, (tri- etching sub-steps of a1~a3 and an oxidation technology step have been sequentially completed in each period) was to form number not
Deng nano-wire array.
Finally, removing hard mask pattern 2 using wet process or dry process referring to Fig. 8 and Fig. 7.DHF, BOE, HF etc. are molten
Liquid carries out wet-cleaning.For example, by using diluted HF, sustained release etching liquid (BOE) for oxidation silicon material, it is directed to using hot phosphoric acid
Silicon nitride material, using oxygen plasma dry etching for DLC material (preferably then further using wet processes such as dHF, dBOE
Technique removes surface oxidation silicon thin layer).In this way, having obtained four layers of nano wire as shown in Figure 7, served as a contrast in two neighboring etching period
The remaining protruding portion 1P in bottom has connected and composed nano wire 1N, and the width of nano wire 1N is less than the width of protruding portion 1P.Such as pass through
Etching parameters and oxygenation parameters are controlled, so that nano wire 1N width is only 0.4~0.7 times of hard 2 width of mask pattern.
According to the method for formation nano-wire array of the invention, in the same chamber alternately plasma etching with
Oxygen plasma oxidation, it is compatible with existing CMOS technology and without additional from oxidation technology is limited, reduce costs, mention
High efficiency.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to the method for forming device architecture.In addition, public by institute
The introduction opened, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, of the invention
Purpose do not lie in and be limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and it is disclosed
Device architecture and its manufacturing method will include all embodiments for falling within the scope of the present invention.
Claims (9)
1. a kind of method for forming nano-wire array, comprising:
Multiple hard mask patterns are formed on the substrate in step 1；
Step 2, using the multiple hard mask pattern as exposure mask, to substrate execute etching technics, form multiple recessed portions and protrusion
Portion；
Step 3 executes oxidation or nitriding process, and the protection of oxide or nitride is formed on multiple recessed portions and protruding portion
Layer；
Step 2 and step 3 is performed a plurality of times in step 4, circulation, and the protruding portion that each etching period leaves forms each nano wire,
In oxidation in each step 3 or nitriding process consume the part material of recessed portion and protruding portion and reduce its width and make
The width of final nano wire is less than the width of protruding portion in step 2；
Step 5 cleans and removes multiple hard mask patterns.
2. the method according to claim 1, wherein etching technics further comprises in step 2:
A1, the protective layer for removing top surface；
A2, anisotropic etching form the groove with vertical sidewall；
A3, isotropic etching form recessed portion and protruding portion.
3. the method according to claim 1, wherein the width of protruding portion is less than the width of each hard mask pattern.
4. method according to claim 2, wherein step a1 carries out dry plasma etch using the fluorine-based etching gas of carbon.
5. method according to claim 2, wherein step a2 carries out plasma dry quarter using oxygroup or bromo etching gas
Erosion.
6. method according to claim 2, wherein step a3 carries out plasma dry etch using fluorine-based etching gas.
7. the method according to claim 1, wherein step 3 carries out plasma oxidation or nitrogen using oxidation or nitriability gas
Chemical industry skill.
8. method according to claim 4, wherein the fluorine-based etching gas of carbon uses the gas selected from He, Ar or combinations thereof to carry out
Dilution.
9. the method according to claim 1, wherein step 3 carries out wet-cleaning using the solution selected from DHF, BOE, HF.
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