CN104078324A - Method for manufacturing stacked nanowires - Google Patents

Method for manufacturing stacked nanowires Download PDF

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Publication number
CN104078324A
CN104078324A CN201310110074.6A CN201310110074A CN104078324A CN 104078324 A CN104078324 A CN 104078324A CN 201310110074 A CN201310110074 A CN 201310110074A CN 104078324 A CN104078324 A CN 104078324A
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fin
nano wire
manufacture method
groove
etching
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CN201310110074.6A
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CN104078324B (en
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秦长亮
殷华湘
洪培真
马小龙
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Abstract

The invention discloses a method for manufacturing stacked nanowires. The method comprises the steps that a, a hard mask is formed on a substrate; b, a first groove and fins are formed by etching the substrate; c, side walls are formed on the side faces of the fins; d, the fins are etched, and second grooves are formed in the lower parts of the side walls; e, the fins are post-processed to form the stacked nanowires. According to the method for manufacturing the stacked nanowires, anisotropic etching and isotropic etching are adopted in a mixed mode, selective etching is achieved under the protection of the side walls on the side faces, precision of the stacked nanowires is improved, and miniaturization of components is facilitated.

Description

Stacking nano wire manufacture method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to a kind of manufacture method of stacking nano wire.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, this structural reinforcing grid control ability, suppressed electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, can suppress short-channel effect (SCE) and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, can realize raceway groove light dope, can carry out adjusting threshold voltage by the work function that metal gates is set, can obtain the drive current of approximately 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid has surrounded channel region end face and two sides, and grid control ability is stronger.Further, loopful has more advantage around nano wire multiple-grid device.
At loopful, in the manufacture process of nano wire multiple-grid device, a kind of known method is as follows: on Si substrate, form hard mask, adopt SF 6the anisortopicpiston of etching gas is dry-etched in the substrate of hard mask below and forms the first groove of indent slightly, leaves backing material and form fin structure between the first relative groove; Adopt high density C xf(carbon fluorine is higher) plasma etching of etching gas, on substrate and the first trenched side-wall form passivation layer; SF again 6anisotropic etching, removes passivation layer on substrate, leaves the passivation layer of the first groove madial wall; SF 6isotropic etching, continues etched substrate, forms the second groove in the first beneath trenches; The like, form multiple grooves and fin structure; Fin structure between oxidation groove, removes oxide, leaves nano-wire array.The method technology controlling and process difficulty, nanowire density is less, and consistency is poor.
Another kind of known method comprises: on SOI substrate, extension forms the overlapping epitaxial loayer of Si and Ge/SiGe successively, forms hard mask layer at top layer, and etching forms grid lines, and the Ge/SiGe layer between selective etch removal adjacent S i layer, leaves Si nano wire.The method is limited to Ge/SiGe bed boundary poor performance, and process costs is high, is difficult to popularize.
Another known method comprises substrate hocket anisotropy and isotropic etching, forms the groove of multiple Σ shape sections in substrate.The method that forms the groove of Σ shape section is for example to utilize Si substrate 110 etch rates in the etching liquids such as TMAH to be greater than 100 speed, and etching is terminated on selected crystal face.But the method is difficult to control groove (nano wire) shape homogeneity in vertical direction, the upper extreme point of for example groove and lower extreme point be (groove top etching is very fast, makes bottom be wider than top) not on vertical line, is not easy to form nano wire stacked structure.
Summary of the invention
From the above mentioned, the object of the present invention is to provide a kind of energy low cost, efficient stacking nano wire manufacture method.
For this reason, the invention provides a kind of stacking nano wire manufacture method, comprising: step a forms hard mask on substrate; Step b, etched substrate forms the first groove and fin; Step c, forms side wall in fin side; Steps d, etching fin forms the second groove below side wall; Step e, reprocessing fin, forms stacking nano wire.
Wherein, repeating step b, to steps d, forms the fin array of multiple fins group formations of stacked on top of one another.
Wherein, adopt anisotropic etching in step b, the first groove of formation has vertical sidewall.
Wherein, step c further comprises: on substrate and fin side form dielectric layer; Anisotropic etching dielectric layer, removes dielectric layer on substrate, only leaves dielectric layer in fin side and forms side wall.
Wherein, the method for formation dielectric layer comprises deposition and/or thermal oxidation.
Wherein, adopt isotropic etching in steps d, the second groove of formation has female parts.
Wherein, isotropic etching method comprises dry etching and/or wet etching.
Wherein, between the second groove in steps d, remain with the remainder of fin, or the second groove break-through is be separated from each other fin.
Wherein, step e further comprises: form oxide layer on fin surface; Remove oxide layer, expose fin.
Wherein, step e comprises: under atmosphere of hydrogen, anneal, make mellow and fullization of fin form stacking nano wire.
According to stacking nano wire manufacture method of the present invention, mix and adopt anisotropy and isotropic etching, under the side wall protection forming at sidewall, realize selective etch, improve thus the precision of stacking nano wire, be conducive to device miniaturization.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 9 is the cut-away view according to the each step of manufacture method of the present invention; And
Figure 10 is the indicative flowchart according to manufacture method of the present invention.
Embodiment
The feature and the technique effect thereof that also describe technical solution of the present invention referring to accompanying drawing in conjunction with schematic embodiment in detail, disclose energy low cost, efficient stacking nano wire manufacture method.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
First, describe in detail according to the each step of method, semi-conductor device manufacturing method of the present invention below with reference to the flow chart of Figure 10 and referring to figs. 1 through the generalized section of Fig. 9.
As shown in Figure 1, on substrate 1, form hard mask 2.Substrate 1 is provided, substrate 1 needs and choose reasonable according to device purposes, can comprise monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.Preferably, substrate 1 for body Si so that with CMOS process compatible for making large scale integrated circuit.More preferably, substrate 1 is (100) crystal face.
By conventional methods such as LPCVD, PECVD, UHVCVD, HDPCVD, thermal oxidation, chemical oxidation, MBE, ALD, evaporation, sputters, on substrate 1, form hard mask layer, and utilize already known processes photoetching/etching to form hard mask graph 2.The material of hard mask 2 can be silica, silicon nitride, silicon oxynitride and combination thereof.
As shown in Figure 2, etched substrate 1 forms the first groove 1G, and substrate 1 remainder that hard mask 2 belows stay forms the first fin 1F.Etching is preferably anisotropic etching, taking the sidewall that makes the first groove 1G as (substantially) vertical.Anisotropic etching is fluorine base gas plasma dry etching preferably, so that accurately control etching depth d by controlling etching condition e, and then control final nanowire height/thickness.Preferably, it is (110) face and (substantially) vertical substrates that etching makes the sidewall of the first groove 1G, and substrate 1 surface is still (100) face.
As shown in Figure 3, form dielectric layer 3 on substrate 1, fin 1F and the first groove 1G surface.Can pass through the method depositions such as LPCVD, PECVD, HDPCVD, UHVCVD, MBE, ALD, also can for example, for example, carry out oxidation growth and form dielectric layer 3 by thermal oxidation (heating in high temperature furnace), chemical oxidation (immersing in the deionized water that contains ozone).The material of dielectric layer 3 is preferably different from hard mask 2, substrate 1, can be selected from silica, silicon nitride, silicon oxynitride, high k material, wherein high k material includes but not limited to that nitride (for example SiN, AlN, TiN), metal oxide (are mainly subgroup and lanthanide element oxide, for example MgO, Al 2o 3, Ta 2o 5, TiO 2, ZnO, ZrO 2, HfO 2, CeO 2, Y 2o 3, La 2o 3), nitrogen oxide (as HfSiON); Perovskite Phase oxide (for example PbZr xti 1-xo 3(PZT), Ba xsr 1-xtiO 3(BST)).In a preferred embodiment of the invention, dielectric layer 3, for the silica that thermal oxidation technology forms, because thermal oxidation technology can make to exist obvious growth rate poor between the dielectric layer 3 of silica and the substrate 1 of silicon, is conducive to improve the conformality of dielectric layer 3.Dielectric layer 3 has covered the surface of substrate 1, fin 1F, the first groove 1G completely.
As shown in Figure 4, selective etch is removed the part dielectric layer 3 on substrate 1 surface, only at fin 1F(the first groove 1G) side reserve part dielectric layer 3, form fin side wall 3S.Lithographic method is anisotropic etching preferably, and for example plasma dry etching can be selected fluorine base gas-such as carbon fluorine base gas (C xh yf z) or chlorine-based gas-such as Cl 2and/or HCl.
As shown in Figure 5, continue etched substrate 1, below fin 1F, form the second groove 1G '.Due to the protection of fin side wall 3S, etching is less for fin 1F impact, but has thereunder formed the second groove 1G ' of indent.Etching herein preferably adopts isotropic etching, and for example dry etching and/or wet etching can use separately, also can be combined with (for example first dry etching vertical direction, then wet etching side).For dry etching, for example select RIE, can select carbon fluorine base gas and adjust proportioning, make it have isotropic etching.For wet etching, can select Tetramethylammonium hydroxide (TMAH) or KOH to corrode with the substrate 1 for Si material.The profile morphology of the second groove 1G ' needn't be only circular-arc as shown in Figure 5, but can comprise that (multistage broken line is connected for rectangle, trapezoidal, inverted trapezoidal, Σ shape, recessed towards channel region, also be the width that the width at groove middle part is greater than top and/or bottom), D shape (1/2 curve, curve comprises circle, oval, hyperbola), C shape (be greater than 1/2 curve, curve comprises circle, oval, hyperbola).In one embodiment of the invention, its indent degree of depth be preferably less than or equal to fin 1F width 1/3, be for example 1/4, also i.e. not break-through of the second groove.
As shown in Figure 6, similar or repeat these operations with technique shown in Fig. 2～Fig. 4, first carry out anisotropic etching substrate and organize the first groove 1G to form another group fin 1F ' below fin 1F with another, then preferably adopt thermal oxidation method to form another dielectric layer 3, anisotropic etching dielectric layer 3 forms another fin side wall 3S ' (second group of fin side wall).
As shown in Figure 7, repeat the operation of Fig. 6 or the operation of Fig. 2 to Fig. 4, below second group of fin, form the 3rd group of fin, and correspondingly form the 3rd group of fin side wall 3S.
Below respectively organize fin and will be used for forming nano wire, the narrow 1C by the second groove 1G ' clamping between two groups of neighbouring fins is connected.
As shown in Figure 8, after having formed many groups fin 1F and narrow connected part 1C, with reference to operation shown in Fig. 5, form last and organize the second groove 1G '.Lithographic method can be dry etching and/or wet etching, forms the second groove 1G ' and has inside recessed.
As shown in Figure 9, carry out reprocessing to form nano wire storehouse.
A kind of conventional method comprises the method that adopts thermal oxidation, chemical oxidation, forms oxide layer (for example silica, not shown), and make remaining fin structure 1F form nano wire 1NW on fin structure 1F surface.Subsequently, remove surperficial oxide layer, leave nano wire 1NW.Removal method is for example that whole device wafer immerses HF base corrosive liquid (dHF or dBOE(slowly-releasing etching agent)), the oxide layer of erosion removal silica material, only leaves the gate line strip array of the stacking formation of multiple nano wire 1NW.Preferably, can further in atmosphere of hydrogen, anneal, make mellow and fullization of fin structure 1F surface, residue ground, the conglobate nano wire 1NW of shape.
In addition, for the second groove 1G ' of different profile morphologies, for example, when second groove 1G ' the indent degree of depth continues to increase when making the second relative groove 1G ' break-through, fin 1F forms prism-shaped, therefore can be without adopting method for oxidation carry out attenuate fin, but directly adopt hydrogen annealing process to make that prismatic fin 1F surface is mellow and full turns to circular nano wire 1NW.
Preferably, the finally hard mask 2 at further erosion removal top also, for example, adopt hot phosphoric acid corrosion to remove the hard mask 2 of silicon nitride material.
It should be noted that the fin shown in figure, nano wire are rectangular section, in fact can be different and there are other various rational shapes according to technique, for example circle, ellipse, parabola, hyperbola, triangle, trapezoidal, rhombus and combination thereof.
According to stacking nano wire manufacture method of the present invention, mix and adopt anisotropy and isotropic etching, under the side wall protection forming at sidewall, realize selective etch, improve thus the precision of stacking nano wire, be conducive to device miniaturization.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (10)

1. a stacking nano wire manufacture method, comprising:
Step a forms hard mask on substrate;
Step b, etched substrate forms the first groove and fin;
Step c, forms side wall in fin side;
Steps d, etching fin forms the second groove below side wall;
Step e, reprocessing fin, forms stacking nano wire.
2. stacking nano wire manufacture method as claimed in claim 1, wherein, repeating step b, to steps d, forms the fin array of multiple fins group formations of stacked on top of one another.
3. stacking nano wire manufacture method as claimed in claim 1, wherein, adopts anisotropic etching in step b, and the first groove of formation has vertical sidewall.
4. stacking nano wire manufacture method as claimed in claim 1, wherein, step c further comprises:
On substrate and fin side form dielectric layer;
Anisotropic etching dielectric layer, removes dielectric layer on substrate, only leaves dielectric layer in fin side and forms side wall.
5. stacking nano wire manufacture method as claimed in claim 4, wherein, the method that forms dielectric layer comprises deposition and/or thermal oxidation.
6. stacking nano wire manufacture method as claimed in claim 1, wherein, adopts isotropic etching in steps d, and the second groove of formation has female parts.
7. stacking nano wire manufacture method as claimed in claim 6, wherein, isotropic etching method comprises dry etching and/or wet etching.
8. stacking nano wire manufacture method as claimed in claim 1, wherein, remain with the remainder of fin between the second groove in steps d, or the second groove break-through is be separated from each other fin.
9. stacking nano wire manufacture method as claimed in claim 1, wherein, step e further comprises:
Form oxide layer on fin surface; Remove oxide layer, expose fin.
10. stacking nano wire manufacture method as claimed in claim 1, wherein, step e comprises: under atmosphere of hydrogen, anneal, make mellow and fullization of fin form stacking nano wire.
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CN105632916A (en) * 2016-02-22 2016-06-01 国家纳米科学中心 Etching method for variable-cross-section silicon holes and silicon channels
CN105719961A (en) * 2016-02-04 2016-06-29 中国科学院微电子研究所 Stacked nanowire manufacturing method
CN105742175A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
CN105742239A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for nanowire array formation
CN105742153A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for cascade nanowire formation
CN105742232A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
CN105742231A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
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CN107437556A (en) * 2016-05-27 2017-12-05 中芯国际集成电路制造(上海)有限公司 GAA structures MOSFET forming method
CN107910362A (en) * 2017-11-17 2018-04-13 北京大学 A kind of FinFET of anti-integral dose radiation and preparation method thereof
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CN104609360A (en) * 2013-11-05 2015-05-13 中国科学院微电子研究所 Nano wire and array formation method
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CN105742175A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
CN105742232B (en) * 2014-12-11 2019-01-18 中国科学院微电子研究所 The method for forming nano-wire array
CN105742239A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for nanowire array formation
CN105742153A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for cascade nanowire formation
CN105742232A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
CN105742231A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Nanowire array formation method
CN105742175B (en) * 2014-12-11 2019-09-24 中国科学院微电子研究所 The method for forming nano-wire array
CN105742153B (en) * 2014-12-11 2019-09-24 中国科学院微电子研究所 The method for forming cascade nano wire
CN105719961A (en) * 2016-02-04 2016-06-29 中国科学院微电子研究所 Stacked nanowire manufacturing method
CN105719961B (en) * 2016-02-04 2018-08-10 中国科学院微电子研究所 Stack nano wire manufacturing method
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