CN107393964B - High-performance FINFET device and preparation method thereof - Google Patents
High-performance FINFET device and preparation method thereof Download PDFInfo
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- CN107393964B CN107393964B CN201710523018.3A CN201710523018A CN107393964B CN 107393964 B CN107393964 B CN 107393964B CN 201710523018 A CN201710523018 A CN 201710523018A CN 107393964 B CN107393964 B CN 107393964B
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 238000005019 vapor deposition process Methods 0.000 claims description 2
- 238000000427 thin-film deposition Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a high-performance FINFET device and a preparation method thereof, wherein a plurality of arc grooves are formed on the side wall of a silicon fin by adopting a plurality of repeated cycles of isotropic etching, thin film deposition and anisotropic etching, so that the length of the silicon fin is improved, and the driving current of the FINFET device is increased because W is increased in proportion to W/L, wherein W is the length of the silicon fin, and L is the length of a grid electrode. Furthermore, the semiconductor substrate is subjected to ion implantation, a dielectric layer is deposited in the groove, and after the next groove is etched, the dielectric layer is completely removed, so that the width of the fin is reduced, the arrangement density of the fins on the substrate is improved, the length L of a grid electrode on a single fin is reduced, and the driving current is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-performance FINFET device and a preparation method thereof.
Background
With the continuous development of semiconductor technology, the thickness of a gate oxide layer, the depth of a depletion layer and the length of a channel are continuously reduced, and the degradation of subthreshold characteristics is more obvious due to the reduction of a drain induction barrier of a short channel effect. Conventional planar MOSFETs have encountered unprecedented difficulties in semiconductor technology development. A Fin Field Effect Transistor (FINFET) effectively suppresses a short channel Effect by a multi-gate structure, and moreover, the manufacturing process of the FINFET has good compatibility with the manufacturing process of a conventional planar channel metal-oxide semiconductor Field Effect Transistor, and gradually becomes a mainstream device structure.
Generally, superior FINFET devices are required to have high gate control capability, current drive capability, and the ability to suppress short channel effects. Therefore, increasing the drive current of FINFET devices is one of the effective means to achieve high performance FINFET devices.
Disclosure of Invention
In order to overcome the above problems, the present invention aims to provide a high performance FINFET device and a method for manufacturing the same, which uses the sidewall of a silicon fin to form a plurality of arc-shaped grooves to increase the driving current of a FINFET.
In order to achieve the above object, the present invention provides a FINFET device having a plurality of curved recesses on the fin sidewalls, such that the gate-fin contact interface overlying the fins follows a plurality of curved shapes.
Preferably, the arc-shaped groove of the fin sidewall is hemispherical.
Preferably, a tip protrusion is formed between adjacent ones of the arc-shaped grooves.
Preferably, the material of the fin is monocrystalline silicon.
In order to achieve the above object, the present invention also provides a method of manufacturing a FINFET device, comprising:
step 01: providing a semiconductor substrate;
step 02: etching the semiconductor substrate by adopting isotropic etching, thereby forming at least two grooves with arc-shaped side walls in the semiconductor substrate;
step 03: forming dielectric layers on the side wall and the bottom of the groove and the surface of the semiconductor substrate;
step 04: removing the dielectric layer at the bottom of the groove by adopting anisotropic etching;
step 05: etching downwards from the bottom of the groove by adopting isotropic etching, so as to form another groove with an arc-shaped side wall in the semiconductor substrate at the bottom of the groove;
step 06: and repeating the steps 03-05 to form the fin with a plurality of arc-shaped groove side walls in the semiconductor substrate.
Preferably, the step 04 further includes continuing to perform anisotropic etching downwards to a certain depth to form vertical sidewalls. In the step 06, the steps 03-05 are repeated, so that vertical side walls located between the arc-shaped grooves are formed on the fin with the plurality of arc-shaped groove side walls.
Preferably, in step 03, a vapor deposition process is used for forming the dielectric layer.
Preferably, the formed dielectric layer is an oxide film, and the step 01 further includes: and carrying out ion implantation on the semiconductor substrate to form the semiconductor substrate with the doping type.
Preferably, in the step 04, all the surfaces perpendicular to the surface of the semiconductor substrate are etched by using plasma in the anisotropic etching process.
Preferably, after the step 04 and before the step 05, the method further comprises: and removing all the residual dielectric layers.
According to the high-performance FINFET device and the preparation method thereof, multiple repeated cycles of isotropic etching, thin film deposition and anisotropic etching are adopted, and multiple arc-shaped grooves are formed in the side wall of the silicon fin, so that the length of the silicon fin is improved. Furthermore, a dielectric layer is deposited in the groove, and after the next groove is etched, the dielectric layer is completely removed, so that the width of the fin is reduced, the arrangement density of the fins on the substrate is improved, the length L of the gate on a single fin is reduced, and the driving current is further improved.
Drawings
FIG. 1 is a schematic diagram of a FINFET device according to a preferred embodiment of the present invention
FIG. 2 is a schematic diagram of a FINFET device according to a preferred embodiment of the present invention
FIG. 3 is a flow chart illustrating a method of fabricating a FINFET device in accordance with a preferred embodiment of the present invention
FIGS. 4-9 are schematic diagrams of steps of a method of making the FINFET device of FIG. 3
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention will be described in further detail with reference to examples 1 to 9. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Referring to fig. 1, the FINFET device of this embodiment is located on a semiconductor substrate 00, and the fin sidewall of the FINFET device has a plurality of arc-shaped trench sidewalls 02, so that the contact interface between the gate and the fin covering the fin is in a plurality of arc shapes. Preferably, the arc-shaped groove sidewall 02 of the fin sidewall is hemispherical. The vertical sidewalls may be set with a certain interval between the adjacent arc-shaped groove sidewalls 02 as shown in fig. 1, or may be set without an interval so that the tip end protrusion is formed between the adjacent arc-shaped groove sidewalls 02 as shown in fig. 2. In this embodiment, the material of the fin may be monocrystalline silicon.
In addition, referring to fig. 3, a method for manufacturing a FINFET device of this embodiment includes:
step 01: referring to fig. 4, a semiconductor substrate 00 is provided;
specifically, the semiconductor substrate 00 may be, but is not limited to, a single crystal silicon substrate. The semiconductor substrate 00 may be ion implanted, but not limited to, such that the semiconductor substrate 00 has a doping type, for example, P-type or N-type.
Step 02: referring to fig. 5, the semiconductor substrate 00 is etched by isotropic etching, thereby forming at least two trenches G1 having arc-shaped groove sidewalls 02 in the semiconductor substrate 00;
specifically, the isotropic etching adopts a plasma dry etching or wet etching process. Since silicon fins are formed between the trenches G1, at least two trenches G1 need to be formed, thereby forming at least one silicon fin. The material of the fin may or may not be the same as the semiconductor substrate 00, e.g., monocrystalline silicon.
Step 03: referring to fig. 6, a dielectric layer J is formed on the sidewall and bottom of the trench G1 and on the surface of the semiconductor substrate 00;
specifically, the dielectric layer J may be deposited by, but is not limited to, a chemical vapor deposition process, and is preferably an oxide film, here a silicon dioxide film.
Step 04: referring to fig. 7, the dielectric layer J at the bottom of the trench G1 is removed by anisotropic etching;
specifically, in the anisotropic etching process, all the surfaces parallel to the surface of the semiconductor substrate 00 may be etched by using plasma.
In this embodiment, after step 04 and before step 05, the method further includes: and removing all the residual dielectric layers, thereby reducing the width of the silicon fin and increasing the arrangement density of the silicon fin.
Step 05: referring to fig. 8, the etching is continued from the bottom of the trench G1 downward by using the isotropic etching, so that another trench G2 having an arc-shaped groove sidewall 02 is formed in the semiconductor substrate 00 at the bottom of the trench G1;
step 06: referring to fig. 9, steps 03-05 are repeated to form a fin having a plurality of curved recess sidewalls 02 in the semiconductor substrate 00.
Specifically, in the fin having the plurality of arc-shaped groove sidewalls 02 obtained, the ends of the arc-shaped groove sidewalls 02 are connected, thereby forming a tip between the adjacent arc-shaped groove sidewalls 02.
It should be noted that, in step 04, in order to obtain a vertical sidewall having a certain height between the arc-shaped grooves of the finally obtained sidewalls of the fin, after the dielectric layer at the bottom of the trench is removed, anisotropic etching may be further performed downward to a certain depth, so as to form the vertical sidewall.
Then, steps 03-05 are repeated in step 06 so that vertical sidewalls are formed between the arcuate grooves on the plurality of fins having arcuate groove sidewalls, as shown in FIG. 1.
Although the present invention has been described with reference to preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, but rather, may be embodied in many different forms and modifications without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (4)
1. A method of fabricating a FINFET device, comprising:
step 01: providing a semiconductor substrate; the semiconductor substrate is a monocrystalline silicon substrate;
step 02: etching the semiconductor substrate by adopting isotropic etching, thereby forming at least two grooves with arc-shaped side walls in the semiconductor substrate;
step 03: forming dielectric layers on the side wall and the bottom of the groove and the surface of the semiconductor substrate;
step 04: removing the dielectric layer at the bottom of the groove by adopting anisotropic etching;
step 05: etching downwards from the bottom of the groove by adopting isotropic etching, so as to form another groove with an arc-shaped side wall in the semiconductor substrate at the bottom of the groove; then, the dielectric layer is completely removed, so that the width of the fin is reduced, the arrangement density of the fins on the substrate is improved, and the length of a grid electrode on a single fin is reduced;
step 06: repeating the steps 03-05, so that a fin with a plurality of arc-shaped groove side walls is formed in the semiconductor substrate; wherein the resulting fin has a plurality of arcuate recess sidewalls, the ends of the arcuate recess sidewalls being connected to form a tip between adjacent arcuate recess sidewalls to increase the length of the silicon fin to increase the drive current of the FINFET.
2. The method according to claim 1, wherein in step 03, the dielectric layer is formed by a vapor deposition process.
3. The method according to claim 1, wherein the formed dielectric layer is an oxide film, and the step 01 further comprises: and carrying out ion implantation on the semiconductor substrate to form the semiconductor substrate with the doping type.
4. The manufacturing method according to claim 1, wherein in the step 04, all the surfaces perpendicular to the surface of the semiconductor substrate are etched by using plasma in the anisotropic etching process.
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| CN201710523018.3A CN107393964B (en) | 2017-06-30 | 2017-06-30 | High-performance FINFET device and preparation method thereof |
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| CN201710523018.3A CN107393964B (en) | 2017-06-30 | 2017-06-30 | High-performance FINFET device and preparation method thereof |
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| CN107393964B true CN107393964B (en) | 2020-10-02 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of making the same |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7407847B2 (en) * | 2006-03-31 | 2008-08-05 | Intel Corporation | Stacked multi-gate transistor design and method of fabrication |
| CN104282559A (en) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | Stacked nanowire MOS transistor and manufacturing method thereof |
| CN104779283A (en) * | 2014-01-09 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | FINFET device capable of enhancing gate control and current drive and manufacturing method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of making the same |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
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