CN103177963B - A kind of manufacture method of FinFET - Google Patents
A kind of manufacture method of FinFET Download PDFInfo
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- CN103177963B CN103177963B CN201110434023.XA CN201110434023A CN103177963B CN 103177963 B CN103177963 B CN 103177963B CN 201110434023 A CN201110434023 A CN 201110434023A CN 103177963 B CN103177963 B CN 103177963B
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Abstract
The invention provides a kind of manufacture method of FinFET, comprising: silicon substrate is provided, and etch described silicon substrate to form the Fin of described FinFET; Described silicon substrate is formed the grid of described FinFET, and forms the first side wall body in the both sides of described grid; The second sidewall bodies is formed in the both sides of described Fin; A groove is formed in the below of the source/drain region of described Fin; Described silicon substrate forms a flowable oxide skin(coating), to fill described groove completely; Described silicon substrate is formed a photoresist oxidant layer, and photoresist oxidant layer described in etch-back; Remove not by the oxide skin(coating) of described photoresist oxidant layer covering; Remove described photoresist oxidant layer, and remove the remaining oxide skin(coating) be positioned in described the first side wall body and the second sidewall bodies; Remove described second sidewall bodies.According to the present invention, buried oxide layer can be formed in the source/drain region of fin (Fin) to realize the good isolation between described Fin, can manufacturing cost be reduced simultaneously.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of manufacture method with the FinFET of local dielectric silicon-on.
Background technology
Existing complementary metal oxide semiconductors (CMOS) (CMOS) transistor is two-dimentional, and along with constantly reducing of channel dimensions, the problem relevant with short-channel effect is more and more difficult to overcome.Therefore, chip manufacturer is developing the transistor of the three-dimensional with higher effect, such as fin formula field effect transistor (FinFET), and it can adapt to the scaled requirement of device size better.
The method of existing formation FinFET generally includes following processing step: the formation of the formation → contact hole of the selective growth → source/drain region injection → self-aligned silicide of the formation → source/drain region of the formation → expansion area injection → sidewall of the formation → sidewall of the formation → well region injection → grid of fin (Fin) and other front end operation.In above-mentioned processing step, fin (Fin) be formed with two kinds of methods.One method is: on silicon substrate, directly etch Fin, then on silicon substrate deposition oxide to isolate described Fin; The shortcoming of the method is: because described Fin has very large depth-width ratio, and between described Fin, thus form oxide skin(coating) is very difficult, and effect neither be fine.Another kind method is: on silicon substrate, first form a silicon oxide layer to form silicon-on-insulator (SOI) structure, then epitaxial growth one silicon layer on described silicon on insulated substrate, etch described silicon layer to form described Fin; The shortcoming of the method is: manufacturing cost is very high, and comparatively silicon substrate is poor for the thermal diffusivity of simultaneously described silicon oxide layer, can cause the heat in raceway groove can not be effectively lost, causes temperature to raise, affects mobility, have negative effect to device performance.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of FinFET, comprising: silicon substrate is provided, and on described silicon substrate, form a laying and a hard mask layer successively; Graphical described silicon substrate, and etch described silicon substrate to form the Fin of described FinFET; Described silicon substrate forms gate stack structure, etches described gate stack structure to form the grid of described FinFET, and form the first side wall body in the both sides of described grid; The second sidewall bodies is formed in the both sides of described Fin; Etch described silicon substrate, form a groove with the below of the source/drain region at described Fin; Described silicon substrate forms a flowable oxide skin(coating), to fill described groove completely; Described silicon substrate is formed a photoresist oxidant layer, and photoresist oxidant layer described in etch-back; Remove not by the oxide skin(coating) of described photoresist oxidant layer covering; Remove described photoresist oxidant layer, and remove the remaining oxide skin(coating) be positioned in described the first side wall body and the second sidewall bodies; Remove described second sidewall bodies.
Further, the material of described laying is oxide.
Further, the material of described hard mask layer is silicon nitride.
Further, chemical vapor deposition method is adopted to form described gate stack structure.
Further, described gate stack structure comprises the high-k dielectric layer, gate material layers and the cover layer that stack gradually from bottom to top.
Further, the material of described the first side wall body and described second sidewall bodies is silicon nitride.
Further, the width of described the first side wall body is greater than the half sum of the width of described second sidewall bodies and the width of described Fin.
Further, the technique of first anisotropic etching isotropic etching is again adopted to etch described silicon substrate to form described groove.
Further, the degree of depth of described groove is greater than the half sum of the width of described second sidewall bodies and the width of described Fin but is less than the width of described the first side wall body.
Further, chemical vapor deposition method is adopted to form described oxide skin(coating).
Further, described etch-back is until stop when making described photoresist oxidant layer only cover the oxide skin(coating) being positioned at described Fin both sides.
Further, wet etching process is adopted to remove not by the oxide skin(coating) of described photoresist oxidant layer covering.
Further, wet etching process is adopted to remove remaining oxide skin(coating).
Further, wet etching process is adopted to remove described second sidewall bodies.
Further, after described second sidewall bodies of removal, following processing step is also comprised: expansion area is injected, form clearance wall structure, source/drain region is injected, form self-aligned silicide, form contact hole and metal interconnecting wires.
The present invention also provides a kind of FinFET, and described FinFET has one and is positioned at local dielectric silicon-on below source/drain region, and described local dielectric silicon-on adopts said method to be formed.
According to the present invention, buried oxide layer can be formed to realize the good isolation between described Fin in the source/drain region of fin (Fin), simultaneously do not form buried oxide layer due to the channel region of described Fin and at the new silicon layer of described buried oxide layer Epitaxial growth, thus need can not reduce manufacturing cost.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 J is the schematic cross sectional view with each step of the manufacture method of the FinFET of local dielectric silicon-on that the present invention proposes;
Fig. 2 is the flow chart with the manufacture method of the FinFET of local dielectric silicon-on that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the manufacture method with the FinFET of local dielectric silicon-on of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step with the manufacture method of the FinFET of local dielectric silicon-on of the present invention's proposition is described with reference to Figure 1A-Fig. 1 J and Fig. 2.
With reference to Figure 1A-Fig. 1 J, illustrated therein is the schematic cross sectional view with each step of the manufacture method of the FinFET of local dielectric silicon-on that the present invention proposes.
First, as shown in Figure 1A, provide silicon substrate 100, adopt chemical vapor deposition method on described silicon substrate 100, form laying 102 and a hard mask layer 103 successively; The material of described laying 102 is oxide, and as silica, the material of described hard mask layer 103 is silicon nitride.Then, graphical described silicon substrate 100, and etch described silicon substrate 100 to form fin (Fin) 101.
Then, as shown in Figure 1B, chemical vapor deposition method is adopted on described silicon substrate 100, to form gate stack structure 104, to cover described fin (Fin) 101.Described gate stack structure 104 comprises the high-k dielectric layer, gate material layers and the cover layer that stack gradually from bottom to top.The material of described high-k dielectric layer can comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia and aluminium oxide.The material of described gate material layers can comprise polysilicon.Described tectal material can comprise titanium nitride and tantalum nitride.
Next, etch described gate stack structure 104, to form the grid of FinFET.Then, form the first side wall body 105 in the both sides of described grid, the material of described the first side wall body 105 is silicon nitride.
Then, as shown in Figure 1 C, form the second sidewall bodies 106 in the both sides of described fin (Fin) 101, the material of described second sidewall bodies 106 is silicon nitride.It should be noted that, the width of described the first side wall body 105 should be greater than the half sum of the width of described second sidewall bodies 106 and the width of described fin (Fin) 101, to guarantee that the silicon substrate below the grid of FinFET described in following etching process is not etched.
Then, as shown in figure ip, adopt the technique of first anisotropic etching isotropic etching again to etch described silicon substrate 100, form a groove 107 with the below of the source/drain region at described fin (Fin) 101.The degree of depth of described groove 107 is greater than the half sum of the width of described second sidewall bodies 106 and the width of described fin (Fin) 101 but is less than the width of described the first side wall body 105, to guarantee that the silicon substrate etched away completely below the source/drain region of described fin (Fin) 101 does not etch the silicon substrate below the grid of described FinFET simultaneously.
Then, as referring to figure 1e, chemical vapor deposition method is adopted on described silicon substrate 100, to form a flowable oxide skin(coating) 108, to fill described groove 107 completely.Because this technique is non-conformal gas-phase deposition, the described oxide skin(coating) thus formed on the side of described the first side wall body 105 and described second sidewall bodies 106 is very thin.
Then, as shown in fig. 1f, spin coating proceeding is adopted to form a photoresist oxidant layer 109 on described silicon substrate 100, and photoresist oxidant layer 109 described in etch-back, only cover to make described photoresist oxidant layer 109 oxide skin(coating) 108 being positioned at described fin (Fin) 101 both sides.
Then, as shown in Figure 1 G, wet etching process is adopted to remove not by oxide skin(coating) 108 that described photoresist oxidant layer 109 covers.The etchant of described wet etching process is the hydrofluoric acid of dilution.
Then, as shown in fig. 1h, remove described photoresist oxidant layer 109, the method that those skilled in the art can be adopted to have the knack of completes this step.
Then, as shown in Figure 1 I, wet etching process is adopted to remove the remaining oxide skin(coating) 108 be positioned in described the first side wall body and the second sidewall bodies.The etchant of described wet etching process is the hydrofluoric acid of dilution.It should be noted that, according to actual needs, the removal amount of described remaining oxide skin(coating) 108 can be controlled.
Then, as shown in figure ij, wet etching process is adopted to remove described second sidewall bodies 106.The etchant of described wet etching process is hot phosphoric acid.
So far, complete whole processing steps that method is according to an exemplary embodiment of the present invention implemented, next, the making of whole FinFET can be completed by subsequent technique, described subsequent technique is identical with traditional FinFET processing technology, and described subsequent technique includes but not limited to that expansion area injection, formation clearance wall structure, source/drain region are injected, form self-aligned silicide, formed contact hole and metal interconnecting wires.According to the present invention, buried oxide layer can be formed to realize the good isolation between described Fin in the source/drain region of fin (Fin), simultaneously do not form buried oxide layer due to the channel region of described Fin and at the new silicon layer of described buried oxide layer Epitaxial growth, thus need can not reduce manufacturing cost.
With reference to Fig. 2, illustrated therein is the flow chart with the manufacture method of the FinFET of local dielectric silicon-on that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide silicon substrate, and on described silicon substrate, form a laying and a hard mask layer successively;
In step 202., graphical described silicon substrate, and etch described silicon substrate to form the Fin of FinFET;
In step 203, described silicon substrate forms gate stack structure, etch described gate stack structure to form the grid of FinFET, and form the first side wall body in the both sides of described grid;
In step 204, the second sidewall bodies is formed in the both sides of described Fin;
In step 205, etch described silicon substrate, form a groove with the below of the source/drain region at described Fin;
In step 206, described silicon substrate forms a flowable oxide skin(coating), to fill described groove completely;
In step 207, described silicon substrate forms a photoresist oxidant layer, and photoresist oxidant layer described in etch-back;
In a step 208, remove not by the oxide skin(coating) of described photoresist oxidant layer covering;
In step 209, remove described photoresist oxidant layer, and remove the remaining oxide skin(coating) be positioned in described the first side wall body and the second sidewall bodies;
In step 210, described second sidewall bodies is removed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (14)
1. a manufacture method for FinFET, comprising:
Silicon substrate is provided, and on described silicon substrate, forms a laying and a hard mask layer successively;
Graphical described silicon substrate, and etch described silicon substrate to form the Fin of described FinFET;
Described silicon substrate forms gate stack structure, etches described gate stack structure to form the grid of described FinFET, and form the first side wall body in the both sides of described grid;
Form the second sidewall bodies in the both sides of described Fin, wherein, the width of described the first side wall body is greater than the half sum of the width of described second sidewall bodies and the width of described Fin;
Etch described silicon substrate, form a groove with the below of the source/drain region at described Fin;
Described silicon substrate forms a flowable oxide skin(coating), to fill described groove completely;
Described silicon substrate is formed a photoresist oxidant layer, and photoresist oxidant layer described in etch-back;
Remove not by the oxide skin(coating) of described photoresist oxidant layer covering;
Remove described photoresist oxidant layer, and remove the remaining oxide skin(coating) be positioned in described the first side wall body and the second sidewall bodies;
Remove described second sidewall bodies.
2. method according to claim 1, is characterized in that, the material of described laying is oxide.
3. method according to claim 1, is characterized in that, the material of described hard mask layer is silicon nitride.
4. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described gate stack structure.
5. the method according to claim 1 or 4, is characterized in that, described gate stack structure comprises the high-k dielectric layer, gate material layers and the cover layer that stack gradually from bottom to top.
6. method according to claim 1, is characterized in that, the material of described the first side wall body and described second sidewall bodies is silicon nitride.
7. method according to claim 1, is characterized in that, adopts the technique of first anisotropic etching isotropic etching again to etch described silicon substrate to form described groove.
8. the method according to claim 1 or 7, is characterized in that, the degree of depth of described groove is greater than the half sum of the width of described second sidewall bodies and the width of described Fin but is less than the width of described the first side wall body.
9. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described oxide skin(coating).
10. method according to claim 1, is characterized in that, described etch-back is until stop when making described photoresist oxidant layer only cover the oxide skin(coating) being positioned at described Fin both sides.
11. methods according to claim 1, is characterized in that, adopt wet etching process to remove not by the oxide skin(coating) of described photoresist oxidant layer covering.
12. methods according to claim 1, is characterized in that, adopt wet etching process to remove remaining oxide skin(coating).
13. methods according to claim 1, is characterized in that, adopt wet etching process to remove described second sidewall bodies.
14. methods according to claim 1, it is characterized in that, after described second sidewall bodies of removal, also comprise following processing step: expansion area is injected, form clearance wall structure, source/drain region is injected, form self-aligned silicide, form contact hole and metal interconnecting wires.
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| CN103972103B (en) * | 2014-04-28 | 2017-01-18 | 上海华力微电子有限公司 | Photo-etching alignment improved gate separating method |
| US9865595B1 (en) * | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
| DE102018114209A1 (en) * | 2017-07-31 | 2019-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SOURCE AND DRAIN STRUCTURE WITH A REDUCED CONTACT RESISTANCE AND IMPROVED MOBILITY |
| US10510875B2 (en) | 2017-07-31 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
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| CN101097956A (en) * | 2006-06-29 | 2008-01-02 | 国际商业机器公司 | Finfet structure and method for fabricating the same |
| CN102034714A (en) * | 2009-10-07 | 2011-04-27 | 格罗方德半导体公司 | Methods for forming isolated fin structures on bulk semiconductor material |
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| JP2009021503A (en) * | 2007-07-13 | 2009-01-29 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
| US20090072279A1 (en) * | 2007-08-29 | 2009-03-19 | Ecole Polytechnique Federale De Lausanne (Epfl) | Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (PI-MOS) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101097956A (en) * | 2006-06-29 | 2008-01-02 | 国际商业机器公司 | Finfet structure and method for fabricating the same |
| CN102034714A (en) * | 2009-10-07 | 2011-04-27 | 格罗方德半导体公司 | Methods for forming isolated fin structures on bulk semiconductor material |
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Effective date of registration: 20170531 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: SMIC new IC technology research and development (Shanghai) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |