CN103177963A - Manufacturing method of Fin FET (field-effect transistor) device - Google Patents
Manufacturing method of Fin FET (field-effect transistor) device Download PDFInfo
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- CN103177963A CN103177963A CN201110434023XA CN201110434023A CN103177963A CN 103177963 A CN103177963 A CN 103177963A CN 201110434023X A CN201110434023X A CN 201110434023XA CN 201110434023 A CN201110434023 A CN 201110434023A CN 103177963 A CN103177963 A CN 103177963A
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Abstract
The invention provides a manufacturing method of a Fin FET device. The method comprises providing a silicon substrate, and etching the silicon substrate to form the Fin of the Fin FET device; forming the grid electrode of the Fin FET device on the silicon substrate, and forming a first sidewall body at both sides of the grid electrode; forming a second sidewall body on both sides of the Fin; forming a groove under the source/drain region of the Fin; forming a flowing oxide layer on the silicon substrate to completely fill the groove; forming a photoresist layer on the silicon substrate, and etching back the photoresist layer; removing the oxide layer portion which is not covered by the photoresist layer; removing the photoresist layer, and removing the residual oxide layer on the first sidewall body and the second sidewall body; and removing the second sidewall body. According to the manufacturing method of the Fin FET device, a buried oxide layer can be formed between the source region and the drain region of the Fin to achieve a good isolation among the Fin, and the manufacturing cost can be reduced simultaneously.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of manufacture method with FinFET device of minor insulation body silicon-on.
Background technology
Existing complementary metal oxide semiconductors (CMOS) (CMOS) transistor is two-dimentional, and along with constantly dwindling of channel dimensions, the problem relevant with short-channel effect more and more is difficult to overcome.Therefore, chip manufacturer is developing the transistor of the three-dimensional with higher effect, fin formula field effect transistor (FinFET) for example, and it can adapt to the scaled requirement of device size better.
The method of existing formation FinFET generally includes following processing step: the formation of the formation → contact hole of the selective growth → source in the formation → source of the formation of the formation → sidewall of the formation of fin (Fin) → well region injection → grid → expansion area injection → sidewall/drain region/drain region injection → self-aligned silicide and other front end operation.In above-mentioned processing step, fin (Fin) be formed with two kinds of methods.A kind of method is: directly etch Fin on silicon substrate, then on silicon substrate deposition oxide to isolate described Fin; The shortcoming of the method is: because described Fin has very large depth-width ratio, thereby the formation oxide skin(coating) is very difficult between described Fin, and effect neither be fine.Another kind method is: first form a silicon oxide layer to form silicon-on-insulator (SOI) structure on silicon substrate, and epitaxial growth one silicon layer on described silicon on insulated substrate then, the described silicon layer of etching is to form described Fin; The shortcoming of the method is: manufacturing cost is very high, and simultaneously the thermal diffusivity of described silicon oxide layer is poor than silicon substrate, can cause the heat in raceway groove can not be effectively lost, causes temperature to raise, and affects mobility, and device performance is had negative effect.
Therefore, need to propose a kind of method, to address the above problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of FinFET device, comprising: silicon substrate is provided, and forms successively a laying and a hard mask layer on described silicon substrate; Graphical described silicon substrate, and the described silicon substrate of etching is to form the Fin of described FinFET device; Form gate stack structure on described silicon substrate, the described gate stack structure of etching to be forming the grid of described FinFET device, and forms the first side wall body in the both sides of described grid; Both sides at described Fin form the second sidewall bodies; The described silicon substrate of etching is to form a groove below source/drain region of described Fin; Form a flowable oxide skin(coating) on described silicon substrate, to fill described groove fully; Form a photoresist layer on described silicon substrate, and the described photoresist layer of etch-back; Remove the oxide skin(coating) that is not covered by described photoresist layer; Remove described photoresist layer, and remove the remaining oxide skin(coating) that is positioned on described the first side wall body and the second sidewall bodies; Remove described the second sidewall bodies.
Further, the material of described laying is oxide.
Further, the material of described hard mask layer is silicon nitride.
Further, adopt chemical vapor deposition method to form described gate stack structure.
Further, described gate stack structure comprises high K medium layer, gate material layers and the cover layer that stacks gradually from bottom to top.
Further, the material of described the first side wall body and described the second sidewall bodies is silicon nitride.
Further, the width of described the first side wall body is greater than half sum of the width of the width of described the second sidewall bodies and described Fin.
Further, adopt first anisotropic etching the more described silicon substrate of technique etching of isotropic etching to form described groove.
Further, the degree of depth of described groove is greater than half sum of the width of the width of described the second sidewall bodies and described Fin but less than the width of described the first side wall body.
Further, adopt chemical vapor deposition method to form described oxide skin(coating).
Further, described etch-back is until stop when described photoresist layer only being covered be positioned at the oxide skin(coating) of described Fin both sides.
Further, adopt wet etching process to remove the oxide skin(coating) that is not covered by described photoresist layer.
Further, adopt wet etching process to remove remaining oxide skin(coating).
Further, adopt wet etching process to remove described the second sidewall bodies.
Further, after removing described the second sidewall bodies, also comprise following processing step: clearance wall structure is injected, formed in the expansion area, source/drain region is injected, formed self-aligned silicide, forms contact hole and metal interconnecting wires.
The present invention also provides a kind of FinFET device, and described FinFET device has a minor insulation body silicon-on that is positioned at below, source/drain region, and described minor insulation body silicon-on adopts said method to form.
According to the present invention, can be in the source of fin (Fin)/drain region forms the buried oxide layer to realize the good isolation between described Fin, channel region due to described Fin does not form the buried oxide layer and does not need the new silicon layer of epitaxial growth on described buried oxide layer simultaneously, thereby can reduce manufacturing cost.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 J is the schematic cross sectional view of each step of the manufacture method of the FinFET device with minor insulation body silicon-on that proposes of the present invention;
Fig. 2 is the flow chart of the manufacture method of the FinFET device with minor insulation body silicon-on that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and be implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that the manufacture method of the FinFET device with minor insulation body silicon-on that explaination the present invention proposes in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, the detailed step of the manufacture method of the FinFET device with minor insulation body silicon-on that the present invention proposes is described with reference to Figure 1A-Fig. 1 J and Fig. 2.
With reference to Figure 1A-Fig. 1 J, wherein show the schematic cross sectional view of each step of the manufacture method of the FinFET device with minor insulation body silicon-on that the present invention proposes.
At first, as shown in Figure 1A, provide silicon substrate 100, adopt chemical vapor deposition method to form successively a laying 102 and a hard mask layer 103 on described silicon substrate 100; The material of described laying 102 is oxide, and as silica, the material of described hard mask layer 103 is silicon nitride.Then, graphical described silicon substrate 100, and the described silicon substrate 100 of etching is to form fin (Fin) 101.
Then, as shown in Figure 1B, adopt chemical vapor deposition method to form gate stack structure 104 on described silicon substrate 100, to cover described fin (Fin) 101.Described gate stack structure 104 comprises high K medium layer, gate material layers and the cover layer that stacks gradually from bottom to top.The material of described high K medium layer can comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia and aluminium oxide.The material of described gate material layers can comprise polysilicon.Described tectal material can comprise titanium nitride and tantalum nitride.
Next, the described gate stack structure 104 of etching is to form the grid of FinFET device.Then, form the first side wall body 105 in the both sides of described grid, the material of described the first side wall body 105 is silicon nitride.
Then, as shown in Fig. 1 C, form the second sidewall bodies 106 in the both sides of described fin (Fin) 101, the material of described the second sidewall bodies 106 is silicon nitride.Need to prove, the width of described the first side wall body 105 should be greater than half sum of the width of the width of described the second sidewall bodies 106 and described fin (Fin) 101, and is not etched to guarantee the silicon substrate below the grid of FinFET device described in following etching process.
Then, as shown in Fig. 1 D, adopt the first anisotropic etching described silicon substrate 100 of technique etching of isotropic etching again, form a groove 107 with the below in the source/drain region of described fin (Fin) 101.The degree of depth of described groove 107 is greater than half sum of the width of the width of described the second sidewall bodies 106 and described fin (Fin) 101 but less than the width of described the first side wall body 105, with the silicon substrate of the grid below of the described FinFET device of silicon substrate not etching simultaneously of the source of guaranteeing to etch away fully described fin (Fin) 101/below, drain region.
Then, as shown in Fig. 1 E, adopt chemical vapor deposition method to form a flowable oxide skin(coating) 108 on described silicon substrate 100, to fill described groove 107 fully.Because this technique is non-conformal gas-phase deposition, thereby the described oxide skin(coating) that forms on the side of described the first side wall body 105 and described the second sidewall bodies 106 is very thin.
Then, as shown in Fig. 1 F, adopt spin coating proceeding to form a photoresist layer 109 on described silicon substrate 100, and the described photoresist layer 109 of etch-back, so that described photoresist layer 109 only covers the oxide skin(coating) 108 that is positioned at described fin (Fin) 101 both sides.
Then, as shown in Fig. 1 G, adopt wet etching process to remove the oxide skin(coating) 108 that is not covered by described photoresist layer 109.The etchant of described wet etching process is the hydrofluoric acid of dilution.
Then, as shown in Fig. 1 H, remove described photoresist layer 109, the method that can adopt those skilled in the art to have the knack of is completed this step.
Then, as shown in Fig. 1 I, adopt wet etching process to remove the remaining oxide skin(coating) 108 that is positioned on described the first side wall body and the second sidewall bodies.The etchant of described wet etching process is the hydrofluoric acid of dilution.Need to prove, can according to actual needs, control the removal amount of described remaining oxide skin(coating) 108.
Then, as shown in Fig. 1 J, adopt wet etching process to remove described the second sidewall bodies 106.The etchant of described wet etching process is hot phosphoric acid.
So far, whole processing steps of method enforcement have according to an exemplary embodiment of the present invention been completed, next, can complete by subsequent technique the making of whole FinFET device, described subsequent technique and traditional FinFET device manufacturing process are identical, and described subsequent technique includes but not limited to that clearance wall structure is injected, formed in the expansion area, source/drain region is injected, formed self-aligned silicide, forms contact hole and metal interconnecting wires.According to the present invention, can be in the source of fin (Fin)/drain region forms the buried oxide layer to realize the good isolation between described Fin, channel region due to described Fin does not form the buried oxide layer and does not need the new silicon layer of epitaxial growth on described buried oxide layer simultaneously, thereby can reduce manufacturing cost.
With reference to Fig. 2, wherein show the flow chart of the manufacture method of the FinFET device with minor insulation body silicon-on that the present invention proposes, be used for schematically illustrating the flow process of whole manufacturing process.
In step 201, silicon substrate is provided, and forms successively a laying and a hard mask layer on described silicon substrate;
In step 202, graphical described silicon substrate, and the described silicon substrate of etching is to form the Fin of FinFET device;
In step 203, form gate stack structure on described silicon substrate, the described gate stack structure of etching to be forming the grid of FinFET device, and forms the first side wall body in the both sides of described grid;
In step 204, form the second sidewall bodies in the both sides of described Fin;
In step 205, the described silicon substrate of etching is to form a groove below source/drain region of described Fin;
In step 206, form a flowable oxide skin(coating) on described silicon substrate, to fill described groove fully;
In step 207, form a photoresist layer on described silicon substrate, and the described photoresist layer of etch-back;
In step 208, remove the oxide skin(coating) that is not covered by described photoresist layer;
In step 209, remove described photoresist layer, and remove the remaining oxide skin(coating) that is positioned on described the first side wall body and the second sidewall bodies;
In step 210, remove described the second sidewall bodies.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. the manufacture method of a FinFET device comprises:
Silicon substrate is provided, and forms successively a laying and a hard mask layer on described silicon substrate;
Graphical described silicon substrate, and the described silicon substrate of etching is to form the Fin of described FinFET device;
Form gate stack structure on described silicon substrate, the described gate stack structure of etching to be forming the grid of described FinFET device, and forms the first side wall body in the both sides of described grid;
Both sides at described Fin form the second sidewall bodies;
The described silicon substrate of etching is to form a groove below source/drain region of described Fin;
Form a flowable oxide skin(coating) on described silicon substrate, to fill described groove fully;
Form a photoresist layer on described silicon substrate, and the described photoresist layer of etch-back;
Remove the oxide skin(coating) that is not covered by described photoresist layer;
Remove described photoresist layer, and remove the remaining oxide skin(coating) that is positioned on described the first side wall body and the second sidewall bodies;
Remove described the second sidewall bodies.
2. method according to claim 1, is characterized in that, the material of described laying is oxide.
3. method according to claim 1, is characterized in that, the material of described hard mask layer is silicon nitride.
4. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described gate stack structure.
5. according to claim 1 or 4 described methods, is characterized in that, described gate stack structure comprises high K medium layer, gate material layers and the cover layer that stacks gradually from bottom to top.
6. method according to claim 1, is characterized in that, the material of described the first side wall body and described the second sidewall bodies is silicon nitride.
7. method according to claim 1, is characterized in that, the width of described the first side wall body is greater than half sum of the width of the width of described the second sidewall bodies and described Fin.
8. method according to claim 1, is characterized in that, adopt first anisotropic etching the more described silicon substrate of technique etching of isotropic etching to form described groove.
9. according to claim 1 or 8 described methods, is characterized in that, the degree of depth of described groove is greater than half sum of the width of the width of described the second sidewall bodies and described Fin but less than the width of described the first side wall body.
10. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described oxide skin(coating).
11. method according to claim 1 is characterized in that, described etch-back is until stop when described photoresist layer only being covered be positioned at the oxide skin(coating) of described Fin both sides.
12. method according to claim 1 is characterized in that, adopts wet etching process to remove the oxide skin(coating) that is not covered by described photoresist layer.
13. method according to claim 1 is characterized in that, adopts wet etching process to remove remaining oxide skin(coating).
14. method according to claim 1 is characterized in that, adopts wet etching process to remove described the second sidewall bodies.
15. method according to claim 1, it is characterized in that, after removing described the second sidewall bodies, also comprise following processing step: clearance wall structure is injected, formed in the expansion area, source/drain region is injected, formed self-aligned silicide, forms contact hole and metal interconnecting wires.
16. a FinFET device is characterized in that, described FinFET device has a minor insulation body silicon-on that is positioned at below, source/drain region, and described minor insulation body silicon-on adopts, and in claim 1-14, the described method of any one forms.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103972103A (en) * | 2014-04-28 | 2014-08-06 | 上海华力微电子有限公司 | Photo-etching alignment improved gate separating method |
| CN108231683A (en) * | 2016-12-14 | 2018-06-29 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacturing method |
| CN109326645A (en) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacturing method |
| US11545562B2 (en) | 2017-07-31 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
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| US20090014802A1 (en) * | 2007-07-13 | 2009-01-15 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
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| CN102034714A (en) * | 2009-10-07 | 2011-04-27 | 格罗方德半导体公司 | Methods for forming isolated fin structures on bulk semiconductor material |
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| CN101097956A (en) * | 2006-06-29 | 2008-01-02 | 国际商业机器公司 | Finfet structure and method for fabricating the same |
| US20090014802A1 (en) * | 2007-07-13 | 2009-01-15 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972103A (en) * | 2014-04-28 | 2014-08-06 | 上海华力微电子有限公司 | Photo-etching alignment improved gate separating method |
| CN103972103B (en) * | 2014-04-28 | 2017-01-18 | 上海华力微电子有限公司 | Photo-etching alignment improved gate separating method |
| CN108231683A (en) * | 2016-12-14 | 2018-06-29 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacturing method |
| CN109326645A (en) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacturing method |
| CN109326645B (en) * | 2017-07-31 | 2022-04-01 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| US11545562B2 (en) | 2017-07-31 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
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Effective date of registration: 20170531 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: SMIC new IC technology research and development (Shanghai) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |