CN108470685B - Nanowire structure and manufacturing method thereof - Google Patents
Nanowire structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN108470685B CN108470685B CN201810290683.7A CN201810290683A CN108470685B CN 108470685 B CN108470685 B CN 108470685B CN 201810290683 A CN201810290683 A CN 201810290683A CN 108470685 B CN108470685 B CN 108470685B
- Authority
- CN
- China
- Prior art keywords
- fin
- forming
- nanowire
- opening
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 129
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 84
- 230000008569 process Effects 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000003647 oxidation Effects 0.000 claims abstract description 37
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 5
- 230000036961 partial effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910005898 GeSn Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
According to the nanowire structure and the manufacturing method thereof provided by the embodiment of the invention, the fin is formed on the substrate, the notches are correspondingly arranged on the two side walls of the fin, then the opening is formed in the middle area of the fin, the thickness of the fin at the notch is smaller due to the existence of the notch, in the subsequent process of utilizing the opening to carry out an oxidation process, the fin at the thinnest notch is completely oxidized firstly, but the fin at the non-notch is not completely oxidized, and after the oxide is removed, the fin which is not completely oxidized is remained, so that the nanowire is formed in the opening.
Description
Technical Field
The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a nanowire structure and a manufacturing method thereof.
Background
With the development of very large scale integrated circuits, the feature size of the device is continuously reduced, the integration level is continuously improved, the conventional planar MOS device is difficult to continuously reduce the critical size, the short channel effect is more and more significant, and the short channel effect becomes a dominant factor influencing the performance of the device.
The nanowire device is one of the solutions of the existing MOS device below 7nm, the nanowire structure is used as a channel, and the nanowire structure is completely surrounded by a grid electrode, so that the nanowire device has good grid control capability, the device has stronger driving current, and the short channel effect is effectively inhibited. At present, how to manufacture a nanowire structure and improve the compatibility with the existing process are key problems in the application of nanowire devices.
In addition, with the continuous improvement of circuit performance, the power consumption is also larger and larger, and the increase of the power consumption brings many disadvantages, such as packaging, heat dissipation, cost, reliability and the like, so that the reduction of the power consumption of the device, especially the static power consumption, is another key problem in the application of the nanowire device.
Disclosure of Invention
Accordingly, the present invention is directed to at least one of the above problems, and provides a nanowire structure and a method for fabricating the same, which is compatible with the conventional processes.
In order to achieve the purpose, the invention has the following technical scheme:
a method of fabricating a nanowire structure, comprising:
providing a semiconductor substrate;
forming a fin on the semiconductor substrate, wherein notches are correspondingly arranged on two side walls of the fin, and the notches extend from one end to the other end of the side wall of the fin;
covering both ends of the fin to form an opening in the middle of the fin;
forming a nanowire in the opening, the forming the nanowire comprising: performing an oxidation process until part of the fin in the area where the notch is located in the opening is completely oxidized; and removing the oxidized oxide to form the nanowire in the opening.
Optionally, forming a fin on the semiconductor substrate comprises: performing one or repeated multiple combined etching processes, wherein each combined etching process comprises the following steps:
etching the semiconductor substrate by adopting an anisotropic etching process to form a vertical part of the fin;
forming a protective layer on the surface of the formed fin;
and continuously etching the semiconductor substrate by adopting an isotropic etching process to continuously form the fin with partial height.
Optionally, covering both ends of the fin to form an opening in the middle of the fin, comprising:
forming a dummy gate on the fin in the middle of the fin, forming a side wall on the side wall of the dummy gate, and forming covering layers covering the fins on two sides of the dummy gate;
and removing the dummy gate to form an opening.
Optionally, after forming the sidewall on the dummy gate and before forming the capping layer, the method further includes:
forming source and drain regions in the fins on two sides of the dummy gate;
after forming the nanowire, further comprising:
a gate region is formed in the opening surrounding the nanowire.
Optionally, forming source and drain regions on the fins on both sides of the dummy gate includes:
forming a sunken area on the fins on two sides of the dummy gate through an etching process;
and forming a source drain region with stress in the recessed region by a selective epitaxial growth process, wherein for a PMOS device, the material of the source drain region provides compressive stress, and for an NMOS device, the material of the source drain region provides tensile stress.
Optionally, the semiconductor substrate comprises a plurality of regions; the forming of the nanowire in the opening includes: and respectively forming nanowires with different apertures in the openings on the different regions, wherein in each step of forming the nanowire, the fin in only one region is exposed by the opening of one region, and different oxidation parameters are adopted in the oxidation process so as to enable the transverse widths of the parts of the fin which are not oxidized to be different, so that the nanowires with different apertures are formed when the oxidized oxide is removed, wherein the oxidation parameters comprise one or more of time, temperature or pressure of the oxidation process.
A nanowire structure, comprising:
a semiconductor substrate;
a support on the semiconductor substrate;
the nanowire is arranged between the supporting bodies, the supporting bodies are made of semiconductor materials the same as the nanowire, notches are correspondingly formed in two side walls of the supporting bodies, the notches extend from one end of the side walls of the supporting bodies to the other end of the side walls of the supporting bodies, and the extending direction of the notches is the length direction of the nanowire.
Optionally, the nanowire is one or more; when the nanowires are multiple, the nanowires are spaced and stacked along the vertical direction of the substrate.
Optionally, the semiconductor substrate comprises a plurality of regions, the nanowires of each region having a different pore size.
A nanowire structure, comprising:
a semiconductor substrate having a plurality of regions;
the nanowire and source and drain regions at two ends of the nanowire are formed on the substrate of each region, the source and drain regions have stress, the nanowire is supported by the source and drain regions, and the nanowire in each region has different apertures.
According to the nanowire structure and the manufacturing method thereof provided by the embodiment of the invention, the fin is formed on the substrate, the notches are correspondingly arranged on the two side walls of the fin, then the opening is formed in the middle area of the fin, the thickness of the fin at the notch is smaller due to the existence of the notch, in the subsequent process of utilizing the opening to carry out an oxidation process, the fin at the thinnest notch is completely oxidized firstly, but the fin at the non-notch is not completely oxidized, and after the oxide is removed, the fin which is not completely oxidized is remained, so that the nanowire is formed in the opening. The method can utilize the existing semiconductor manufacturing process, is easy to realize, and has good compatibility with the existing process.
Furthermore, the back gate process of the existing three-dimensional fin device can be adopted, the nanowire device is integrated while the nanowire is formed, the manufacturing difficulty of the nanowire is reduced, and meanwhile, the manufacturing of the nanowire device is realized by utilizing the existing process, so that the mass production of the nanowire device becomes possible.
Furthermore, when the nano wires are formed, different oxidation processes can be adopted in different areas, so that the nano wires with different apertures can be formed, and the nano wires with different apertures form devices with different thresholds.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a flow chart of a method of fabricating a nanowire structure according to an embodiment of the invention;
fig. 2 shows a schematic top view after forming a fin according to a manufacturing method of an embodiment of the invention;
fig. 3A-15B are schematic structural diagrams illustrating a process of forming a nanowire structure according to an embodiment of the present invention, wherein a is a cross-sectional view along AA in fig. 2, and B is a cross-sectional view along BB in fig. 2.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, as the feature size of the device is continuously reduced, the nanowire device becomes a development direction of the three-dimensional device, and how to implement the nanowire structure and the device is a key issue in the application thereof, for this reason, referring to fig. 1, the embodiment of the present application provides a method for manufacturing the nanowire structure, including:
providing a semiconductor substrate;
forming a fin on the semiconductor substrate, wherein notches are correspondingly arranged on two side walls of the fin, and the notches extend from one end to the other end of the side wall of the fin;
covering both ends of the fin to form an opening in the middle of the fin;
forming a nanowire in the opening, the forming the nanowire comprising: performing an oxidation process until part of the fin in the area where the notch is located in the opening is completely oxidized; and removing the oxidized oxide to form the nanowire in the opening.
It will be appreciated that this open region exposes a portion of the fin, which is the channel region where the nanowire is located, i.e., the target region for forming the nanowire.
According to the method, a fin is formed on a substrate, notches are correspondingly formed in two side walls of the fin, then an opening is formed in the middle area of the fin, due to the existence of the notches, the thickness of the fin at the notch is smaller, in the subsequent process of utilizing the opening to conduct an oxidation process, the fin at the thinnest notch is completely oxidized firstly, the fin at the non-notch is not completely oxidized, and after oxide is removed, the fin which is not completely oxidized is reserved, so that a nanowire is formed in the opening. The method can utilize the existing semiconductor manufacturing process, is easy to realize, and has good compatibility with the existing process.
For a better understanding of the technical solutions and effects of the present invention, the following detailed description of specific embodiments will be given with reference to the accompanying drawings.
Referring to fig. 1, in step S01, the semiconductor substrate 100 may be provided as shown in fig. 2 and fig. 3A-6A.
In the embodiment of the present invention, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) substrate, or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator), or the like. The semiconductor substrate 100 may have n-type or p-type doping therein.
In the present embodiment, the semiconductor substrate 100 is a bulk silicon substrate.
In step S02, a fin 110 is formed on the semiconductor substrate 100, wherein notches 1101 are correspondingly disposed on two side walls of the fin 110, and the notches 1101 extend from one end to the other end of the side walls of the fin 110, as shown in fig. 2 and fig. 6A and 6B.
In the illustration of this embodiment, fig. 2, fig. 6A, and fig. 6B are schematic diagrams after forming the fin, among others. Fig. 2 is a schematic top view, fig. 6A is a cross-sectional view along AA in fig. 2, fig. 6B is a cross-sectional view along BB in fig. 2, and in the subsequent fig. 7A-15B, a top view with corresponding steps omitted, and only cross-sectional views in different directions of the subsequent steps are shown, the directions of the cross-sections being as shown in fig. 2, wherein the direction of the cross-section in the diagram denoted by a is the direction of AA in fig. 2, and the direction of the cross-section in the diagram denoted by B is the direction of BB in fig. 2.
In this step, a fin 110 having a notch 1101 is formed, and the notch 110 is correspondingly disposed on both sides of the fin and extends from one end of the fin to the other end, that is, the notch is symmetrically disposed at substantially the same position on both sides of the fin and extends through the entire fin along the length direction of the fin, so that the lateral thicknesses of the fin at different heights are different. In the embodiment of the present invention, the number of the notches is one or more, and when a plurality of notches are present, the notches may be uniformly arranged in the height direction of the fin, and vertical portions 114 having a substantially straight appearance may be present between and above the notches.
The shape of the notch formed may vary depending on the manufacturing process, and in embodiments of the invention, the notch may be substantially concave, i.e., the depth of the notch may be slightly greater in the middle than at the ends of the notch.
In the present embodiment, the fin provided with the notch may be formed by the following method. Specifically, first, in step S021, the semiconductor substrate 100 is etched by using an anisotropic etching process to form a vertical portion 1101 of a fin, which is shown in fig. 3A.
A mask layer 102, which may be, for example, silicon oxide or silicon nitride or a stack thereof, may be formed on a substrate, and then plasma etching is performed to select a suitable plasma etchant to perform anisotropic etching on the substrate 100, where in the anisotropic etching, etching is mainly performed along a direction perpendicular to the substrate surface, and a structure formed after etching is relatively uniform in morphology, that is, a fin portion having a straight morphology is used as a vertical portion 1101 of the fin, as shown in fig. 3A.
Then, in step S022, a protective layer 103 is formed on the surface of the formed fin, as shown with reference to fig. 4A.
An appropriate protective layer 103 may be used according to specific needs so that when the substrate 100 is etched further, the already formed fins are not etched away. In this embodiment, a special plasma, such as oxygen plasma, may be used to protect the sidewalls of the formed fins.
Then, in step S023, the semiconductor substrate 100 is continuously etched using an isotropic etching process to continuously form the groove portion 1102 of the fin, as shown with reference to fig. 5A.
Plasma etching can be adopted, a proper plasma etching agent is selected to carry out isotropic etching on the substrate, the substrate is continuously etched, and in the isotropic etching, the etching is carried out along all directions, so that the etching is carried out towards the side surface while the etching is carried out downwards, and therefore the groove part 1102 of the fin is formed.
Thus, a combined etching process is completed, which includes the above steps S021 to S023, the fin having one groove may be formed by the combined etching process, and after repeating the etching process for a plurality of times, the mask layer 102 on the top of the fin and the protective layer on the sidewall are removed, and the fin having a plurality of notches 112 may be formed, and the portion above and between the notches is the vertical portion 114 of the fin, as shown in fig. 6A and 6B.
It is understood that in the first combining process, in step S022, the formed fins are the vertical portions 1101 of the first formed fin, and in the subsequent combining process, in step S022, the formed fins are the vertical portions of all the formed fins and the groove portions of the fins.
In forming the nanowire device, after the fins 110 are formed, an isolation structure 115, which may be a shallow trench isolation, may be formed between the fins, and the isolation structure 115 may be formed by depositing an isolation material, such as silicon oxide, and the like, and then performing an etching back, referring to fig. 7A and 7B.
In step S03, both ends of the fin 110 are covered to form an opening 126 in the middle of the fin 110, as shown with reference to fig. 11A and 11B.
The two ends of the fin 110 are covered by the cover layer, while the middle of the fin is exposed, i.e. an opening 126 is formed in the middle of the fin 110, the area of the fin in the opening being used for forming the nanowire.
In the process of forming the opening, a gate-last process of the fin gate device can be adopted, the nanowire structure and the nanowire device are realized by utilizing the existing process, a new process does not need to be developed, and the mass production of the nanowire structure and the nanowire device becomes possible.
Specifically, first, in step S031, a dummy gate 120 on the fin is formed in the middle of the fin 110, and a sidewall 122 is formed on the sidewall of the dummy gate 120, as shown in fig. 9A and 9B.
The dummy gate can comprise a dummy dielectric layer and a dummy gate, and the region where the dummy gate is located is a gate region of the final device. The dummy gate may be formed by sequentially depositing a dummy dielectric layer, such as silicon oxide, and a dummy gate, such as polysilicon, and then patterning the dummy gate by an etching technique, as shown in fig. 8A and 8B.
The sidewall 122 may be a single layer or a multi-layer structure, and may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials, combinations thereof, and/or other suitable materials. The spacers 122 may be formed by depositing a spacer material and then by an anisotropic etch process, as shown with reference to fig. 9A and 9B.
In the process of simultaneously integrating the nanowire devices, after forming the dummy gate, source and drain regions 124 may be formed in the fin 110 on both sides of the dummy gate in step S032, as shown with reference to fig. 10A and 10B.
Source and drain regions 124 may be formed by ion implantation or other suitable methods, and in order to improve carrier mobility of the device channel region, in this embodiment, a stressed source and drain region is epitaxially grown.
Specifically, first, a recess region may be formed on the fin 110 on both sides of the dummy gate through an etching process, for example, a dry etching process.
And forming a source drain region with stress in the recessed region through a selective epitaxial growth process, wherein for the PMOS device, the material of the source drain region provides compressive stress, and for the NMOS device, the material of the source drain region provides tensile stress.
In selective epitaxial growth, growth is performed only in the recess region, and thus, source and drain regions are formed in the recess region. In a specific embodiment, for an NMOS device, the lattice constant of the material grown in the source and drain regions may be smaller than the lattice constant of the material in the channel region, that is, the fin in the opening, and the source and drain regions provide tensile stress for the channel, thereby improving the mobility of carriers in the channel region, and when the fin is Si, the source and drain regions may be SiC; when the fin is Ge, the source and drain regions may be Si, SiGe, SiC or the like. For a PMOS device, the lattice constant of a material grown in a source drain region can be larger than that of a material grown in a channel region, the source drain region provides compressive stress for the channel, and therefore the mobility of carriers in the channel region is improved, and when a fin is Si, the source drain region can be SiGe, Ge, GeSn or a III-V material; when the fin is Ge, the source and drain regions may be GeSn or a III-V material, etc.
In step S033, a capping layer 130 is formed to cover the fins on both sides of the dummy gate 120, as shown with reference to fig. 10A and 10B.
The capping layer is used to protect the underlying fin during the formation of the opening and the formation of the nanowire in the opening, and the capping layer 130 may be an interlayer dielectric layer. The dielectric material, e.g. undoped silicon oxide (SiO), may be deposited by a suitable deposition method2) Doped silicon oxide (e.g., borosilicate glass, borophosphosilicate glass, etc.), nitridedSilicon (Si)3N4) Or other low-k dielectric material, and then planarized, such as CMP (chemical mechanical polishing), to form the capping layer 130.
In step S034, the dummy gate 120 is removed to form an opening 126, as shown with reference to fig. 11A and 11B.
The dummy gate 120 may be removed using a wet etch and/or a dry etch to form an opening 126 in the region of the original dummy gate 120 that exposes the fin.
At step S04, nanowires 150, 152 are formed in the openings 126, the forming nanowires including: performing an oxidation process until part of the fin in the area where the notch is located in the opening is completely oxidized; the oxidized oxide is removed to form a nanowire in the opening, as shown with reference to fig. 14A and 14B.
In the embodiment of the present invention, the fin 110 has the notch 112, as shown in fig. 11A and 11B, so that the fin in the notch region and the fin in the non-notch region have different thicknesses in the lateral direction, when the oxidation process is performed, the fin in the opening is oxidized, and the fin in the notch region is thinner, so that the fin is completely oxidized first, and at least part of the fin in the area where the notch is located is completely oxidized.
In this embodiment, when the nanowires are formed, different oxidation processes may be used in different regions, so that nanowires with different apertures may be formed, and nanowires with different apertures may form devices with different thresholds.
The semiconductor substrate may include a plurality of regions, each region for forming a nanowire device of a different threshold.
Specifically, forming the nanowire in the opening may include: and respectively forming nanowires with different apertures in the openings on the different regions, wherein in each step of forming the nanowire, the fin in only one region is exposed by the opening of one region, and different oxidation parameters are adopted in the oxidation process so as to enable the transverse widths of the parts of the fin which are not oxidized to be different, so that the nanowires with different apertures are formed when the oxidized oxide is removed, wherein the oxidation parameters comprise one or more of time, temperature or pressure of the oxidation process.
Specifically, in step S041, a shielding layer is formed in the openings of the other regions than the one region, as shown with reference to fig. 12A and 12B.
In step S042, an oxidation process is performed to completely oxidize the fin in the area where the trench is located in the opening of the area not covered by the shielding layer, and the oxide generated by the oxidation process is removed to form a nanowire structure with an aperture, and the shielding layer in another area is removed, as shown in fig. 13A and 13B.
In step S043, a shielding layer is formed in the openings of the other regions than the other region, as shown with reference to fig. 14A and 14B.
In step S044, another oxidation process is performed to completely oxidize the fin in the region where the trench is located in the opening of the another region, and the oxide generated by the another oxidation process in the another region is removed to form the nanowire structure with another aperture, and the shielding layer in the another region is removed, as shown in fig. 14A and 14B.
The above steps S043 and S044 are repeated until the nanowires are formed in all the regions and the pore diameters are different from each other.
In the above steps, the region where the shielding layer is not formed is to be subjected to an oxidation process, and a nanowire is formed, and the region where the shielding layer is formed is protected in the oxidation process without oxidation and formation of the nanowire, so that the nanowires with different apertures from the region are formed on different regions through formation of the shielding layer and the oxidation process for multiple times. In a specific oxidation process, the oxidation degree of the fin can be different by adjusting oxidation parameters including one or more of time, temperature or pressure of the oxidation process, so that the formed nanowires are nanowires with different pore diameters after the oxide is removed.
In the following, the nanowire with two different apertures formed on two different regions will be described as an example, and the two regions are respectively referred to as a first region and a second region. In this embodiment, the first shielding layer 140 is formed in the opening of the first region, as shown in fig. 12A and 12B.
Then, a first oxidation process is performed to completely oxidize the fin in the region where the trench is located in the opening of the second region, and the oxide generated by the first oxidation process in the second region is removed to form the first nanowire 150 having the first aperture, as shown in fig. 13A and 13B. The first masking layer 140 is then removed over the first area.
Then, a second shielding layer 142 is formed in the opening of the second region, as shown in fig. 14A and 14B.
Finally, a second oxidation process is performed to completely oxidize at least a portion of the fin in the area where the notch is located in the opening of the first region, and an oxide generated by the second oxidation process in the first region is removed to form a second nanowire 152 having a second aperture, as shown in fig. 14A and 14B. The first blocking layer 142 is then removed over the second area. Thus, two nanowires with different apertures are formed on the first region and the second region, and only two regions are taken as an example for illustration, it is understood that in other applications, there may be more regions, and nanowires with different apertures may be formed on different regions, respectively.
A gate region 160 surrounding the nanowires 150, 152 can then be formed in the opening, as shown with reference to fig. 15A and 15B, to form a nanowire device.
The gate region 160 includes a gate dielectric layer, which may be a high-k dielectric material (e.g., a material having a high dielectric constant compared to silicon oxide) or other suitable dielectric material, and a gate electrodeSuch as hafnium-based oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO, etc., the gate may be a metal gate, may be a one-layer or multi-layer structure, may include a metal material such as Ti, TiAl or polysilicon or a combination thereofx、TiN、TaNx、HfN、TiCx、TaCxAnd so on.
In this embodiment, the nanowire device with various apertures is integrated while the nanowire is formed by using the gate-last process of the conventional three-dimensional fin device, and meanwhile, the nanowire device is manufactured by using the conventional process, so that the mass production of the nanowire device becomes possible.
In addition, an embodiment of the present invention further provides a nanowire structure and a device formed by the above method, and as shown in fig. 15A and 15B, the nanowire structure includes:
a semiconductor substrate 100;
a support 110 on the semiconductor substrate 100;
the nanowire array comprises nanowires 150 and 152 between support bodies 110, the support bodies 110 and the nanowires 150 and 152 are made of the same semiconductor material, notches 112 are correspondingly formed in two side walls of the support bodies 110, the notches 112 extend from one end to the other end of the side walls of the support bodies 110, and the extending direction of the notches 112 is the length direction of the nanowires 150 and 152.
Wherein, the support 110 is the remaining part of the fin for forming the nanowire, and further forms a source drain region on the support, further comprising: and the source and drain regions 124 are arranged on the support body 110, and the source and drain regions 124 are arranged at two ends of the nanowire. Specifically, for example, the source and drain regions may be formed by doping, or the source and drain regions may be formed by epitaxial growth on the support, or the source and drain regions may be formed after etching and removing a portion of the support and performing epitaxy.
Further, the source drain regions 124 may be stressed epitaxial source drain regions, wherein the source drain regions provide compressive stress for PMOS devices and tensile stress for NMOS devices.
Further, the nanowires 150, 152 are one or more strips; when the nanowires 150, 152 are multiple, the nanowires 150, 152 are spaced apart from each other in a direction perpendicular to the substrate 100 and distributed in a stacked manner.
In the nanowire structure and the device formed by the above method, the support of the nanowire structures 150 and 152 is the portion at both ends of the fin, and thus, the nanowire structure has the same semiconductor material as the nanowire, and the notches formed on the fin are also reserved on both sides of the support. The nanowire formed is a channel region of a device, it can be understood that a source region and a drain region are located in support bodies on two sides of the channel region, the nanowire structure and the device in the embodiment of the present invention are formed by the above method, and for the description of each component, reference may be made to the description in the method, and details will not be described here.
In addition, the present application also provides a nanowire structure and a device, as shown with reference to fig. 15A and 15B, including:
a semiconductor substrate 100 having a plurality of regions;
In the nanowire structure of these embodiments, the source and drain regions 124 also support the nanowire, the source and drain regions are formed by epitaxial growth and have a stress effect on the nanowire, and nanowires with different apertures are formed in different regions, so that a multi-threshold device can be formed.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (5)
1. A method of fabricating a nanowire structure, comprising:
providing a semiconductor substrate;
forming a fin on the semiconductor substrate, wherein notches are correspondingly arranged on two side walls of the fin, and the notches extend from one end to the other end of the side wall of the fin;
covering both ends of the fin to form an opening in the middle of the fin;
forming a nanowire in the opening, the forming the nanowire comprising: and forming nanowires with different apertures in the openings on different regions respectively, wherein the apertures are determined according to the threshold values of the different regions, only the opening of one region exposes the fin in each step of forming the nanowire, different oxidation parameters are adopted in an oxidation process, so that the transverse widths of the parts of the fins which are not oxidized are different, and therefore, the nanowires with different apertures are formed when oxidized oxides are removed, and the oxidation parameters comprise one or more of time, temperature or pressure of the oxidation process.
2. The method of manufacturing of claim 1, wherein forming a fin on the semiconductor substrate comprises: performing one or repeated multiple combined etching processes, wherein each combined etching process comprises the following steps:
etching the semiconductor substrate by adopting an anisotropic etching process to form a vertical part of the fin;
forming a protective layer on the surface of the formed fin;
and continuously etching the semiconductor substrate by adopting an isotropic etching process to continuously form the fin with partial height.
3. The method of manufacturing of claim 1, wherein covering both ends of the fin to form an opening in a middle portion of the fin comprises:
forming a dummy gate on the fin in the middle of the fin, forming a side wall on the side wall of the dummy gate, and forming covering layers covering the fins on two sides of the dummy gate;
and removing the dummy gate to form an opening.
4. The method of claim 3, wherein after forming the sidewalls on the dummy gate and before forming the capping layer, further comprising:
forming source and drain regions on the fins on two sides of the dummy gate;
after forming the nanowire, further comprising:
a gate region is formed in the opening surrounding the nanowire.
5. The manufacturing method of claim 4, wherein forming source and drain regions on the fins on both sides of the dummy gate comprises:
forming a sunken area on the fins on two sides of the dummy gate through an etching process;
and forming a source drain region with stress in the recessed region by a selective epitaxial growth process, wherein for a PMOS device, the material of the source drain region provides compressive stress, and for an NMOS device, the material of the source drain region provides tensile stress.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810290683.7A CN108470685B (en) | 2018-03-30 | 2018-03-30 | Nanowire structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810290683.7A CN108470685B (en) | 2018-03-30 | 2018-03-30 | Nanowire structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108470685A CN108470685A (en) | 2018-08-31 |
| CN108470685B true CN108470685B (en) | 2022-02-01 |
Family
ID=63262675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810290683.7A Active CN108470685B (en) | 2018-03-30 | 2018-03-30 | Nanowire structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108470685B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411415B (en) * | 2018-09-07 | 2021-04-30 | 上海集成电路研发中心有限公司 | Method for forming semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110073842A1 (en) * | 2008-06-09 | 2011-03-31 | National Institue Of Advanced Industrial Science And Technology | Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor |
| CN103295903A (en) * | 2012-03-05 | 2013-09-11 | 中国科学院微电子研究所 | Method for manufacturing fin type semiconductor device with wrap gate structure |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104253048A (en) * | 2013-06-28 | 2014-12-31 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104425410A (en) * | 2013-08-26 | 2015-03-18 | 台湾积体电路制造股份有限公司 | Integrate circuit with nanowires |
-
2018
- 2018-03-30 CN CN201810290683.7A patent/CN108470685B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110073842A1 (en) * | 2008-06-09 | 2011-03-31 | National Institue Of Advanced Industrial Science And Technology | Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor |
| CN103295903A (en) * | 2012-03-05 | 2013-09-11 | 中国科学院微电子研究所 | Method for manufacturing fin type semiconductor device with wrap gate structure |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104253048A (en) * | 2013-06-28 | 2014-12-31 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104425410A (en) * | 2013-08-26 | 2015-03-18 | 台湾积体电路制造股份有限公司 | Integrate circuit with nanowires |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108470685A (en) | 2018-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106252231B (en) | Semiconductor device including fin structure and method of manufacturing the same | |
| KR101637718B1 (en) | Fin structure of semiconductor device | |
| CN106373997B (en) | Semiconductor device and method for manufacturing the same | |
| US10714585B2 (en) | Gate-all-around field-effect-transistor devices and fabrication methods thereof | |
| US11239345B2 (en) | Gate formation with varying work function layers | |
| US12094953B2 (en) | Semiconductor manufacturing | |
| EP3306665A2 (en) | Semiconductor structure and fabrication method thereof | |
| KR102429611B1 (en) | Method for fabricating semiconductor device | |
| CN107017296B (en) | Fin field effect transistor | |
| CN113782531A (en) | Semiconductor device including fin field effect transistor | |
| CN112530943A (en) | Semiconductor device and method for manufacturing the same | |
| US10811541B2 (en) | Semiconductor device having germanium containing active pattern and method for fabricating the same | |
| CN110034015B (en) | Method for forming nanowire fence device | |
| US9691903B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI696216B (en) | Semiconductor device and manufacturing method thereof | |
| TWI772935B (en) | Semiconductor devices and methods for manufacturing the same | |
| EP3208830A1 (en) | A method to improve ge channel interfacial layer quality for cmos finfet | |
| CN106972054B (en) | Semiconductor device and method for manufacturing the same | |
| CN108470685B (en) | Nanowire structure and manufacturing method thereof | |
| US12020950B2 (en) | Semiconductor structure and method for forming thereof | |
| CN106601793B (en) | Semiconductor device and manufacturing method thereof | |
| CN115249738A (en) | Semiconductor structure and forming method thereof | |
| CN114864578A (en) | Semiconductor device and method for manufacturing the same | |
| KR102610265B1 (en) | Semiconductor device and method of fabricating the same | |
| CN110729360A (en) | Nanotube device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |