CN108565218A - Surrounding gate nanowire field effect transistor and preparation method thereof - Google Patents
Surrounding gate nanowire field effect transistor and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a ring gate nanowire field effect transistor and a preparation method thereof. The preparation method comprises the following steps: s1, forming a fin structure on the substrate; s2, forming a first fin body isolated from the substrate by the fin structure, wherein the first fin body consists of a first region, a second region and a third region which are sequentially connected along the length direction; s3, oxidizing the second region in the first fin body partially to form a nanowire structure and an oxide layer wrapping the nanowire structure on the second region, and removing the oxide layer to expose the nanowire structure; s4, forming a gate stack structure around the periphery of the nanowire structure, and the method further comprises the steps of: source/drain electrodes are formed in the first region and the third region, and the source/drain electrodes are connected to both ends of the nanowire structure. The preparation method improves the grid control capability of the device, reduces the leakage current of the device, reduces the source-drain parasitic resistance of the device and improves the reliability of the device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of ring gate nano line field-effect transistor and its
Preparation method.
Background technology
With the continuous atrophy of device, it is special that traditional fin FET (FinFET) faces the subthreshold value seriously degenerated
Property, the Punchthrough leakage current that sharply increases and gate medium tunneling leakage, improve driveability and reduce system power dissipation to work
Make electrical parameter statistic fluctuation caused by the conflicting requirements and process variation of voltage (Statistical Fluctuations)
Etc. various severe challenges.
How leakage current to be reduced by optimised devices structure and manufacturing process and optimizes Sub-Threshold Characteristic, is still fin field
Effect transistor has to the technical barrier solved.
Invention content
The main purpose of the present invention is to provide a kind of ring gate nano line field-effect transistors and preparation method thereof, to solve
The higher problem of the leakage current of fin FET in the prior art.
To achieve the goals above, according to an aspect of the invention, there is provided a kind of ring gate nano line field effect transistor
The preparation method of pipe, includes the following steps：S1 forms fin structure on substrate；Fin structure is formed the be isolated with substrate by S2
One fin body, the first fin body are made of first area connected in sequence along its length, second area and third region；S3 makes
Second area is formed nano thread structure and wraps up the oxidation of nano thread structure by the second area partial oxidation in one fin body
Layer, removes removing oxide layer so that nano thread structure is exposed；S4 forms grid stacked structure around the periphery of nano thread structure, and, it prepares
Method is further comprising the steps of：Form source/drain in first area and third region, the two of source/drain and nano thread structure
End connection.
Further, step S1 includes following procedure：S11 sequentially forms the second separation layer, sacrificial layer and covers on substrate
Film layer；S12 removes partial sacrificial layer and mask layer, so that the second insulation surface of part is exposed using patterning process；S13,
Remaining mask layer is removed, and forms the first side wall for being covered in sacrificial layer both sides on the second separation layer；S14, removal are remaining
Sacrificial layer, and remove the second separation layer of part and section substrate, part corresponding with the first side wall by mask of the first side wall
Substrate convexes to form fin structure, while the both sides of fin structure are formed with opposite groove, and groove is prolonged by 1/3 height of fin structure
It extends at 2/3 height.
Further, the process for forming fin structure includes：The second separation layer of part is removed using anisotropic etch process
And section substrate, so that remaining substrate has bulge-structure；Using isotropic etching technique bulge-structure both sides shape
At groove；Section substrate below groove is located at using anisotropic etch process removal, has reeded fin structure to be formed.
Further, in step sl, form fin structure on substrate, at the same the both sides of fin structure be formed with it is opposite recessed
Slot, groove are extended to by 1/3 height of fin structure at 2/3 height, and step S2 includes following procedure：S21, by fin structure oxygen
Change, the position of the corresponding fin structure of further groove is fully oxidized so that fin structure forms independent first fin body and the second fin
Body, the first fin body are located at the second side of the fin body far from substrate；S22, deposition of insulative material, first is covered to be formed on substrate
First separation layer of fin body and the second fin body；S23 carries out planarization process to the first separation layer, so that the first separation layer and the
The upper surface flush of one fin body.
Further, between step S2 and step S3, preparation method is further comprising the steps of：From the table of the first separation layer
Face starts etching removal the first separation layer of part, so that part the first fin body is exposed；On remaining first separation layer formed across
The false grid of part the first fin body stack, and form the second side wall across part the first fin body in the both sides that false grid stack；Removal is false
Grid stack, and part the first fin body between the second side wall is second area.
Further, before the step of false grid of removal stack, source/drain is formed in first area and third region,
And source/drain and the both ends of the nano thread structure formed in step S3 is made to connect.
Further, before the step of making second area partial oxidation, step S3 further includes：From the table of the first separation layer
Face starts first separation layer of the etching removal between the second side wall, so that second area is completely exposed, it is preferred to use wet method
Etching technics removes the first separation layer of part, and the corrosive agent of more preferable wet-etching technology includes DHF.
Further, in step s3, removing oxide layer, the preferably corrosion of wet-etching technology are gone using wet-etching technology
Agent includes DHF.
Further, after the step of forming grid stacked structure, source/drain is formed in first area and third region
Pole, and source/drain and the both ends of the nano thread structure formed in step S3 is made to connect.
According to another aspect of the present invention, a kind of ring gate nano line field-effect transistor is provided, including：Substrate；First
Fin body is located on substrate, and the first fin body is by first area connected in sequence along its length, second area and third region group
At, and second area is nano thread structure, the section of nano thread structure is drops；First separation layer is set to substrate and
Between one fin body, for the first fin body to be isolated with substrate；Grid stacked structure is arranged around nano thread structure；And source/drain
Pole is located in first area and third region, and the both ends of source/drain and nano thread structure connect.
Further, ring gate nano line field-effect transistor further includes cover grid stacked structure both sides and across the first fin body
Second side wall.
It applies the technical scheme of the present invention, provides a kind of preparation method of ring gate nano line field-effect transistor, the system
In Preparation Method after forming fin structure, fin structure is formed to the first fin body being isolated with substrate, and the first fin body is by along length
Direction first area connected in sequence, second area and third region composition, then make the second area in the first fin body complete
It is exposed, second area is aoxidized, second area is formed into nano thread structure and wraps up the oxide layer of nano thread structure, removal
Oxide layer is so that nano thread structure is exposed, and forms the grid stacked structure around the nano thread structure, due in grid stacked structure
Grid four sides wrap up nano thread structure for forming trenches, to make the grid-control ability for improving device, device turn off
In the case of, the carrier in raceway groove will be completely depleted, this so that Punchthrough leakage current is inhibited well；Due to upper
It states the first fin body obtained in preparation method to be integrally kept completely separate with substrate, has completely cut off substrate direction leakage path, to reduce
The leakage current of device；Since only nano wire will be formed as the part of raceway groove in fin structure, to enable source/drain to tie up
Hold original form, on the one hand efficiently avoid short-channel effect, optimize Sub-Threshold Characteristic, at the same enable the device to have compared with
Low dead resistance；Also, it is formed since above-mentioned nano thread structure removes removing oxide layer after oxidation, so as to remove
The defective silicon of original surface band, the nano wire for making boundary defect greatly reduce, and newly being formed more they tend to smooth, reduction tip exception
Electric discharge, so that device reliability is improved.
Description of the drawings
The Figure of description for constituting the part of the present invention is used to provide further understanding of the present invention, and of the invention shows
Meaning property embodiment and its explanation are not constituted improper limitations of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 shows in the preparation method for the ring gate nano line field-effect transistor that the application embodiment is provided,
The matrix cross-sectional view after the second separation layer, sacrificial layer and mask layer is sequentially formed on substrate；
Fig. 2 shows removal partial sacrificial layer shown in FIG. 1 and mask layers, so that after the second insulation surface of part is exposed
Matrix cross-sectional view；
Fig. 3 shows removal remaining mask layer shown in Fig. 2, and is formed on the second separation layer and be covered in sacrificial layer two
Matrix cross-sectional view after first side wall of side；
Fig. 4 shows the matrix cross-sectional view after removing sacrificial layer shown in Fig. 3；
Fig. 5 shows the matrix cross-sectional view for being formed in matrix shown in Fig. 4 and having reeded fin structure；
Fig. 6, which is shown, aoxidizes fin structure shown in fig. 5, so that fin structure forms independent first fin body and the second fin body
Matrix cross-sectional view afterwards；
Fig. 7 shows the first separation layer to be formed and cover the first fin body and the second fin body shown in fig. 6, and makes part first
Matrix cross-sectional view after fin body is exposed；
Fig. 8 shows the matrix perspective view after forming the second side wall in matrix shown in Fig. 7；
Fig. 9 show make the second area in the first fin body shown in Fig. 7 completely it is exposed after matrix cross-section structure
Schematic diagram；
Figure 10, which is shown, aoxidizes second area shown in Fig. 9 to form the matrix section after nano thread structure and oxide layer
Structural schematic diagram；
Figure 11, which is shown, to be removed oxide layer shown in Fig. 10 so that the matrix cross-section structure after nano thread structure is exposed shows
It is intended to；And
Figure 12 shows a kind of perspective view for ring gate nano line field-effect transistor that embodiment of the present invention is provided.
Wherein, above-mentioned attached drawing includes the following drawings label：
10, substrate；110, fin structure；111, the first fin body；112, the second fin body；113, oxide layer；120, nanowire-junction
Structure；210, the second separation layer；220, sacrificial layer；230, mask layer；240, the first side wall；250, the second side wall；30, the first isolation
Layer；40, source/drain.
Specific implementation mode
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
It should be noted that term " first " in description and claims of this specification and above-mentioned attached drawing, "
Two " etc. be for distinguishing similar object, without being used to describe specific sequence or precedence.It should be appreciated that using in this way
Data can be interchanged in the appropriate case, so as to the embodiment of the present invention described herein.In addition, term " comprising " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing series of steps or unit
Process, method, system, product or equipment those of are not necessarily limited to clearly to list step or unit, but may include without clear
It is listing to Chu or for these processes, method, product or equipment intrinsic other steps or unit.
As described in background technology, how to be reduced in the prior art by optimised devices structure and manufacturing process
Leakage current simultaneously optimizes Sub-Threshold Characteristic, is still that fin FET has to the technical barrier solved.The invention of the present invention
People studies regarding to the issue above, it is proposed that a kind of preparation method of ring gate nano line field-effect transistor, including following step
Suddenly：S1 forms fin structure 110 on substrate 10；Fin structure 110 is formed the first fin body 111 being isolated with substrate 10 by S2, the
One fin body 111 is made of first area connected in sequence along its length, second area and third region, and above-mentioned length direction is
Refer to the extending direction of the first fin body 111；S3 keeps the second area in the first fin body 111 completely exposed, second area is aoxidized,
Second area is formed nano thread structure 120 and wraps up the oxide layer of nano thread structure 120, removing oxide layer is removed so that nanometer
Cable architecture 120 is exposed；S4 forms grid stacked structure around the periphery of nano thread structure 120, and, preparation method further includes following
Step：Source/drain is formed in first area and third region, source/drain 20 is connect with the both ends of nano thread structure 120.
Due to after forming fin structure in the preparation method of above-mentioned ring gate nano line field-effect transistor, by fin structure shape
At the first fin body being isolated with substrate, and the first fin body is by first area connected in sequence along its length, second area and
Three regions form, and then make the second area in the first fin body completely exposed, second area is aoxidized, second area is formed
Nano thread structure and the oxide layer for wrapping up nano thread structure remove removing oxide layer so that nano thread structure is exposed, and is formed and surround
Nano thread structure for forming trenches is wrapped up at the grid stacked structure of the nano thread structure, the grid four sides in grid stacked structure,
So as to make the grid-control ability for improving device, being turned off in device, the carrier in raceway groove will be completely depleted,
This so that Punchthrough leakage current is inhibited well；Due to the first fin body entirety and substrate obtained in above-mentioned preparation method
It is kept completely separate, has completely cut off substrate direction leakage path, to reduce the leakage current of device；Due to only by conduct in fin structure
The part of raceway groove forms nano wire, to make source/drain be able to maintain that original form, on the one hand efficiently avoids short channel effect
It answers, optimizes Sub-Threshold Characteristic, while enabling the device to that there is lower dead resistance；Also, due to above-mentioned nano thread structure
Removing oxide layer is removed after oxidation and is formed, and so as to remove the defective silicon of original surface band, boundary defect is made to subtract significantly
It is small, and the nano wire newly formed more they tends to smooth, reduction tip paradoxical discharge, so that device reliability is improved
It is described in more detail below according to the preparation method of ring gate nano line field-effect transistor provided by the invention
Illustrative embodiments.However, these illustrative embodiments can be implemented by many different forms, and should not be by
It is construed to be only limited to embodiments set forth herein.It should be understood that thesing embodiments are provided so that this Shen
Disclosure please is thoroughly and complete, and the design of these illustrative embodiments is fully conveyed to ordinary skill people
Member.
First, step S1 is executed：Fin structure 110 is formed on substrate 10, as shown in Figures 1 to 5.Above-mentioned substrate 10 can be with
For semiconductor substrate conventional in the prior art, (absolutely such as Si substrates, Ge substrates, SiGe substrate, SOI (silicon-on-insulator) or GOI
Germanium on edge body) etc..
In above-mentioned steps S1, process conventional in the prior art may be used and form above-mentioned fin structure 110, one
In kind preferred embodiment, above-mentioned steps S1 includes following procedure：S11 sequentially forms the second separation layer on substrate 10
210, sacrificial layer 220 and mask layer 230, as shown in Figure 1；S12 removes partial sacrificial layer 220 and mask using patterning process
Layer 230, so that 210 surface exposure of the second separation layer of part, as shown in Figure 2；S13 removes remaining mask layer 230, and
The first side wall 240 for being covered in 220 both sides of sacrificial layer is formed on two separation layers 210, as shown in Figure 3；S14, removal are remaining sacrificial
Domestic animal layer 220, and be that mask removes the second separation layer of part 210 and section substrate 10 with the first side wall 240, with the first side wall 240
Corresponding section substrate 10 convexes to form fin structure 110, while the both sides of fin structure 110 are formed with opposite groove, groove by
It is extended at 1/3 height of fin structure 110 at 2/3 height, as shown in Figure 4 and Figure 5.
In above process S11, may be used MOCVD, PECVD etc. in the prior art conventional deposition method formed it is above-mentioned
Second separation layer 210, sacrificial layer 220 and mask layer 230, those skilled in the art can be according to actual demands to above-mentioned deposition side
The process conditions of method carry out reasonable set；Also, those skilled in the art can according to the prior art to above-mentioned formation second every
The material of absciss layer 210, sacrificial layer 220 and mask layer 230 carries out Rational choice, and the material of the second separation layer of above-mentioned formation 210 can
Think oxide, such as silica, the material of above-mentioned formation sacrificial layer 220 can be non-crystalline silicon (α-Si), above-mentioned formation mask layer
230 material can be Si3N4。
In above process S12, patterning process may include：Photoresist is coated on 230 surface of mask layer, then in light
Mask plate is set above photoresist, photoetching window, the length of remaining photoresist are obtained after removing part photoresist by exposure imaging
Degree is of substantially equal with the length of required mask layer 230, is covered finally by glue is not photo-etched on photoetching opening etch removal substrate 10
The part mask layer 230 and partial sacrificial layer 220 of lid, so that 210 surface exposure of the second separation layer of part, wherein above-mentioned second
Separation layer 210 is for preventing substrate to be partially etched in patterning process.
In above process S13, those skilled in the art can be according to the prior art to the first side wall of above-mentioned formation 240
Material carries out Rational choice, and the material for forming above-mentioned first side wall 240 can be Si3N4。
In above process S14, those skilled in the art can be according to the prior art to the remaining sacrificial layer of above-mentioned removal
220 technique carries out Rational choice, it is preferable that removes above-mentioned sacrificial layer 220 using selective etch technology, above-mentioned selectivity is carved
Erosion can be dry etching or wet etching, by being adjusted to technological parameter so that etching gas or etching solution are to sacrificing
Layer 220 and the first side wall 240 have different etch rates, are optionally removed to sacrificial layer 220 so as to realize.
In above process S14, has reeded fin structure 110 to be effectively formed both sides, it is preferable that use simultaneously
Anisotropic etch process and isotropic etching technique form groove in the both sides of fin structure 110.Specifically, the fin knot is formed
The process of structure 110 may include：The second separation layer of part 210 and section substrate 10 are removed using anisotropic etch process, with
Make remaining substrate 10 that there is bulge-structure；Groove is formed in the both sides of bulge-structure using isotropic etching technique；Using
Anisotropic etch process removal is located at the section substrate 10 below groove, has reeded fin structure 110 to be formed.
It is further preferable that the etching gas of above-mentioned anisotropic etch process includes HBr, Cl2、O2With inert gas such as N2、
The mixed gas of Ar etc. or above-mentioned arbitrary gas, process conditions are：Etching temperature be 20~90 DEG C, etching power be 4~
300W, etch period are 30~500s；The etching gas of above-mentioned isotropic etching technique includes SF6、CF4、Ch2F2And inertia
Gas such as N2, Ar etc. or above-mentioned arbitrary gas mixed gas, process conditions are：Etching power is 4~300W, etch period
For 30~500s.
After having executed above-mentioned steps S1, step S2 is executed：Fin structure 110 is formed to the first fin being isolated with substrate 10
Body 111, the first fin body 111 is made of first area connected in sequence along its length, second area and third region, such as Fig. 6
Shown in Fig. 7.
In a preferred embodiment, above-mentioned steps S2 includes following procedure：S21 aoxidizes fin structure 110,
The position of the corresponding fin structure of further groove 110 is fully oxidized so that fin structure 110 forms independent first fin body 111 and second
Fin body 112, the first fin body 111 are located at the second side of the fin body 112 far from substrate 10, as shown in Figure 6；S22 sinks on substrate 10
Product insulating materials, to form the first separation layer 30 of covering the first fin body 111 and the second fin body 112；S23, to the first separation layer
30 carry out planarization process, so that the upper surface flush of the first separation layer 30 and the first fin body 111.
In above process S21, in order to enable the position of fin structure corresponding with groove 110 to be fully oxidized, preferably
Ground, the process conditions that fin structure 110 is aoxidized are rapid thermal oxidation (RTP), or are passed through oxygen or oxygen and hydrogen using boiler tube
The mixed gas of gas, and heat 30s~10h.
Above process S22 and process S23 can be shallow-trench isolation (STI) technique of routine in the prior art, this field skill
Art personnel can carry out Rational choice according to the prior art to the insulating materials that is deposited in the STI techniques, which can be with
For SiO2；Also, those skilled in the art can be according to actual demand to depositing operation and planarization process in above-mentioned STI techniques
Process conditions carry out reasonable set.
Preceding grid technique, which may be used, in the above-mentioned preparation method of the present invention can also use rear grid technique, at this time nano thread structure
Can be formed in preceding grid technique can also form in rear grid technique, in order to avoid front gate process high-temperature technique is to gate dielectric
Influence, present invention preferably employs rear grid techniques.At this point, upon step s 2, above-mentioned preparation method of the invention can also wrap
Include following steps：Etching removal the first separation layer of part 30 since the surface of the first separation layer 30, so that part the first fin body
111 is exposed, as shown in Figure 7；The false grid formed on remaining first separation layer 30 across part the first fin body 111 stack, and
The both sides that false grid stack form the second side wall 250 across part the first fin body 111；The false grid of removal stack, and are located at the second side wall 250
Between part the first fin body 111 be second area, obtained structure is as shown in Figure 8.
In above-mentioned steps, false grid stacking may include the first gate dielectric layer and false grid, in order to preferably control the first grid
The thickness of dielectric layer, it is preferable that above-mentioned first gate dielectric layer is formed using atom layer deposition process (ALD)；Also, it is formed above-mentioned
The material of first gate dielectric layer may include SiO2、HfO2、La2O3、Al2O3、TiO2Any one or more of, above-mentioned vacation grid material
Material can be non-crystalline silicon, the material and vacation that those skilled in the art can be according to the prior art to above-mentioned first gate dielectric layer of formation
The type of grid material carries out Rational choice.
Also, when using rear grid technique, before the step of false grid of removal stack, in first area and third region
Above-mentioned source/drain 40 is formed, and source/drain 40 and the both ends of the nano thread structure 120 formed in step S3 is made to connect, is obtained
Structure it is as shown in Figure 8.The technique for forming above-mentioned source/drain can be doping in situ, and those skilled in the art can be according to existing
There is technology to carry out reasonable set to the above-mentioned process conditions adulterated in situ.
After having executed above-mentioned steps S2, step S3 is executed：Make the second area partial oxidation in the first fin body 111,
With by second area formed nano thread structure 120 and wrap up nano thread structure 120 oxide layer 113, go removing oxide layer 113 with
Keep nano thread structure 120 exposed, as shown in Figures 9 to 11.At this time preferably, by using monocrystalline substrate to make in step sl
For substrate 10, it is single crystal silicon material that can make above-mentioned nano thread structure 120, since raceway groove is formed in above-mentioned nano thread structure 120
In, it is the mobility that single crystal silicon material improves device carrier to make raceway groove.
In above-mentioned formation nano thread structure 120 the step of, by the second area in the first fin body 111 since outer surface
Oxidation is to form oxide layer, and not oxidized part constitutes the nano thread structure 120 that section is drops in second area.In order to
Improve the efficiency for forming above-mentioned nano thread structure 120, it is preferable that in above-mentioned steps S3, rapid thermal oxidation may be used
(RTP), pure oxygen or oxygen and hydrogen gas mixture can also be used to aoxidize the part of second area；Also, it is preferred that
Ground removes above-mentioned oxide layer 113 using wet-etching technology, and the corrosive agent of above-mentioned wet-etching technology may include DHF.
It is excellent when being formed across above-mentioned second side wall 250 of the first fin body 111 of part between above-mentioned steps S2 and step S3
Selection of land, before the step of making second area partial oxidation, above-mentioned steps S3 further includes：Since the surface of the first separation layer 30
First separation layer 30 of the etching removal between the second side wall 250, so that the second area in the first fin body 111 is completely naked
Dew, as shown in figure 9, then by aoxidizing the second area in the first fin body 111 since outer surface, and remove the oxygen on surface
Change layer 113, part the first fin body 111 is formed into nano thread structure 120, source/drain 40 is located at nano thread structure 120 at this time
Both sides, obtained structure are as shown in figure 12；It is further preferable that removing above-mentioned first separation layer in part using wet-etching technology
30, the corrosive agent used in wet-etching technology can be DHF.
After having executed above-mentioned steps S3, step S4 is executed：Grid, which are formed, around the periphery of nano thread structure 120 stacks knot
Structure.Above-mentioned grid stacked structure includes package and surround the second gate dielectric layer and grid of nano thread structure 120.In order to preferably
Control the thickness of the second gate dielectric layer, it is preferable that above-mentioned second gate dielectric layer is formed using atom layer deposition process (ALD)；And
And the material for forming above-mentioned second gate dielectric layer may include SiO2、HfO2、La2O3、Al2O3、TiO2Any one of or it is more
Kind.Formed above-mentioned grid metal gate material can be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN,
RuTax、NiTax, MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、Ti、Al、Cr、
Au, Cu, Ag, HfRu and RuOxAny one or more of, those skilled in the art can be according to the prior arts to above-mentioned metal
The type of grid material carries out Rational choice.
Also, when using preceding grid technique, after the step of forming grid stacked structure, in first area and third region
Middle formation source/drain, and source/drain and the both ends of the nano thread structure 120 formed in step S3 is made to connect.Formed above-mentioned source/
The technique of drain electrode can be doping in situ, and those skilled in the art can be according to the prior art to the above-mentioned technique item adulterated in situ
Part carries out reasonable set.
According to another aspect of the present invention, a kind of ring gate nano line field-effect transistor is provided, as shown in figure 12, packet
It includes：Substrate 10；First fin body 111, be located at substrate 10 on, the first fin body 111 by first area connected in sequence along its length,
Second area and third region composition, and second area is nano thread structure 120, the section of nano thread structure 120 is drops；
First separation layer 30 is set between substrate 10 and the first fin body 111, for the first fin body 111 to be isolated with substrate 10；Grid heap
Stack structure (not shown), around nano thread structure 120；Source/drain 40 is located in first area and third region, and source/
Drain electrode 40 is connect with the both ends of nano thread structure 120.
The present invention above-mentioned ring gate nano line field-effect transistor in due to grid stacked structure in grid four sides package use
In the nano thread structure for forming raceway groove, to make the grid-control ability for improving device, turned off in device, the load in raceway groove
Stream will be completely depleted, this so that Punchthrough leakage current is inhibited well；Due to above-mentioned first fin body and substrate
Separation, has completely cut off substrate direction leakage path, to reduce the substrate leakage current of device；Also, due to only by fin structure
The middle part as raceway groove forms nano wire and is on the one hand efficiently avoided short to make source/drain be able to maintain that original form
Channelling effect optimizes Sub-Threshold Characteristic, while enabling the device to have lower dead resistance.
The above-mentioned ring gate nano line field-effect transistor of the present invention can be prepared by above-mentioned preparation method, and ring grid are received
Rice noodles field-effect transistor can also include cover grid stacked structure both sides and the second side wall 250 across the first fin body 111, this
Two side walls 250 can play the role of grid stacked structure and source/drain 40 is isolated.
It can be seen from the above description that the above embodiments of the present invention realize following technique effect：
1, since the grid in grid stacked structure wraps up nano thread structure for forming trenches, to make to improve device
Grid-control ability, turned off in device, the carrier in raceway groove will be completely depleted, this makes Punchthrough leakage current
Inhibited well；
2, since the first fin body obtained in above-mentioned preparation method is detached with substrate, to reduce the leakage current of device；
3, since only nano wire will be formed as the part of raceway groove in fin structure, to make source/drain be able to maintain that original
Carry out shape, efficiently avoid short-channel effect, optimize Sub-Threshold Characteristic, and enables the device to that there is lower parasitic electricity
Resistance；In addition source and drain areas can also use all-metal source and drain, selective epitaxial or Schottky source drain technique, further decrease device
The source and drain dead resistance of part；
4, it is formed since above-mentioned nano thread structure removes removing oxide layer after oxidation, so as to remove original surface band
Defective silicon, makes boundary defect greatly reduce, and the nano wire newly formed more they tends to smooth, reduction tip paradoxical discharge, into
And device reliability is improved；
5, by using monocrystalline substrate as substrate, it is single crystal silicon material that can make above-mentioned nano thread structure, due to ditch
Road is formed in above-mentioned nano thread structure, and it is the mobility that polycrystalline silicon material improves device to make raceway groove.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (11)
1. a kind of preparation method of ring gate nano line field-effect transistor, which is characterized in that include the following steps：
S1 forms fin structure (110) on substrate (10)；
The fin structure (110) is formed the first fin body (111) being isolated with the substrate (10), the first fin body by S2
(111) it is made of first area connected in sequence along its length, second area and third region；
S3 makes the second area partial oxidation in the first fin body (111), and the second area is formed nano wire
Structure (120) and the oxide layer (113) of the package nano thread structure (120), remove the oxide layer (113) so that described
Nano thread structure (120) is exposed；
S4 forms grid stacked structure around the periphery of the nano thread structure (120),
And the preparation method is further comprising the steps of：
Source/drain, the source/drain (20) and the nano thread structure are formed in the first area and the third region
(120) both ends connection.
2. preparation method according to claim 1, which is characterized in that the step S1 includes following procedure：
S11 sequentially forms the second separation layer (210), sacrificial layer (220) and mask layer (230) on the substrate (10)；
S12, using the patterning process removal part sacrificial layer (220) and the mask layer (230), so that part described the
Two separation layers (210) surface exposure；
S13 removes the remaining mask layer (230), and is formed on second separation layer (210) and be covered in the sacrifice
First side wall (240) of layer (220) both sides；
S14 removes the remaining sacrificial layer (220), and is that mask removes part described second with first side wall (240)
Separation layer (210) and the part substrate (10), part corresponding with the first side wall (240) substrate (10) convex shaped
It is formed with opposite groove at the both sides of the fin structure (110), while the fin structure (110), the groove is by the fin
It is extended at 1/3 height of structure (110) at 2/3 height.
3. preparation method according to claim 2, which is characterized in that the process for forming the fin structure (110) includes：
Using anisotropic etch process removal part second separation layer (210) and the part substrate (10), so that surplus
The remaining substrate (10) has bulge-structure；
The groove is formed in the both sides of the bulge-structure using isotropic etching technique；
The part substrate (10) below the groove is located at using anisotropic etch process removal, to be formed with described
The fin structure (110) of groove.
4. preparation method according to claim 1, which is characterized in that in the step S1, on the substrate (10)
The fin structure (110) is formed, while the both sides of the fin structure (110) are formed with opposite groove, the groove is by described
It is extended at 1/3 height of fin structure (110) at 2/3 height, the step S2 includes following procedure：
S21 aoxidizes the fin structure (110), wherein the position of the corresponding fin structure (110) of the groove is by complete oxygen
Change so that the fin structure (110) forms the independent first fin body (111) and the second fin body (112), the first fin body
(111) it is located at side of the second fin body (112) far from the substrate (10)；
S22, the deposition of insulative material on the substrate (10) cover the first fin body (111) and second fin to be formed
The first separation layer (30) of body (112)；
S23 carries out planarization process to first separation layer (30), so that first separation layer (30) and first fin
The upper surface flush of body (111).
5. preparation method according to claim 4, which is characterized in that between the step S2 and the step S3, institute
It is further comprising the steps of to state preparation method：
Etching removal part first separation layer (30) since the surface of first separation layer (30), so that described in part
First fin body (111) is exposed；
The false grid formed on remaining first separation layer (30) across part the first fin body (111) stack, and in institute
State second side wall of the both sides formation across part the first fin body (111) of false grid stacking；
It removes the false grid to stack, part the first fin body (111) between second side wall is secondth area
Domain.
6. preparation method according to claim 5, which is characterized in that before removing the step of false grid stack,
The source/drain is formed in the first area and the third region, and the source/drain is made to be formed with the step S3
The nano thread structure (120) both ends connection.
7. preparation method according to claim 5, which is characterized in that the step of making the second area partial oxidation it
Before, the step S3 further includes：
First isolation of the etching removal between second side wall since the surface of first separation layer (30)
Layer (30), so that the second area is completely exposed, it is preferred to use wet-etching technology removes part first separation layer
(30), the corrosive agent of the more preferably wet-etching technology includes DHF.
8. preparation method according to claim 1, which is characterized in that in the step S3, using wet-etching technology
The oxide layer (113) is removed, the corrosive agent of the preferably described wet-etching technology includes DHF.
9. preparation method according to claim 1, which is characterized in that after the step of forming the grid stacked structure,
The source/drain is formed in the first area and the third region, and makes the source/drain and shape in the step S3
At the nano thread structure (120) both ends connection.
10. a kind of ring gate nano line field-effect transistor, which is characterized in that including：
Substrate (10)；
First fin body (111) is located on the substrate (10), and the first fin body (111) is by connected in sequence along its length
First area, second area and third region composition, and the second area is nano thread structure (120), the nanowire-junction
The section of structure (120) is drops；
First separation layer (30) is set between the substrate (10) and the first fin body (111), is used for first fin
Body (111) is isolated with the substrate (10)；
Grid stacked structure is arranged around the nano thread structure (120)；And
Source/drain (40) is located in the first area and the third region, and the source/drain (40) and the nanometer
The both ends of cable architecture (120) connect.
11. ring gate nano line field-effect transistor according to claim 10, which is characterized in that ring gate nano line field
Effect transistor further includes covering grid stacked structure both sides and across the second side wall (250) of the first fin body (111).
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