CN108288647A - Surrounding gate nanowire field effect transistor and preparation method thereof - Google Patents

Abstract

The invention provides a gate-around nanowire field effect transistor and a preparation method thereof. The preparation method includes the following steps: S1, forming a first fin body isolated from the substrate on the substrate, the first fin body is composed of a first region, a second region and a third region sequentially connected along the length direction; S2 , forming a nanowire structure in the second region of the first fin body; S3, sequentially forming a stacked interface oxide layer, a ferroelectric layer and a gate around the exposed surface of the nanowire structure, and the preparation method further includes the following steps: Source/drain electrodes are formed in the first region and the third region, and the source/drain electrodes are connected to both ends of the nanowire structure. The above preparation method improves the gate control ability of the device, reduces the leakage current of the device, reduces the source-drain parasitic resistance of the device, and can make the sub-threshold slope of the device much lower than 60mV/dec.

Description

Gate-all-around nanowire field-effect transistor and preparation method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a gate-around nanowire field-effect transistor and a preparation method thereof.

Background technique

As devices continue to shrink, traditional Fin Field Effect Transistors (FinFETs) face severely degraded sub-threshold characteristics, sharply increased source-drain punch-through leakage currents, and gate-dielectric tunneling leakage currents, improving drive performance and reducing system power consumption. There are many serious challenges such as the contradictory requirements of voltage and statistical fluctuations of electrical parameters caused by process variation. Therefore, a steeper sub-threshold slope means that a lower threshold voltage and lower power consumption can be obtained. However, due to the limitation of its physical characteristics, the sub-threshold slope of traditional MOSFETs cannot be lower than 60mV/dec.

How to provide a lower subthreshold slope and optimize gate control by optimizing the device structure and manufacturing process is still a technical problem that must be solved for fin field effect transistors.

Contents of the invention

The main purpose of the present invention is to provide a gate-all-around nanowire field effect transistor and its preparation method, so as to solve the problem of high subthreshold slope in the fin field effect transistor in the prior art.

In order to achieve the above object, according to one aspect of the present invention, a method for manufacturing a gate-all-around nanowire field effect transistor is provided, including the following steps: S1, forming a first fin body isolated from the substrate on the substrate, first The fin body is composed of the first region, the second region and the third region sequentially connected along the length direction; S2, the second region in the first fin body is formed into a nanowire structure; S3, the exposed surface sequence around the nanowire structure forming a laminated interface oxide layer, a ferroelectric layer, and a gate, and the preparation method further includes the following steps: forming a source/drain in the first region and a third region, the source/drain being connected to both ends of the nanowire structure .

Further, step S1 includes the following steps: S11, forming a fin structure on the substrate, with opposite grooves on both sides of the fin structure; S12, oxidizing the fin structure, wherein the position of the fin structure corresponding to the groove is completely oxidized to Make the fin structure form independent first fin body and second fin body, the first fin body is located on the side of the second fin body away from the substrate; S13, deposit insulating material on the substrate, to form the covering first fin body and the second fin body The first isolation layer of the second fin body; S14, planarize the first isolation layer, so that the first isolation layer is flush with the upper surface of the first fin body.

Further, step S11 includes the following processes: S111, sequentially forming a second isolation layer, a sacrificial layer, and a mask layer on the substrate; S112, removing part of the sacrificial layer and mask layer using a patterning process, so that part of the second isolation layer The surface of the layer is exposed; S113, remove the remaining mask layer, and form a first side wall covering both sides of the sacrificial layer on the second isolation layer; S114, remove the remaining sacrificial layer, and use the first side wall as a mask Part of the second isolation layer and part of the substrate are removed, and part of the substrate corresponding to the first sidewall is raised to form a fin structure, and grooves are formed on both sides of the fin structure, and the groove extends from 1/3 of the height of the fin structure to 2/3 height.

Further, the process of forming the fin structure includes: using an anisotropic etching process to remove part of the second isolation layer and part of the substrate, so that the remaining substrate has a raised structure; using an isotropic etching process to remove a part of the raised structure Grooves are formed on both sides of the groove; an anisotropic etching process is used to remove part of the substrate under the groove to form a fin structure with grooves.

Further, between step S1 and step S2, the preparation method further includes the following steps: starting from the surface of the first isolation layer to etch and remove part of the first isolation layer, so as to expose part of the first fin body; A dummy gate stack spanning part of the first fin body is formed on the isolation layer, and second sidewalls spanning part of the first fin body are formed on both sides of the dummy gate stack; the part between the second sidewalls is removed from the dummy gate stack The first fin body is the second area.

Further, before the step of removing the dummy gate stack, a source/drain is formed in the first region and the third region, and the source/drain is connected to both ends of the nanowire structure formed in step S2.

Further, step S2 includes: completely exposing the second region in the first fin body, annealing the second region in a hydrogen atmosphere, so as to form a part of the first fin body into a nanowire structure, preferably the pressure of the hydrogen atmosphere is 10-50mT, the temperature of the annealing treatment is 650-950°C, and the time is 10-300s; or partially oxidize the second region in the first fin body, so as to form the second region into a nanowire structure and oxidize the wrapping nanowire structure layer, removing the oxide layer to expose the nanowire structure, preferably using a wet etching process to remove the oxide layer, and the etchant of the wet etching process includes DHF.

Further, in step S3, the exposed surface of the nanowire structure is treated with ozone to form an interface oxide layer.

Further, in step S3, an atomic layer deposition process is used to form a ferroelectric layer around the exposed surface of the interface oxide layer.

Further, the material forming the ferroelectric layer includes HfZrO and/or HfSiO.

Further, between the steps of forming the ferroelectric layer and the gate, step S3 further includes the following step: forming a work function layer around the periphery of the ferroelectric layer.

Further, a work function layer is formed around the exposed surface of the ferroelectric layer by atomic layer deposition process.

Further, the substrate is N-type doped, and the energy gap of the work function layer is 4.1-4.4eV, and the material forming the work function layer is preferably TiAl; or the substrate is P-type doped, and the energy gap of the work function layer is 4.7 eV. ~4.9eV, preferably the material forming the work function layer is TiN.

Further, after the step of forming the gate, a source/drain is formed in the first region and the third region, and the source/drain is connected to both ends of the nanowire structure formed in step S2.

According to another aspect of the present invention, there is provided a gate-all-around nanowire field effect transistor, comprising: a substrate; a first fin body located on the substrate, and the first fin body is composed of first regions sequentially connected along the length direction , the second area and the third area, and the second area is a nanowire structure; the first isolation layer is arranged between the substrate and the first fin body, and is used to isolate the first fin body from the substrate; the interface is oxidized A layer surrounding the nanowire structure; a ferroelectric layer surrounding the interface oxide layer; a gate surrounding the ferroelectric layer; and a source/drain located in the first region and the third region, and the source/drain is connected to the nanowire structure Both ends are connected.

Further, the gate-all-around nanowire field effect transistor further includes a work function layer surrounding the ferroelectric layer, and the work function layer is arranged between the ferroelectric layer and the gate.

Further, the gate-all-around nanowire field effect transistor further includes a second side wall covering both sides of the gate and straddling the first fin body.

Applying the technical scheme of the present invention, a method for preparing a gate-all-around nanowire field effect transistor is provided. In the preparation method, the first fin body isolated from the substrate is formed, and the first fin body is sequentially connected along the length direction. After the first region, the second region and the third region are composed, the second region of the first fin body is formed into a nanowire structure, and an interface oxide layer, a ferroelectric layer and a gate are sequentially formed around the nanowire structure, because the gate The four sides of the pole wrap the nanowire structure used to form the channel, thereby improving the gate control capability of the device. When the device is turned off, the carriers in the channel will be completely depleted, which makes the source-drain through leakage current is well suppressed; since the first fin body obtained in the above preparation method is completely separated from the substrate, the leakage path in the direction of the substrate is isolated, thereby reducing the leakage current of the device; Partially form nanowires, so that the source/drain can maintain the original shape, on the one hand, effectively avoid the short channel effect, optimize the sub-threshold characteristics, and at the same time enable the device to have lower parasitic resistance; and, due to the formation of the above iron The material of the electrical layer is a negative capacitance material, which has polarization characteristics, so that the subthreshold slope of the device can be greatly lower than 60mV/dec, the switching speed is faster, and the power consumption is lower.

Description of drawings

The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention, and the schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 shows a schematic cross-sectional structure diagram of a substrate after sequentially forming a second isolation layer, a sacrificial layer and a mask layer on a substrate in a method for manufacturing a gate-all-around nanowire field effect transistor provided in an embodiment of the present application;

FIG. 2 shows a schematic diagram of a cross-sectional structure of the substrate after removing part of the sacrificial layer and mask layer shown in FIG. 1 to expose part of the surface of the second isolation layer;

FIG. 3 shows a schematic cross-sectional structure diagram of the substrate after removing the remaining mask layer shown in FIG. 2 and forming first sidewalls covering both sides of the sacrificial layer on the second isolation layer;

FIG. 4 shows a schematic diagram of the cross-sectional structure of the substrate after removing the sacrificial layer shown in FIG. 3;

FIG. 5 shows a schematic cross-sectional structure diagram of a substrate in which a fin structure with grooves is formed in the substrate shown in FIG. 4;

FIG. 6 shows a schematic cross-sectional view of the base body after the fin structure shown in FIG. 5 is oxidized so that the fin structure forms an independent first fin body and a second fin body;

FIG. 7 shows a schematic cross-sectional structure diagram of the substrate after forming the first isolation layer covering the first fin body and the second fin body shown in FIG. 6 and exposing part of the first fin body;

Fig. 8 shows a perspective view of the substrate after forming a second side wall in the substrate shown in Fig. 7;

FIG. 9 shows a schematic cross-sectional structure diagram of the substrate after the second region in the first fin shown in FIG. 7 is completely exposed;

FIG. 10 shows a schematic diagram of a cross-sectional structure of a substrate after forming part of the first fin body shown in FIG. 9 into a nanowire structure;

Fig. 11 shows a schematic diagram of the cross-sectional structure of the substrate after the second region shown in Fig. 9 is oxidized to form a nanowire structure and an oxide layer;

FIG. 12 shows a schematic cross-sectional structure diagram of the substrate after removing the oxide layer shown in FIG. 11 to expose the nanowire structure;

Fig. 13 shows a schematic diagram of the cross-sectional structure of the substrate after forming an interface oxide layer around the exposed surface of the nanowire structure shown in Fig. 12;

FIG. 14 shows a schematic cross-sectional structure diagram of the substrate after forming a ferroelectric layer around the exposed surface of the interface oxide layer shown in FIG. 13;

Fig. 15 shows a schematic cross-sectional structure diagram of the substrate after forming a work function layer around the exposed surface of the ferroelectric layer shown in Fig. 14;

FIG. 16 is a schematic diagram of a cross-sectional structure of a substrate after forming a gate around the exposed surface of the work function layer shown in FIG. 15;

Fig. 17 shows a perspective view of a gate-all-around nanowire field-effect transistor provided by an embodiment of the present invention; and

FIG. 18 shows a schematic cross-sectional structure diagram of an interface oxide layer, a ferroelectric layer, a work function layer and a grid surrounding the nanowire structure in the gate-all-around nanowire field effect transistor shown in FIG. 17 .

Wherein, the above-mentioned accompanying drawings include the following reference signs:

10, substrate; 110, fin structure; 111, first fin body; 112, second fin body; 113, oxide layer; 120, nanowire structure; 210, second isolation layer; 220, sacrificial layer; 230, mask Film layer; 240, first side wall; 250, second side wall; 30, first isolation layer; 40, source/drain; 50, interface oxide layer; 60, ferroelectric layer; 70, work function layer; 80 , Gate.

Detailed ways

It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.

In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It should be understood that the data so used may be interchanged under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

As introduced in the background art, how to provide lower subthreshold slope and optimize gate control by optimizing the device structure and manufacturing process in the prior art is still a technical problem that must be solved for fin field effect transistors. The inventors of the present invention conducted research on the above-mentioned problems, and proposed a method for manufacturing a gate-all-around nanowire field-effect transistor, including the following steps: S1, forming a first fin body 111 isolated from the substrate 10 on the substrate 10, The first fin body 111 is composed of a first region, a second region and a third region sequentially connected along the length direction, the above-mentioned length direction refers to the extension direction of the first fin body 111; S2, the first fin body 111 The second region forms the nanowire structure 120; S3, sequentially forming a stacked interface oxide layer, a ferroelectric layer and a gate around the exposed surface of the nanowire structure 120, and the preparation method further includes the following steps: in the first region and the third A source/drain 40 is formed in the region, and the source/drain 40 is connected to both ends of the nanowire structure 120 .

In the preparation method of the above-mentioned gate-all-around nanowire field effect transistor, since the first fin body isolated from the substrate is formed, and the first fin body is composed of the first region, the second region and the third region connected in sequence along the length direction Finally, the second region of the first fin body is formed into a nanowire structure, and an interface oxide layer, a ferroelectric layer, and a gate are sequentially formed around the nanowire structure. Since the gate surrounds the nanowire structure used to form a channel, Therefore, the gate control capability of the device is improved. When the device is turned off, the carriers in the channel will be completely depleted, which makes the source-drain punch-through leakage current well suppressed; due to the obtained in the above preparation method The first fin body is completely separated from the substrate as a whole, which isolates the leakage path in the direction of the substrate, thereby reducing the leakage current of the device; because only the part of the fin structure that is used as the channel is formed into a nanowire, the source/drain can maintain The original shape, on the one hand, effectively avoids the short channel effect, optimizes the sub-threshold characteristics, and at the same time enables the device to have lower parasitic resistance; moreover, since the material forming the ferroelectric layer is a negative capacitance material, it has polarization characteristics , so that the sub-threshold slope of the device can be greatly lower than 60mV/dec, the switching speed is faster, and the power consumption is lower.

An exemplary embodiment of a method for fabricating a gate-all-around nanowire field effect transistor according to the present invention will be described in more detail below. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art.

First, step S1 is performed: forming a first fin body 111 isolated from the substrate 10 on the substrate 10, the first fin body 111 is composed of a first region, a second region and a third region sequentially connected along the length direction, As shown in Figures 1 to 7. The aforementioned substrate 10 may be a conventional semiconductor substrate in the prior art, such as Si substrate, Ge substrate, SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like.

In order to obtain the above-mentioned first fin body 111 isolated from the substrate 10, in a preferred implementation manner, the above-mentioned step S1 includes the following steps: S11, forming a fin structure 110 on the substrate 10, the two sides of the fin structure 110 have The opposite groove, as shown in FIGS. 1 to 5; S12, oxidize the fin structure 110, wherein the position of the fin structure 110 corresponding to the groove is completely oxidized so that the fin structure 110 forms an independent first fin body 111 and a second fin body. Fin body 112, the first fin body 111 is located on the side of the second fin body 112 away from the substrate 10, as shown in FIG. The first isolation layer 30 of the second fin body 112 ; S14 , planarize the first isolation layer 30 so that the first isolation layer 30 is flush with the upper surface of the first fin body 111 .

In the above-mentioned step S11, the above-mentioned fin structure 110 can be formed using a conventional process method in the prior art. In a preferred embodiment, the above-mentioned step S11 includes the following process: S111, sequentially forming a second isolation on the substrate 10 layer 210, sacrificial layer 220, and mask layer 230, as shown in FIG. 1; S112, using a patterning process to remove part of the sacrificial layer 220 and mask layer 230, so that part of the surface of the second isolation layer 210 is exposed, as shown in FIG. 2 S113, remove the remaining mask layer 230, and form the first spacer 240 covering both sides of the sacrificial layer 220 on the second isolation layer 210, as shown in FIG. 3; S114, remove the remaining sacrificial layer 220, And use the first sidewall 240 as a mask to remove part of the second isolation layer 210 and part of the substrate 10, the part of the substrate 10 corresponding to the first sidewall 240 protrudes to form the fin structure 110, and at the same time, the two sides of the fin structure 110 are formed There are opposite grooves, and the grooves extend from 1/3 of the height of the fin structure 110 to 2/3 of the height, as shown in FIG. 4 and FIG. 5 .

In the above process S111, conventional deposition methods in the prior art such as MOCVD and PECVD can be used to form the above-mentioned second isolation layer 210, sacrificial layer 220 and mask layer 230. The process conditions are reasonably set; and, those skilled in the art can reasonably select the materials for forming the second isolation layer 210, the sacrificial layer 220 and the mask layer 230 according to the prior art, and the above-mentioned materials for forming the second isolation layer 210 It may be an oxide, such as silicon oxide, the material for forming the sacrificial layer 220 may be amorphous silicon (α-Si), and the material for forming the mask layer 230 may be Si ₃ N ₄ .

In the above process S112, the patterning process may include: coating photoresist on the surface of the mask layer 230, and then setting a mask plate above the photoresist, removing part of the photoresist through exposure and development to obtain a photolithographic window, and the remaining The length of the photoresist is substantially equal to the length of the required mask layer 230, and finally the part of the mask layer 230 and part of the sacrificial layer 220 that are not covered by the photoresist on the substrate 10 are removed by photolithography window etching, so that Part of the surface of the second isolation layer 210 is exposed, wherein the above-mentioned second isolation layer 210 is used to prevent the substrate from being partially etched during the patterning process.

In the above process S113, those skilled in the art can reasonably select the material for forming the first side wall 240 according to the prior art, and the material for forming the first side wall 240 can be Si ₃ N ₄ .

In the above process S114, those skilled in the art can reasonably select the above-mentioned process for removing the remaining sacrificial layer 220 according to the prior art. Preferably, the above-mentioned sacrificial layer 220 is removed by using a selective etching technique, and the above-mentioned selective etching can be For dry etching or wet etching, by adjusting the process parameters so that the etching gas or etching solvent has different etching rates for the sacrificial layer 220 and the first sidewall 240, the sacrificial layer 220 can be realized selectively removed.

In the above process S114 , in order to effectively form the fin structure 110 with grooves on both sides, preferably, the anisotropic etching process and the isotropic etching process are used to form grooves on both sides of the fin structure 110 . Specifically, the process of forming the fin structure 110 may include: using an anisotropic etching process to remove part of the second isolation layer 210 and part of the substrate 10, so that the remaining substrate 10 has a raised structure; An etching process forms grooves on both sides of the protruding structure; an anisotropic etching process is used to remove part of the substrate 10 below the grooves to form a fin structure 110 with grooves.

More preferably, the etching gas of the above-mentioned anisotropic etching process includes HBr, Cl ₂ , O ₂ and inert gases such as N ₂ , Ar, etc. or a mixture of any of the above gases, and the process conditions are: the etching temperature is 20-90°C, etching power 4-300W, etching time 30-500s; the etching gas for the above isotropic etching process includes SF ₆ , CF ₄ , Ch ₂ F ₂ and inert gases such as N ₂ , Ar etc. or a mixed gas of any of the above-mentioned gases, the process conditions are as follows: the etching power is 4-300W, and the etching time is 30-500s.

In the above process S12, in order to completely oxidize the position of the fin structure 110 corresponding to the groove, preferably, the process condition for oxidizing the fin structure 110 is rapid thermal oxidation (RTP), or the furnace tube is used to feed oxygen or Mixed gas of oxygen and hydrogen, and heated for 30s~10h.

The above-mentioned process S13 and process S14 can be a conventional shallow trench isolation (STI) process in the prior art, and those skilled in the art can reasonably select the insulating material deposited in the STI process according to the prior art, and the insulating material can be SiO ₂ ; and, those skilled in the art can reasonably set the process conditions of the deposition process and planarization treatment in the above STI process according to actual needs.

The above-mentioned preparation method of the present invention can adopt the front gate process or the last gate process. At this time, the nanowire structure can be formed in the front gate process or the last gate process. In order to avoid the high temperature process of the front gate process from affecting the gate dielectric Influenced by the influence, the present invention preferably adopts the gate-last process. At this time, after step S1, the above-mentioned preparation method of the present invention may further include the following step: starting from the surface of the first isolation layer 30 to etch and remove part of the first isolation layer 30, so that part of the first fin body 111 is exposed, as As shown in FIG. 7; a dummy gate stack spanning part of the first fin body 111 is formed on the remaining first isolation layer 30, and a second sidewall spanning part of the first fin body 111 is formed on both sides of the dummy gate stack; The dummy gate is stacked, and part of the first fin body 111 located between the second sidewalls is the second region, so that the structure shown in FIG. 8 is obtained.

In the above steps, the dummy gate stack may include a first gate dielectric layer and a dummy gate. In order to better control the thickness of the first gate dielectric layer, preferably, the first gate dielectric layer is formed by atomic layer deposition (ALD) and, the material for forming the first gate dielectric layer may include any one or more of SiO ₂ , HfO ₂ , La ₂ O ₃ , Al ₂ O ₃ , TiO _{2 ,} and the dummy gate material may be amorphous silicon Those skilled in the art can reasonably select the materials for forming the first gate dielectric layer and the types of dummy gate materials according to the prior art.

Moreover, when the gate-last process is adopted, before the step of removing the dummy gate stack, the above-mentioned source/drain 40 is formed in the first region and the third region, and the source/drain 40 and the nanometer formed in step S2 Both ends of the wire structure 120 are connected, as shown in FIG. 8 . The process for forming the above-mentioned source/drain 40 may be in-situ doping, and those skilled in the art can reasonably set the process conditions for the above-mentioned in-situ doping according to the prior art.

After the above step S1 is performed, step S2 is performed: forming the nanowire structure 120 in the second region of the first fin body 111 . At this time, preferably, by using a single-crystal silicon substrate as the substrate 10 in step S1, the above-mentioned nanowire structure 120 can be made of a single-crystal silicon material, and since the channel is formed in the above-mentioned nanowire structure 120, the channel is Single crystal silicon material improves the mobility of device carriers.

In order to form the nanowire structure 120 in the second region in the first fin body 111, in a preferred implementation manner, the above step S2 includes: completely exposing the second region in the first fin body 111, under hydrogen atmosphere Annealing is performed on the second region to form a part of the first fin body 111 into a nanowire structure 120 with a circular cross section, as shown in FIGS. 9 and 10 . Annealing in a hydrogen atmosphere can cause the silicon surface to undergo atomic reconstruction under a reduced pressure and high temperature environment, thereby moving some of the Si atoms at the corners of the first fin body 111 to positions with lower energy to form the nanowire structure 120 . In order to improve the efficiency of forming the nanowire structure 120, preferably, the pressure of the hydrogen atmosphere is 10-50 mT, the annealing temperature is 650-950° C., and the time is 10-300 s.

In another preferred embodiment, the above step S2 includes: partially oxidizing the second region in the first fin body 111 to form the nanowire structure 120 and the oxide layer 113 surrounding the nanowire structure 120 in the second region, The oxide layer 113 is removed to expose the nanowire structure 120, as shown in FIGS. 11 and 12 . The second region of the first fin body 111 is oxidized from the outer surface to form an oxide layer, and the unoxidized part of the second region forms a nanowire structure 120 with a drop-shaped cross section. In order to improve the efficiency of forming the above-mentioned nanowire structure 120, preferably, rapid thermal oxidation (RTP) can be used, and pure oxygen or a mixed gas of oxygen and hydrogen can be used to oxidize the part of the second region; and, preferably, wet The above-mentioned oxide layer 113 is removed by a wet etching process, and the etchant of the above-mentioned wet etching process may include DHF.

When forming the above-mentioned second sidewall 250 spanning part of the first fin body 111 between the above-mentioned step S1 and the step S2, in the above-mentioned step S2, preferably, start from the surface of the first isolation layer 30 to etch and remove the the first isolation layer 30 between the two sidewalls 250, so that the second region in the first fin body 111 is completely exposed, as shown in FIG. By oxidizing the second region of the first fin body 111 from the outer surface, and removing the oxide layer 113 on the surface, a part of the first fin body 111 is formed into a nanowire structure 120, and at this time, the source/drain 40 is located on the nanowire On both sides of the structure 120 , the resulting structure is shown in FIG. 12 ; more preferably, a part of the above-mentioned first isolation layer 30 is removed by a wet etching process, and the etchant used in the wet etching process may be DHF.

After the above step S2 is performed, step S3 is performed: sequentially forming a stacked interface oxide layer 50 , a ferroelectric layer 60 and a gate 80 around the exposed surface of the nanowire structure 120 , as shown in FIGS. 13 to 16 . Since the material forming the above-mentioned ferroelectric layer 60 is a negative capacitance material, which has polarization characteristics, the subthreshold slope of the device can be greatly lower than 60mV/dec; The control ability is the strongest. When the device is turned off, the carriers in the channel will be completely depleted, which makes the source-drain punch-through leakage current well suppressed.

In the above step S3, in order to form the above-mentioned interface oxide layer 50 more effectively, preferably, the exposed surface of the nanowire structure 120 is treated with ozone to form the interface oxide layer 50, and the obtained structure is shown in FIG. 13; and, for To form the ferroelectric layer 60 more efficiently, preferably, the ferroelectric layer 60 is formed around the exposed surface of the interface oxide layer 50 by atomic layer deposition (ALD). The obtained structure is shown in FIG. 14 . Those skilled in the art can reasonably select the process conditions for the above-mentioned ozone treatment and atomic layer deposition according to the prior art.

In the above step S3, in order to ensure the polarization characteristics of the ferroelectric layer 60, so that the subthreshold slope of the device can be greatly lower than 60mV/dec, preferably, the ferroelectric material forming the ferroelectric layer 60 includes HfZrO and/or HfSiO. However, it is not limited to the above-mentioned preferred types, and those skilled in the art can make reasonable selections to form the above-mentioned ferroelectric materials according to the prior art.

In the above step S3, the metal gate material for forming the gate 80 may be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, _NiTax , _MoNx , _TiSiN , TiCN, TaAlC, TiAlN, TaN , _PtSix , Ni ₃ Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu and RuO _x any one or more, those skilled in the art can The types of the above metal gate materials are reasonably selected.

In a preferred embodiment, between the steps of forming the ferroelectric layer 60 and the gate 80, step S3 further includes the following step: forming a work function layer 70 around the periphery of the ferroelectric layer 60, and the obtained structure is shown in FIG. 15 As shown, the gate 80 is disposed around the surface of the work function layer 70 at this time. The above-mentioned work function layer 70 is used for adjusting the threshold voltage of the device to meet the requirements of high performance devices and low power consumption devices.

In order to form the above-mentioned work function layer 70 more efficiently, preferably, the work function layer 70 is formed around the exposed surface of the ferroelectric layer 60 by an atomic layer deposition process. Moreover, in order to enable the above-mentioned work function layer 70 to achieve effective adjustment of the turn-on voltage, preferably, when the substrate 10 is N-type doped, the energy gap of the above-mentioned work function layer 70 is 4.1-4.4eV, and it is preferable to form a work function layer The material of 70 is TiAl; when the substrate 10 is P-type doped, the energy gap of the above-mentioned work function layer 70 is 4.7-4.9 eV, preferably the material forming the work function layer 70 is TiN.

Moreover, when using the gate-front process, after the step of forming the gate 80, the source/drain 40 is formed in the first region and the third region, and the source/drain 40 is connected with the nanowire structure formed in step S3 The two ends of 120 are connected. The process for forming the above-mentioned source/drain 40 may be in-situ doping, and those skilled in the art can reasonably set the process conditions for the above-mentioned in-situ doping according to the prior art.

According to another aspect of the present invention, a gate-all-around nanowire field effect transistor is provided, as shown in FIG. 17 and FIG. 18 , comprising: a substrate 10; a first fin body 111 located on the substrate 10; The body 111 is composed of a first region, a second region and a third region sequentially connected along the length direction, and the second region is a nanowire structure 120; the first isolation layer 30 is arranged between the substrate 10 and the first fin body 111 between the first fin body 111 and the substrate 10; the interface oxide layer 50 surrounds the nanowire structure 120; the ferroelectric layer 60 surrounds the interface oxide layer 50; the gate 80 surrounds the ferroelectric layer 60; The source/drain 40 is located in the first region and the third region, and the source/drain 40 is connected to both ends of the nanowire structure 120 .

FIG. 17 does not show the gate 80 in the above-mentioned gate-all-around nanowire field effect transistor. The cross-sectional schematic diagram of the nanowire structure surrounded by the interface oxide layer 50 , the ferroelectric layer 60 and the gate 80 is shown in FIG. 18 .

In the above-mentioned gate-all-around nanowire field effect transistor of the present invention, since the grid is surrounded by the nanowire structure used to form the channel, the gate control capability of the device is improved. When the device is turned off, the current carrying capacity in the channel The fins will be completely depleted, which makes the source-drain punch-through leakage current well suppressed; since the above-mentioned first fin body is completely separated from the substrate, the leakage path in the direction of the substrate is isolated, thereby reducing the leakage current of the device; Since only the part of the fin structure that is used as the channel is formed into nanowires, the source/drain can maintain the original shape. On the one hand, the short channel effect is effectively avoided, the sub-threshold characteristics are optimized, and the device can have a lower The parasitic resistance; and, because the material forming the ferroelectric layer is a negative capacitance material, which has polarization characteristics, the subthreshold slope of the device can be greatly lower than 60mV/dec.

The above-mentioned gate-all-around nanowire field-effect transistor of the present invention can be prepared by the above-mentioned preparation method, and the gate-all-around nanowire field effect transistor also includes a second sidewall 250 covering both sides of the gate 80 and spanning the first fin body 111 , The second spacer 250 can isolate the gate 80 from the source/drain 40 .

In the above-mentioned gate-all-around nanowire field effect transistor of the present invention, preferably, the gate-all-around nanowire field effect transistor further includes a work function layer 70, and the work function layer 70 is arranged between the ferroelectric layer 60 and the gate 80, such as Figure 18 shows. The above-mentioned work function layer 70 is used for adjusting the threshold voltage of the device to meet the requirements of high performance devices and low power consumption devices.

From the above description, it can be seen that the above-mentioned embodiments of the present invention have achieved the following technical effects:

1. Since the gate in the gate stack structure wraps the nanowire structure used to form the channel on all sides, the gate control capability of the device is improved. When the device is turned off, the carriers in the channel will be completely consumed As far as possible, this makes the source-drain punch-through leakage current well suppressed;

2. Since the first fin body obtained in the above preparation method is completely separated from the substrate, the leakage path in the direction of the substrate is isolated, thereby reducing the leakage current of the device;

3. Since only the part of the fin structure that is used as the channel is formed into a nanowire, the source/drain can maintain the original shape. On the one hand, the short channel effect is effectively avoided, the sub-threshold characteristic is optimized, and the device can have Lower parasitic resistance;

4. Since the material forming the ferroelectric layer is a negative capacitance material with polarization characteristics, the subthreshold slope of the device can be greatly lower than 60mV/dec;

5. The gate-all-around nanowire field effect transistor also includes a work function layer, which is used to adjust the threshold voltage of the device and meet the requirements of high performance devices and low power consumption devices.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (17)

1. a kind of preparation method of ring gate nano line field-effect transistor, which is characterized in that include the following steps：

S1, forms the first fin body (111) for being isolated with the substrate (10) on substrate (10), the first fin body (111) by First area connected in sequence, second area and third region composition along its length；

The second area in the first fin body (111) is formed nano thread structure (120) by S2；

S3 sequentially forms interface oxide layer (50), the ferroelectric layer (60) of stacking around the exposed surface of the nano thread structure (120) With grid (80),

And the preparation method is further comprising the steps of：

Source/drain (40), the source/drain (40) and the nano wire are formed in the first area and the third region The both ends of structure (120) connect.

2. preparation method according to claim 1, which is characterized in that the step S1 includes the following steps：

S11, forms fin structure (110) on substrate (10), and the both sides of the fin structure (110) have opposite groove；

S12 aoxidizes the fin structure (110), wherein the position of the corresponding fin structure (110) of the groove is by complete oxygen Change so that the fin structure (110) forms the independent first fin body (111) and the second fin body (112), the first fin body (111) it is located at side of the second fin body (112) far from the substrate (10)；

S13, the deposition of insulative material on the substrate (10) cover the first fin body (111) and second fin to be formed The first separation layer (30) of body (112)；

S14 carries out planarization process to first separation layer (30), so that first separation layer (30) and first fin The upper surface flush of body (111).

3. preparation method according to claim 2, which is characterized in that the step S11 includes following procedure：

S111 sequentially forms the second separation layer (210), sacrificial layer (220) and mask layer (230) on the substrate (10)；

S112, using the patterning process removal part sacrificial layer (220) and the mask layer (230), so that described in part Second separation layer (210) surface exposure；

S113 removes the remaining mask layer (230), and formed on second separation layer (210) be covered in it is described sacrificial First side wall (240) of domestic animal layer (220) both sides；

S114, removes the remaining sacrificial layer (220), and is that mask removes part described the with first side wall (240) Two separation layers (210) and the part substrate (10), part corresponding with the first side wall (240) substrate (10) protrusion The fin structure (110) is formed, while the both sides of the fin structure (110) are formed with the groove, the groove is by the fin It is extended at 1/3 height of structure (110) at 2/3 height.

4. preparation method according to claim 3, which is characterized in that the process for forming the fin structure (110) includes：

Using anisotropic etch process removal part second separation layer (210) and the part substrate (10), so that surplus The remaining substrate (10) has bulge-structure；

The groove is formed in the both sides of the bulge-structure using isotropic etching technique；

The part substrate (10) below the groove is located at using anisotropic etch process removal, to be formed with described The fin structure (110) of groove.

5. preparation method according to claim 2, which is characterized in that between the step S1 and the step S2, institute It is further comprising the steps of to state preparation method：

Etching removal part first separation layer (30) since the surface of first separation layer (30), so that described in part First fin body (111) is exposed；

The false grid formed on remaining first separation layer (30) across part the first fin body (111) stack, and in institute State second side wall of the both sides formation across part the first fin body (111) of false grid stacking；

It removes the false grid to stack, part the first fin body (111) between second side wall is secondth area Domain.

6. preparation method according to claim 5, which is characterized in that before removing the step of false grid stack, The source/drain (40) is formed in the first area and the third region, and makes the source/drain (40) and the step The both ends of the nano thread structure (120) formed in S2 connect.

7. preparation method according to claim 1, which is characterized in that the step S2 includes：

Keep the second area in the first fin body (111) completely exposed, under an atmosphere of hydrogen to the second area into Part the first fin body (111) is formed nano thread structure (120), the pressure of the preferably described atmosphere of hydrogen by row annealing It is 10~50mT by force, the temperature of the annealing is 650~950 DEG C, and the time is 10~300s；Or

Make the second area partial oxidation in the first fin body (111), the second area is formed into nanowire-junction The oxide layer (113) of structure (120) and the package nano thread structure (120), removes the oxide layer (113) so that described receive Nanowire structure (120) is exposed, it is preferred to use wet-etching technology removes the oxide layer (113), the wet-etching technology Corrosive agent includes DHF.

8. preparation method according to claim 1, which is characterized in that in the step S3, using ozone treatment around institute The exposed surface for stating nano thread structure (120) forms the interface oxide layer (50).

9. preparation method according to claim 1, which is characterized in that in the step S3, using atomic layer deposition work Skill forms the ferroelectric layer (60) around the exposed surface of the interface oxide layer (50).

10. preparation method according to claim 1, which is characterized in that the material for forming the ferroelectric layer (60) includes HfZrO and/or HfSiO.

11. preparation method according to claim 1, which is characterized in that forming the ferroelectric layer (60) and the grid (80) between the step of, the step S3 is further comprising the steps of：

Work-function layer (70) is formed around the periphery of the ferroelectric layer (60).

12. preparation method according to claim 11, which is characterized in that using atom layer deposition process around the ferroelectric layer (60) exposed surface forms the work-function layer (70).

13. preparation method according to claim 11, which is characterized in that

The substrate (10) is n-type doping, and the energy gap of the work-function layer (70) is 4.1~4.4eV, is preferably formed as the work content The material of several layers (70) is TiAl；Or

The substrate (10) is adulterated for p-type, and the energy gap of the work-function layer (70) is 4.7~4.9eV, is preferably formed as the work content The material of several layers (70) is TiN.

14. preparation method according to claim 1, which is characterized in that after the step of forming grid (80), The source/drain (40) is formed in the first area and the third region, and makes the source/drain (40) and the step The both ends of the nano thread structure (120) formed in S2 connect.

15. a kind of ring gate nano line field-effect transistor, which is characterized in that including：

Substrate (10)；

First fin body (111) is located on the substrate (10), and the first fin body (111) is by connected in sequence along its length First area, second area and third region composition, and the second area is nano thread structure (120)；

First separation layer (30) is set between the substrate (10) and the first fin body (111), is used for first fin Body (111) is isolated with the substrate (10)；

Interface oxide layer (50), around the nano thread structure (120)；

Ferroelectric layer (60), around the interface oxide layer (50)；

Grid (80), around the ferroelectric layer (60)；And

Source/drain is located in the first area and the third region, and the source/drain and the nano thread structure (120) both ends connection.

16. ring gate nano line field-effect transistor according to claim 15, which is characterized in that ring gate nano line field Effect transistor further includes the work-function layer (70) around the ferroelectric layer (60), and the work-function layer (70) is set to the iron Between electric layer (60) and the grid (80).

17. ring gate nano line field-effect transistor according to claim 15, which is characterized in that ring gate nano line field Effect transistor further includes covering grid (80) both sides and across the second side wall (250) of the first fin body (111).