CN109904236A - Manufacturing method of field effect transistor and field effect transistor - Google Patents
Manufacturing method of field effect transistor and field effect transistor Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000002070 nanowire Substances 0.000 claims abstract description 137
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 230000000694 effects Effects 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 127
- 238000000137 annealing Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 13
- 238000000407 epitaxy Methods 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 12
- 229910010038 TiAl Inorganic materials 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000003475 lamination Methods 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 230000005621 ferroelectricity Effects 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910004129 HfSiO Inorganic materials 0.000 claims description 6
- 229910010041 TiAlC Inorganic materials 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000010521 absorption reaction Methods 0.000 claims description 4
- 230000009471 action Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 3
- 229910015844 BCl3 Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 3
- 229910003855 HfAlO Inorganic materials 0.000 claims description 3
- 229910004490 TaAl Inorganic materials 0.000 claims description 3
- 241000946381 Timon Species 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 150000004678 hydrides Chemical class 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000005457 optimization Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- 229910052712 strontium Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 229910004166 TaN Inorganic materials 0.000 claims 1
- 229910034327 TiC Inorganic materials 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910003468 tantalcarbide Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005549 size reduction Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 210000000720 eyelash Anatomy 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a field effect transistor and the field effect transistor, wherein the method comprises the following steps: forming P-type MOSFET regions on a substrate, the P-type MOSFET regions being separated by shallow trench isolation regions; forming a hard mask pattern in the P-type MOSFET region; forming a silicon nanowire array structure comprising a plurality of stacked layers of silicon nanowires; carrying out SiGe selective epitaxial growth and concentrated oxidation on the silicon nanowire, and removing an oxidation layer to obtain a SiGe nanowire array structure; and sequentially forming an interface oxide layer, a ferroelectric material gate dielectric stack and a metal gate stack at the nanowire array structure. The field effect transistor not only greatly enhances the grid control capability due to the surrounding grid structure, but also improves the hole mobility due to the PMOSFET SiGe nanowire, and particularly, the surface potential of a channel is amplified due to the introduction of the ferroelectric negative capacitance effect, so that a nanowire device has an ultra-steep subthreshold slope and an improved on/off current ratio.
Description
Technical field
The disclosure belongs to technical field of semiconductors, is related to the production method and field-effect tube of a kind of field-effect tube.
Background technique
As integrated circuit feature size is smaller and smaller, planar CMOS device encounters serious challenge, various new device junctions
Structure comes into being, and device gate structures develop to the gate-all-around structure of double grid, three grid to fully wrapped around channel from traditional plane list grid,
Grid-control ability and the ability of control short-channel effect constantly enhance, the nano wire gate-all-around structure with quasi- ballistic transport characteristic
(GAA) MOSFET is paid much attention to extensively due to the ability with extremely strong grid-control ability and size reduction, becomes 3nm
And following technology is for strong competitor.But when device size enters 2 nanometers or less technology nodes, GAA nano wire or receive
Rice piece device also will be unable to meet the further miniature needs of size.This is because GAA device is similarly subjected to Boltzmann theory
Limitation, SS can only infinite approach and 60mV/dec cannot be less than.It is limited by subthreshold swing, if constantly reducing threshold value
Voltage (VT), it will cause OFF state electric leakage (IOFF) exponentially to increase, to make element leakage power consumption ramp, therefore Bohr
The operating voltage that hereby graceful theory limits device can not be reduced with device feature size to be further decreased, before integrated circuit is faced with
The challenge not having.Traditional Boltzmann theory limitation is broken through, the research for carrying out the super new device of steep subthreshold swing is compeled in eyebrow
Eyelash.By years of researches, the super steep subthreshold swing device based on different mechanisms is put forward one after another, and mainly includes ionization by collision
MOSFET (IMOS, Impact-ionization MOS), tunneling field-effect transistor (TFET, Tunneling FET), machine of receiving
Field effect transistor (NEMFET, Nano-Electro-Mechanical FET), spin fet (Spin-
) and negative capacitance field effect transistor (NCFET, Negative-capacitance FET) etc. FET.In these new device knots
In structure, IMOS and TFET rely primarily on ionization by collision and band-to-band-tunneling working principle and device are caused to be difficult to meet high saturation current
It is required that limiting its application in high performance integrated circuit.NEMFET realizes switch operation, production using micro electronmechanical principle
Complex process, can not be compatible with traditional cmos process.Spin fet, element manufacturing difficulty is larger, and needs efficient
The spin of rate is injected and is detected to realize sufficiently large on/off ratio.And hafnium oxide (the HfO based on alternative gate2) base ferroelectric material
NCFET it is compatible with the CMOS technology of mainstream, use the HfO of doping2Based ferroelectric film material replaces original HfO2High k grid
Medium utilizes HfO2The negative capacitance effect of base ferroelectric material realizes the amplification of channel surface potential, thus breaks through subthreshold swing
Boltzmann limitation, realizes super steep subthreshold swing.The calculation formula of subthreshold swing are as follows: SS=dVG/d (logISD)=
(dVG/d ψ S) .d ψ S/d (logISD)=(1+CS/Cins) (kT/q) ln10, wherein VG is gate voltage, and ISD is source-drain current, ψ
S is semiconductor channel surface potential, and CS is channel semiconductor capacitor, and Cins is gate dielectric capacitance, and k is Boltzmann constant, T
For temperature, q is electron charge.By the formula it is found that (kT/q) ln10 is about at room temperature 60mV/dec, if therefore making SS
Less than 60mV/dec, then crucial (1+CS/Cins) item.And CS and Cins is positive value in conventional field effect transistor, leads to (1+
CS/Cins) forever can not be less than 1, the negative capacitance effect that also can not be just less than 60mV/dec. and ferroelectric material can make ferroelectric capacitor
For negative value, i.e. CF < 0.Therefore ferroelectric material is replaced into conventional gate dielectric material, i.e., replaces Cins with CF, (1+ can be realized
Cs/CF) < 1, finally SS is made to be lower than 60mV/dec at room temperature.NCFET has the saturation conduction electricity to compare favourably with conventional MOS FET
Stream, higher ON/OFF electric current ratio meet the requirement of high performance integrated circuit, it is considered to be 3nm and the high property of following technology node
The optimal solution of energy low power consumption integrated circuit technology.Therefore negative capacitance effect is integrated into SiGe nano-wire array ring grid knot
The PMOSFET of structure is strong combination, is an optimal selection.Simultaneously in view of SiGe nano wire is due to its good manufacture craft
Compatibility and have been favored by people, SiGe nano wire is the first choice of PMOSFET due to there is higher hole mobility.It is so far
Only, it is reported production SiGe nano wire complex process, using Si/SiGe alternating extension big cordovan scholar vacation grid technique at
This valuableness, and the size reduction of nano wire has certain limitation.
Therefore, it is necessary to propose that a kind of being easily integrated, manufacture craft is simple, a kind of ferroelectricity material compatible with CMOS technology
Expect negative capacitance SiGe nanometers of wire loop grid p-type field-effect tube structure and preparation method thereof.
Summary of the invention
In view of the above problems, present disclose provides a kind of production method of field-effect tube and field-effect tube, by the method
Field-effect tube obtained is not only due to enclosing structure and has greatly reinforced grid-control ability, due also to PMOSFET SiGe nano wire mentions
High hole mobility amplifies channel surface potential especially because introducing negative capacitance effect, to make nano wire
Device has the ON/OFF electric current ratio of super steep sub-threshold slope and raising.
According to one aspect of the disclosure, a kind of production method of field-effect tube is provided, comprising:
P-type MOSFET region is formed on the substrate, the p-type MOSFET region is separated by shallow channel isolation area；
Hard mask pattern is formed in the p-type MOSFET region；
Silicon nanowire array structure is formed, the silicon nanowire array structure includes the silicon nanowires of multiple-level stack；
The growth of SiGe selective epitaxy and concentration oxidation are carried out on the silicon nanowires of the multiple-level stack, obtain SiGe nanometers
Linear array structure；And
Interfacial oxide layer, ferroelectric material gate medium lamination and metal are sequentially formed at the nanowire array structure
Gate stack；
Wherein, anisotropy is used alternatingly using repetition in the silicon nanowire array structure and isotropic plasma is carved
It loses the p-type MOSFET region to be formed, the metal gate stack wraps up the ferroelectric material gate medium lamination, including the first metal
Grid 3 and the second Metal gate layer.
Optionally, described that the growth of SiGe selective epitaxy is carried out on the silicon nanowires of the multiple-level stack, it obtains SiGe and receives
Nanowire arrays structure includes:
The growth of SiGe selective epitaxy is carried out on the silicon nanowires；
Si protective film is formed on the SiGe selective epitaxy grown layer；
Concentration oxidation is carried out at a set temperature；
Remove oxide layer, obtains SiGe nanowire array structure.
Optionally, for the temperature of the concentration oxidation between 750 DEG C~900 DEG C, the time is 8 hours~15 hours；With/
Or the thickness of the selective epitaxy grown layer, between 5nm~20nm, the thickness of protective film is between 0~3nm.
Optionally, the formation silicon nanowire array structure includes:
Passivation, the surface of the nanowire structure of using plasma oxidation exposure, forms passivating film after every step etches；And
Using the passivating film of CF4 anisortopicpiston removal substrate surface.
Optionally, interfacial oxide layer, ferroelectric material gate medium lamination are sequentially formed at the nanowire array structure
And metal gate stack includes:
Formed on the substrate of the p-type MOSFET region false gate stack, around false gate stack grid curb wall and
Source/drain region；
The false gate stack in the p-type MOSFET region is removed to form gate openings on the inside of grid curb wall, makes nanometer
Expose on the surface of linear array structure groove；
Interfacial oxide layer, ferroelectric material gate dielectric layer and are sequentially formed at the gate openings of p-type MOSFET region
One Metal gate layer；
P-type doping is carried out to first Metal gate layer, and dopant dose is controlled according to desired threshold voltage；And
The second Metal gate layer is formed on first Metal gate layer, and is made annealing treatment；
Wherein, first Metal gate layer is realized using isotropic plasma doping p-type (PMOSFET) dopant
The adjusting of work function, or the work function that PMOSFET is required is adjusted using p-type workfunction metal grid, second Metal gate layer covers
It covers first Metal gate layer and is made annealing treatment, interface is on the one hand made to form dipole, adjust effective work function；It is another simultaneously
On the one hand due to metal electrode clamping action in annealing process, the generation of negative capacitance effect is induced.
Optionally, described false gate stack to be formed on the substrate of p-type MOSFET region, around the gate electrode side of false gate stack
Wall and source/drain region include:
After the grid curb wall is formed, the source/drain region silicon etching is carried out；
Appropriate over etching is carried out to the side wall, forms corresponding inner recess around nano wire；And
It carries out P and adulterates SiGe selective epitaxial, form P+SiGe source /drain region.
Optionally, false gate stack is formed above the substrate of the p-type MOSFET region, around the gate electrode side of false gate stack
False gate stack in wall and source/drain region and the removal p-type MOSFET region is opened with forming grid on the inside of grid curb wall
Mouthful, make nanowire array structure groove surface expose the step of between, further includes:
Silicification area is formed, positioned at the surface of the source/drain region；
Interlayer dielectric layer is formed, the top of the source/drain region is covered on, is around the grid curb wall outer surface and described
The top of false gate stack；And
The surface of polishing planarization interlayer dielectric layer and the top surface of the false grid conductor of exposure；
Wherein, the false gate stack includes: false gate oxide dielectrics and false grid conductor, is planarized using chemically mechanical polishing
Interlayer dielectric layer.
Optionally, the condition made annealing treatment is as follows: short annealing temperature is 350 DEG C -950 DEG C, annealing time
For 20min-40min.
Optionally, the annealing includes that PMA makes annealing treatment, Spike annealing and laser annealing processing, Ke Yigen
It is determined according to ferroelectric media material thermal characteristics.
Optionally, the anisotropic plasma etch uses HBr/Cl2/O2/ He plasma；And/or
The isotropic etching uses SF6/ He plasma；And/or
The energy of anisotropic plasma etch is between 150W~500W；When using HBr, Cl2Plasma into
When row anisotropic plasma etch, Cl2: HBr is between 1:1~1:5, additive O2；And/or
The energy of isotropic plasma etching is between 200W~800W；When using SF6, He carry out isotropism
When plasma etching, SF6: He is between 1:3~1:20.
Optionally, the P-type dopant includes: the hydride, fluoride or chloride of boron, is one of following material
Or combinations thereof: B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3, in addition p-type workfunction metal grid metal is to make Effective power
The increased metal of function, including Pt, Ni, Ir, Re, Mo, Co, TiN, TiNC, MoN and WN are a kind of or combine.
According to another aspect of the present invention, a kind of field-effect tube is provided, comprising:
Substrate；
Shallow trench is located on the substrate, the substrate is separated out p-type MOSFET region；
SiGe nanowire array structure is located on the substrate between the multiple shallow trench；
Interfacial oxide layer, ferroelectric material gate medium lamination and metal gate stack, are sequentially located at the nano-wire array
Body structure surface；
Source region and drain region are located between the nanowire array structure and the shallow trench.
Optionally, the SiGe nanowire array structure includes the SiGe nano wire of multiple-level stack.
Optionally, the metal gate stack includes the first Metal gate layer and the second Metal gate layer.
Optionally, the material of the interfacial oxide layer includes: SiO2、SiON、HfO2、ZrO2、Al2O3、HfSiO、
HfSiON、HfAlON、Y2O3、La2O3Or HfLaON is one such or combinations thereof.
Optionally, the interfacial oxide layer is between 0.5~1.5nm；The thickness of the ferroelectricity gate dielectric layer between
Between 1.5nm~10nm；The thickness of first Metal gate layer is between 1nm~10nm.
Optionally, the ferroelectric material gate dielectric layer is doping Hf base oxide, one kind or its group including following material
It closes: HfZrO, HfZrAlO, HfAlO, HfSiO, HfLaO, HfSrO, HfGdO or HfYO.
Optionally, it is described doping hafnium oxide base (HfO) ferroelectric material gate dielectric layer ferroelectric properties power also with it is therein
The content of doped chemical is closely related, if the optimization percentage composition of Zr, Si, Y, Al, Gd, Sr and La are respectively 30- than range
60%, 3-6%, 4-6.5%, 3.5-6.5%, 1.5-5%, 8-12% and 3-6%.
Optionally, the material of first Metal gate layer includes one of following material or combinations thereof: Mo, Ti, W,
TiN、TiC、TiAl、TiAlC、TaC、TaN、TaAlC、TaAl、TaCN、NbAlC、TiMoN、MoN、WN、TiWN。
Optionally, second Metal gate layer includes multiple layer metal material, wherein abutting the metal material of the first Metal gate layer
The good metal of material selection oxygen absorption performance, comprising: at least one of Ti, TiAl, Ta；Followed by potential barrier barrier metal, comprising:
One or both of TiN, TaN, Ta, MoN, AlN or WN；It is finally filling metal, comprising: W, Al, TiAl, TiAlC or Mo
One of or it is a variety of.
The production method and field-effect tube for the field-effect tube that the disclosure provides, have the advantages that
Silicon nanowire array structure is made to p-type MOSFET region first, wherein silicon nanowire array structure can be by silicon
Substrate etches alternate mode using anisotropic plasma etch and isotropic plasma and etches to obtain, and passes through simultaneously
Control etching parameters are more easily implemented the diminution of nanowire size, obtain desired nanowire size and Cross Section Morphology；And pass through
The oxidation of nano wire sacrifice further obtains desired nanowire size and circular cross-section pattern using oxidation stress effect, to obtain
Optimal grid-control characteristic is obtained, while eliminating nanowire surface damage；And SiGe nanowire array structure is by silicon nanometer
The growth of SiGe selective epitaxy is carried out on line, and covering Si film may be selected on SiGe as protective film, then carry out at a predetermined temperature
Concentration oxidation obtains；SiGe nanometers of wire loop grid PMOSFET improve hole mobility, at the same SiGe source/drain generate to channel
Compression further improved sky cave mobility.And since the gate-all-around structure of nano wire substantially increases grid-control ability,
Admirably inhibit short-channel effect.The SiGe nano-wire array ring grid PMOSFET structure of the especially disclosure is integrated with negative electricity
Hold effect, effectively improve the surface potential of device channel, be larger than applied gate voltage, that is, realize voltage amplification effect,
The Boltzmann limitation for breaching subthreshold swing, realizes super steep subthreshold swing, higher ON/OFF electric current ratio is met
The requirement of high performance integrated circuit.Therefore it is strong for negative capacitance effect being integrated into the PMOSFET of GeSi nano wire gate-all-around structure
It is strong to combine, it is a kind of optimal selection, makes it possible that device feature size is further reduced to 2 nm technology generations.
And a kind of above-mentioned ferroelectric material negative capacitance SiGe nano-wire array ring grid PMOSFET and traditional industry CMOS technology
Completely compatible, simple process, cost is relatively low, has fabulous industrialization prospect.
Detailed description of the invention
Fig. 1 is the production method flow chart of the field-effect tube according to shown in one embodiment of the disclosure.
Fig. 2 a- Fig. 2 e shows the sectional view in each stage of field-effect tube manufacturing method according to an embodiment of the present invention.
10- substrate；The shallow channel isolation area 20-；
30- exposure mask；
31-PE SiO2；32-αSi；
40- nanowire array structure；50- sacrificial oxide layer；
60- vacation gate stack；
61- vacation gate medium；62- vacation grid conductor；
70- grid curb wall；80- interlayer dielectric layer；
81- source region；The drain region 82-；
91- interfacial oxide layer；92- ferroelectric material gate dielectric layer；
93- the first Metal gate layer the second Metal gate layer of 94-.
Specific embodiment
The disclosure is to provide the production method and field-effect tube of a kind of field-effect tube, SiGe nanometers of wire loop grid PMOSFET
Improve hole mobility, at the same SiGe source/drain generate hole mobility is further improved to the compression of channel.And
Since the gate-all-around structure of nano wire substantially increases grid-control ability, short-channel effect is admirably inhibited.The especially disclosure
Nano-wire array encloses grid PMOSFET structure and is integrated with negative capacitance effect, effectively improves the surface potential of device channel, keeps it big
In applied gate voltage, that is, voltage amplification effect is realized, breaches the Boltzmann limitation of subthreshold swing, realize super steep Asia
The threshold value amplitude of oscillation, higher ON/OFF electric current ratio, meets the requirement of high-performance PMOSFET.Therefore ferroelectricity negative capacitance effect is integrated
It is strong combination into the PMOSFET of SiGe nano wire gate-all-around structure, is a kind of optimal selection, keeps device feature size further
2 nm technology generations are narrowed down to be possibly realized.And a kind of above-mentioned ferroelectric material negative capacitance SiGe nano-wire array ring grid PMOSFET
Completely compatible with traditional industry CMOS technology, simple process, cost is relatively low, has fabulous industrialization prospect.
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
The disclosure is further described in attached drawing.
In the disclosure, term " semiconductor device structure " refers to forms after each step of experience production semiconductor devices
Substrate 10 and all layers formed on substrate 10 or region.Term " P-type dopant " refers to for p-type MOSFET's
The dopant of effective work function can be increased.Term " source/drain region 81/82 " refers to source region 81 and the drain region 82 2 of a MOSFET
Person.Term " between " includes two endpoint values.In the following description, regardless of whether showing in different embodiments, class
As component using same or similar appended drawing reference indicate.In various figures, for the sake of clarity, each portion in attached drawing
Divide and is not necessarily to scale.When may cause understanding of this disclosure and cause to obscure, conventional structure or construction will be omitted.And
The shape and size of each component do not reflect actual size and ratio in figure, and only illustrate the content of the embodiment of the present disclosure.Attached drawing figure
Filler in 2c and Fig. 2 d in gate openings indicates identical structure using identical filling-tag.
It should be noted that semiconductor structure is all made of cross-sectional view and is illustrated, and cross section refers to nano wire in attached drawing
Cross section.
In an exemplary embodiment of the disclosure, a kind of ferroelectric material negative capacitance SiGe nano-wire array ring grid are provided
The production method of PMOSFET.
Fig. 1 is the production method flow chart of the field-effect tube according to shown in one embodiment of the disclosure.
Shown in referring to Fig.1, the production method of the field-effect tube with nano wire of the disclosure, comprising:
Step S101: the p-type MOSFET region separated by shallow channel isolation area 20 is formed on substrate 10, in substrate 10
Upper deposit SiO2The hard exposure mask 30 of/α-Si.
The substrate 10 of the disclosure is common semiconductor substrate 10, can be silicon substrate 10, SOI substrate 10 and other half
Conductor substrate 10.Due in the next steps, nanowire array structure 40 being made in p-type MOSFET region, in body silicon substrate 10
Upper production nano wire, which compares the production nano wire in SOI substrate 10, obviously advantage, such as: eliminating SOI substrate 10
Self-heating effect and floater effect；Avoid complicated source and drain engineering；10 cost of body silicon substrate is much lower；With conventional bulk silicon
CMOS technology is more compatible etc., therefore the preferred silicon substrate 10 of semiconductor substrate 10 in the present embodiment.
The ferroelectric material negative capacitance nano-wire array gate-all-around structure of the disclosure is the device architecture of p-type MOSFET region.
Step S102: making hard 30 pattern of exposure mask of nano wire by lithography on substrate 10, and alternately using anisotropy and it is each to
Same sex plasma etching forms the silicon nanowire structure stacked.
Fig. 2 a is that cuing open along what cross-sectional direction was splitted for the hard exposure mask 30 of 31/ α Si of PE SiO2 32 is deposited on substrate 10
Face structural schematic diagram.Fig. 2 b is that isotropism and the method for anisotropic plasma etch are used to Si substrate 10 alternately
The schematic diagram of the section structure splitted after the nanowire array structure 40 that Multilayered Nanowires stack along cross section is formed after etching.
Nano-material is selected from Si, SiGe, Ge, iii-v, II-VI group and metal and its silicide etc..This implementation
It is illustrated so that p-type MOSFET region includes SiGe nano wire as an example in example.
In the present embodiment, referring to shown in Fig. 2 a, the exposure mask 30 that photoetching uses is hard exposure mask 30, including the PE being sequentially depositing
In SiO2 31 and α Si 32, this step S2, after forming hard exposure mask 30, whirl coating, exposure, development etc. are carried out on hard exposure mask 30
Lithography step forms the glue pattern of one layer of nano wire, then etches hard exposure mask 30 using the method for dry etching, then removes light
Photoresist forms the hard exposure mask 30 of silicon nanowires.
Step S103: dry etching forms bulk silicon nano line stacked structure: anisotropic etching and isotropic etching are handed over
For progress, the silicon face of the nanowire structure with plasma oxidation exposure is during which needed after every step etching, to form passivating film,
Not damage established nanowire structure in back to back subsequent etching, the protection to silicon nanowire structure is realized.Respectively to
Anisotropic etch uses HBr/Cl2/O2/ He plasma carries out；Isotropic etching uses SF6/ He plasma carries out；Blunt
Change in step, aoxidized using oxygen plasma, anisotropic plasma etch is then carried out using CF4, only removal half
The silicon oxide passivation layer on 10 surface of conductor substrate, with going on smoothly for sharp subsequent etching, and according to desired nanowire structure
Size and shape adjusts the parameters such as etching power, gas composition and etch period.
Wherein, anisotropic plasma etch uses HBr, Cl2、O2, He plasma；Isotropic etching uses
SF6, He plasma.
In the present embodiment, the energy of anisotropic plasma etch is between 150W~500W；Cl2: HBr is between 1:
It, can be with doping O between 1~1:52。
In the present embodiment, the energy of isotropic plasma etching is between 200W~800W；SF6: He is between 1:3
Between~1:20.
In the present embodiment, the silicon nanowire array structure 40 that Multilayered Nanowires that step S103 is obtained stack b referring to fig. 2
Shown, the present embodiment is only illustrated with the structure that 3 layers of nano wire stacks, but the disclosure does not limit the number of plies of nano wire.
Step S104: forming sacrificial oxide layer 50 on every nano wire of silicon nanowire array structure 40, is received with regulation
Then the size and shape of rice noodles removes sacrificial oxide layer 50.
Fig. 2 c is to cut open after forming sacrificial oxide layer 50 on every nano wire of nanowire array structure 40 along cross section
The schematic diagram of the section structure opened, at this time nanowire cross-section size reduction, and close circle.
Referring to shown in Fig. 2 c, sacrificial oxide layer 50 is formed on every nano wire of nanowire array structure 40, with removal
Etching injury and further control nanowire structure size and shape, in the present embodiment, in silicon nanowire array structure 40
It is formed after sacrificial oxide layer 50 on each nano wire, due to the effect of stress, the size and shape of nanowire array structure 40
Regulated and controled, obtains circular shape as shown in Figure 2 c；Then sacrificial oxide layer 50 is removed.
Step S105: to p-type MOSFET region, the growth of SiGe selective epitaxy is carried out on silicon nanowires, SiGe is upper optional
Covering Si protective film is selected, concentration oxidation is then carried out at a set temperature, obtains the SiGe nano-wire array knot of Ge high-content
Structure 40.
In the present embodiment, to p-type MOSFET region, the growth of SiGe selective epitaxy is carried out on silicon nanowires, on SiGe
Covering may be selected or do not cover Si protective film, then carry out concentration oxidation at a predetermined temperature, internal Si atom is to extending out
It is scattered at SiO2It is consumed, the SiGe nanowire array structure 40 to form Ge high-content is concentrated in Ge.
In the present embodiment, the thickness of SiGe selective epitaxy growth covers Si film between 0~3nm between 5nm~20nm
Between, wherein 0 indicates not covering Si film as protective layer；The temperature of oxidation is concentrated between 750 DEG C~900 DEG C in SiGe, when
Between be 8 hours~15 hours.
Step S106: false gate stack 60 is formed above the substrate 10 of p-type MOSFET region, around the grid of false gate stack 60
Pole side wall 70 and source/drain region 81/82.
Fig. 2 d is false gate stack 60 to be formed above the substrate 10 of p-type MOSFET region, around the grid of false gate stack 60
Vertical section structure schematic diagram is axially splitted along nano wire behind side wall 70 and source/drain region 81/82.
In the present embodiment, false gate stack 6060 is formed, around false gate stack 60 in the top of the substrate 10 in the region PMOSFET
Grid curb wall 70 and source region 81, drain region 82, as shown in Figure 2 d.For p-type MOSFET region, nano-wire array knot
Structure 40 is SiGe nanowire array structure 40, and forming process is as shown in step S101-S105.
In the present embodiment, the source/drain region 81/82 of p-type MOSFET region is P+SiGe source/drain, it is in grid curb wall 70
After formation, the silicon of the source/drain region p-type MOSFET 81/82 is performed etching, and then the appropriate over etching of SiN side wall is formed corresponding
Inner recess is around SiGe nano wire；Then it carries out B and adulterates SiGe selective epitaxial, form P+81/ drain region 82 of SiGe source region.
In the present embodiment, the false gate stack 60 of formation includes: false gate medium 61 and false grid conductor 62, the material of false gate medium 61
Expect that such as silica, the material of false grid conductor 62 can be polysilicon, α Si32 etc..
Step S107: the false gate stack 60 in removal p-type MOSFET region is opened with forming grid on the inside of grid curb wall 70
Mouthful, so that the surface of 40 groove of nanowire array structure is exposed.
Step S108: at the gate openings of p-type MOSFET region around SiGe nanowire array structure 40 successively
Form interfacial oxide layer 91, ferroelectric material gate dielectric layer 92 and the first Metal gate layer 93.
In the present embodiment, the interfacial oxide layer is one kind or combinations thereof of following material: SiO2、SiON、HfO2、
ZrO2、Al2O3、AlN、HfSiO、HfSiON、HfAlON、Y2O3、La2O3Or HfLaON；And/or
In the present embodiment, the ferroelectric material gate dielectric layer be doping Hf base oxide, be following material one kind or its
Combination: HfZrO, HfZrAlO, HfAlO, HfSiO, HfLaO, HfSrO, HfGdO or HfYO.
The ferroelectric properties power of the doping hafnium oxide base ferroelectric media film is also close with the content of doped chemical therein
Cut phase is closed, if the optimization percentage composition of Zr, Si, Y, Al, Gd, Sr and La are respectively 30-60%, 3-6%, 4-6.5% than range,
3.5-6.5%, 1.5-4%, 8-12% and 2-5%.
In the present embodiment, the material of first Metal gate layer 93 is one of following material or combinations thereof: Mo, Ti,
W、TiN、TiC、TiAl、TiAlC、TaC、TaN、TaAlC、TaAl、TaCN、NbAlC、TiMoN、MoN、WN、TiWN。
In the present embodiment, second Metal gate layer 94 includes multiple layer metal material, wherein abutting the first Metal gate layer 93
The good metal of metal material selection oxygen absorption performance, comprising: at least one of Ti, TiAl, Ta；Followed by potential barrier barrier layer gold
Belong to, comprising: one or both of TiN, TaN, Ta, MoN, AlN or WN；It is finally filling metal, comprising: W, Al, TiAl,
One of TiAlC or Mo or a variety of.
In the present embodiment, the interfacial oxide layer is between 0.5~1.5nm；The thickness of the ferroelectricity gate dielectric layer
Between 1.5nm~10nm；And the thickness of first Metal gate layer 93 is between 1nm~10nm.
Step S109: utilize isotropic plasma doping in the first Metal gate layer 93 p-type MOSFET region
Doped p-type (PMOSFET) dopant ion, and the energy of plasma is controlled, so that Doped ions are only distributed only over the first gold medal
Belong in grid layer 93, and dopant dose is controlled according to desired threshold voltage；Or use makes the increased p-type metal of effective work function
Grid metal, which is adjusted, obtains the work function that PMODFET is required.
In the present embodiment, the Doped ions of the first metal gate of p-type MOSFET region are the p-type that can increase effective work function
Dopant.P-type dopant includes: the hydride, fluoride or chloride of boron, be can be, but not limited to as one of following material
Or combinations thereof: B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3.In addition p-type metal grid metal is to increase effective work function
The grid metal added, including Pt, Ni, Ir, Re, Mo, Co, TiN, TiNC, MoN and WN one kind or combinations thereof.
Step S110: the second Metal gate layer 94 is formed on the first Metal gate layer 93 after doping and covers the first Metal gate layer
93 to fill gate openings, and carries out PMA annealing, and interface is on the one hand made to form dipole, adjusts effective work function；Simultaneously
On the other hand due to metal electrode clamping action during PMA, the generation of negative capacitance effect is induced.So far SiGe nanometers are completed
Linear array encloses the production of grid PMOSFET structure.
Fig. 2 e is that interfacial oxide layer 91, ferroelectric material grid Jie are sequentially formed at the gate openings of p-type MOSFET region
The vertical section structure schematic diagram splitted after matter layer 92 and Metal gate layer (93+94) along nanometer bobbin thread.Referring to shown in Fig. 2 e, often
Interfacial oxide layer 91, ferroelectricity gate dielectric layer 92 and Metal gate layer (93+94) have been sequentially depositing around a nano wire.
In other embodiments, false gate stack 60 is formed above the substrate 10 of p-type MOSFET region, is folded around false grid
After the step of grid curb wall 70 of layer 60 and source/drain region 81/82, further includes: form silicification area, be located at source/drain region 81/
82 surface；And interlayer dielectric layer 80 is formed, it is covered on top, 70 outer surface of grid curb wall of respective source/drain region 81/82
The top of surrounding and false gate stack 60；The vacation gate stack 60 includes: false gate medium 61 and false grid conductor 62, and utilizationization
Learn the top surface on the surface of mechanical polishing planarization (CMP) interlayer dielectric layer 80 and the false grid conductor 62 of exposure.Due to silicification area
Setting with interlayer dielectric layer 80 belongs to conventional means, in order to simplify signal, only denotes planarized in Fig. 2 e here
Interlayer dielectric layer 80 later, in Fig. 2 e, grid curb wall 70 also goes through planarization process, and grid curb wall 70 is in figure with identical
Filling indicate.
In the present embodiment, the second Metal gate layer 94 includes multiple layer metal material, wherein abutting the gold of the first Metal gate layer 93
Belong to the good metal of material selection oxygen absorption performance, comprising: at least one of Ti, TiAl, Ta；Followed by potential barrier barrier metal,
It include: TiN, TaN, Ta, MoN, one or both of AlN or WN；It is finally filling metal, comprising: in W, Al, TiAl or Mo
It is one or more.
In the present embodiment, the condition for carrying out PMA annealing is as follows: short annealing temperature is 350 DEG C -950 DEG C, when annealing
Between be 20min-40min；Spike annealing and laser annealing can also be used, determined according to ferroelectric media material thermal characteristics.
In an exemplary embodiment of the disclosure, a kind of field-effect tube is provided, the ferroelectric material negative capacitance nanometer linear array
Column ring grid PMOSFET structure production method as described in the disclosure is made, referring to shown in Fig. 2 e, the field-effect tube of the disclosure, and packet
Include: substrate 10 has the p-type MOSFET region separated by shallow channel isolation area 20 thereon；Source/drain region 81/82 is located at p-type
The both sides of edges of MOSFET region；Nanowire array structure 40 is the stacked structure of Multilayered Nanowires, is located at source region 81 and drain region
Between 82；Interfacial oxide layer 91, ferroelectricity gate medium are sequentially formed with around each nano wire of nanowire array structure 40
The 92, first Metal gate layer 93 of layer and the second Metal gate layer 94；And grid curb wall 70, it is centered around interfacial oxide layer 91, iron
Around electric gate dielectric layer 92, the first Metal gate layer 93 and the second Metal gate layer 94；The wherein nanometer of p-type MOSFET region
Linear array structure 40 is SiGe nanowire array structure 40, the SiGe nano wire comprising multiple-level stack；Metal gate layer includes first
Metal gate layer 93 and the second Metal gate layer 94, the first Metal gate layer 93 use isotropic plasma doping p-type
(PMOSFET) dopant, the second Metal gate layer 94 cover the first Metal gate layer 93 to fill gate openings, then move back by PMA
Fire processing, on the one hand forms interface dipole, adjusts effective work function；Simultaneously on the other hand due to metal electrode during PMA
Clamping action induces the generation of negative capacitance effect.
In other embodiments, false gate stack 60 is formed above the substrate 10 of p-type MOSFET region, is folded around false grid
After the step of grid curb wall 70 of layer 60 and source/drain region 82, further includes: form silicification area, be located at respective source/drain region
81/82 surface；And interlayer dielectric layer 80 is formed, it is covered on the top of respective source/drain region 81/82, outside grid curb wall 70
Around the surface and top of false gate stack 60；The vacation gate stack 60 includes: false gate medium 61 and false grid conductor 62, and sharp
With the surface of chemically mechanical polishing planarization (CMP) interlayer dielectric layer 80 and the top surface of the false grid conductor 62 of exposure.Due to S/D
Silicification area is common process, is not indicated in figure here.
In conclusion present disclose provides a kind of nano-wire array ring grid PMOSFET and preparation method thereof, by p-type
MOSFET region makes nanowire array structure 40, wherein silicon nanowire array structure 40 can be from silicon substrate 10 using each to same
Property plasma etching and the alternate mode of anisotropic plasma etch etch to obtain, while by control etching parameters more
It is easily achieved the diminution of nanowire size, obtains desired nanowire size and Cross Section Morphology；And aoxidized by nano wire sacrifice,
Desired nanowire size and circular cross-section pattern are further obtained using oxidation stress effect, it is special to obtain optimal grid-control
Property, while eliminating nanowire surface damage；SiGe nanowire array structure 40 on silicon nanowires by carrying out SiGe selection
Covering Si film may be selected on SiGe as protective film for epitaxial growth, then carry out concentration at a predetermined temperature and aoxidize to obtain；SiGe
Nano wire and SiGe S/D structure ring grid PMOSFET substantially increase hole mobility；And due to the gate-all-around structure of nano wire
Grid-control ability is fundamentally substantially increased, short-channel effect is admirably inhibited.The especially SiGe nanometer linear array of the disclosure
Column ring grid PMOSFET structure is integrated with negative capacitance effect, effectively improves the surface potential of device channel, is larger than additional grid
Voltage realizes voltage amplification effect, breach the Boltzmann limitation of subthreshold swing, realizes super steep subthreshold value pendulum
Width, higher ON/OFF electric current ratio, meets the requirement of high performance integrated circuit.Therefore negative capacitance effect SiGe is integrated into receive
It is strong combination in the PMOSFET of nanowire arrays gate-all-around structure, is a kind of optimal selection, further reduces device feature size
It is possibly realized to 2 nm technology generations.This manufacturing method is completely compatible with CMOS technology simultaneously, and simple process, cost is relatively low, has
Fabulous industrialization prospect.
It should be noted that word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims
Suddenly.Word "a" or "an" located in front of the element does not exclude the presence of multiple such elements.
The word of ordinal number such as " first ", " second ", " third " etc. used in specification and claim, with modification
Corresponding element, itself is not meant to that the element has any ordinal number, does not also represent the suitable of a certain element and another element
Sequence in sequence or manufacturing method, the use of those ordinal numbers are only used to enable an element and another tool with certain name
Clear differentiation can be made by having the element of identical name.
In addition, unless specifically described or the step of must sequentially occur, there is no restriction in the above institute for the sequence of above-mentioned steps
Column, and can change or rearrange according to required design.And above-described embodiment can be based on the considerations of design and reliability, that
This mix and match is used using or with other embodiments mix and match, i.e., the technical characteristic in different embodiments can be freely combined
Form more embodiments.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail it is bright, it is all it should be understood that be not limited to the disclosure the foregoing is merely the specific embodiment of the disclosure
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (21)
1. a kind of production method of field-effect tube, comprising:
P-type MOSFET region is formed on the substrate, the p-type MOSFET region is separated by shallow channel isolation area；
Hard mask pattern is formed in the p-type MOSFET region；
Silicon nanowire array structure is formed, the silicon nanowire array structure includes the silicon nanowires of multiple-level stack；
The growth of SiGe selective epitaxy and concentration oxidation are carried out on the silicon nanowires of the multiple-level stack, oxide layer obtains
SiGe nanowire array structure；And
Interfacial oxide layer, ferroelectric material gate medium lamination and metal are sequentially formed at the SiGe nanowire array structure
Gate stack；
Wherein, anisotropy is used alternatingly using repetition in the silicon nanowire array structure and isotropic plasma etching exists
The p-type MOSFET region is formed, and the metal gate stack wraps up the ferroelectric material gate medium lamination, including the first metal gate
Layer and the second Metal gate layer.
2. manufacturing method according to claim 1, wherein described to carry out SiGe on the silicon nanowires of the multiple-level stack
Selective epitaxy growth, obtaining SiGe nanowire array structure includes:
Selection SiGe epitaxial growth is carried out on the silicon nanowires；
Si protective film is formed on the SiGe epitaxially grown layer；
Concentration oxidation is carried out at a set temperature；
Remove oxide layer, obtains SiGe nanowire array structure.
3. production method according to claim 2, wherein it is described concentration oxidation temperature between 750 DEG C~900 DEG C it
Between, the time is 8 hours~15 hours；And/or the thickness of the selective epitaxy grown layer is between 5nm~20nm, protective film
Thickness between 0~3nm.
4. manufacturing method according to claim 1, wherein the formation silicon nanowire array structure includes:
Passivation, the surface of the nanowire structure of using plasma oxidation exposure, forms passivating film after every step etches；And
Using the passivating film of CF4 anisortopicpiston removal substrate surface.
5. manufacturing method according to claim 1, wherein sequentially form interface oxidation at the nanowire array structure
Nitride layer, ferroelectric material gate medium lamination and metal gate stack include:
False gate stack, grid curb wall and source/drain around false gate stack are formed on the substrate of the p-type MOSFET region
Area；
The false gate stack in the p-type MOSFET region is removed to form gate openings on the inside of grid curb wall, makes a nanometer linear array
Expose on the surface of array structure groove；
Interfacial oxide layer, ferroelectric material gate dielectric layer and the first gold medal are sequentially formed at the gate openings of p-type MOSFET region
Belong to grid layer；
P-type doping is carried out to first Metal gate layer, and dopant dose is controlled according to desired threshold voltage；And
The second Metal gate layer is formed on first Metal gate layer, and is made annealing treatment；
Wherein, first Metal gate layer realizes work content using isotropic plasma doping p-type (PMOSFET) dopant
Several adjustings, or the work function that PMOSFET is required is adjusted using p-type workfunction metal grid, second Metal gate layer covers institute
It states the first Metal gate layer and is made annealing treatment, interface is on the one hand made to form dipole, adjust effective work function；Another party simultaneously
Face induces the generation of negative capacitance effect due to metal electrode clamping action in annealing process.
6. production method according to claim 5, wherein the vacation grid that formed on the substrate of p-type MOSFET region are folded
Layer, the grid curb wall around false gate stack and source/drain region include:
After the grid curb wall is formed, the source/drain region silicon etching is carried out；
Appropriate over etching is carried out to the side wall, forms corresponding inner recess around nano wire；And
It carries out B and adulterates SiGe selective epitaxial, form P+SiGe source /drain region.
7. production method according to claim 5, wherein form false grid above the substrate of the p-type MOSFET region
False gate stack in lamination, the grid curb wall around false gate stack and source/drain region and the removal p-type MOSFET region with
Between the step of forming gate openings on the inside of grid curb wall, exposing the surface of nanowire array structure groove, further includes:
Silicification area is formed, positioned at the surface of the source/drain region；
Interlayer dielectric layer is formed, is covered on the top of the source/drain region, around the grid curb wall outer surface and the false grid
The top of lamination；And
The surface of polishing planarization interlayer dielectric layer and the top surface of the false grid conductor of exposure；
Wherein, the false gate stack includes: false gate oxide dielectrics and false grid conductor, using between chemically mechanical polishing planarization layer
Dielectric layer.
8. production method according to claim 5, wherein the condition made annealing treatment is as follows: short annealing temperature
Degree is 350 DEG C -950 DEG C, annealing time 20min-40min.
9. production method according to claim 5, wherein the annealing includes that RTA makes annealing treatment, Spike annealing
Processing and laser annealing processing, can determine according to ferroelectric media material thermal characteristics.
10. manufacturing method according to claim 1, wherein
The anisotropic plasma etch uses HBr/Cl2/O2/ He plasma；And/or
The isotropic etching uses SF6/ He plasma；And/or
The energy of anisotropic plasma etch is between 150W~500W；When using HBr, Cl2Plasma carry out it is each to
When anisotropic plasma etching, Cl2: HBr is between 1:1~1:5, additive O2；And/or
The energy of isotropic plasma etching is between 200W~800W；When using SF6, He carry out isotropism etc. from
When daughter etches, SF6: He is between 1:3~1:20.
11. manufacturing method according to claim 1, wherein the P-type dopant include: the hydride of boron, fluoride or
Chloride is one of following material or combinations thereof: B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
12. manufacturing method according to claim 1, wherein the p-type workfunction metal grid metal is to make effective work function
Increased metal, including Pt, Ni, Ir, Re, Mo, Co, TiN, TiNC, MoN and WN are a kind of or combine.
13. a kind of field-effect tube, comprising:
Substrate；
Shallow trench is located on the substrate, the substrate is separated out p-type MOSFET region；
SiGe nanowire array structure is located on the substrate between the multiple shallow trench；
Interfacial oxide layer, ferroelectric material gate medium lamination and metal gate stack are sequentially located at the SiGe nano-wire array
Body structure surface；
Source region and drain region are located between the SiGe nanowire array structure and the shallow trench.
14. field-effect tube according to claim 13, wherein the SiGe nanowire array structure includes multiple-level stack
SiGe nano wire.
15. field-effect tube according to claim 13, wherein the metal gate stack includes the first Metal gate layer and second
Metal gate layer.
16. field-effect tube according to claim 13, wherein the material of the interfacial oxide layer includes: SiO2、SiON、
HfO2、ZrO2、Al2O3、HfSiO、HfSiON、HfAlON、Y2O3、La2O3Or HfLaON is one such or combinations thereof.
17. field-effect tube according to claim 13, wherein the interfacial oxide layer is between 0.5~1.5nm；
The thickness of the ferroelectricity gate dielectric layer is between 1.5nm~10nm；The thickness of first Metal gate layer is between 1nm~10nm
Between.
18. field-effect tube according to claim 13, wherein the ferroelectric material gate dielectric layer is doping Hf base oxidation
Object, one kind or combinations thereof including following material: HfZrO, HfZrAlO, HfAlO, HfSiO, HfLaO, HfSrO, HfGdO or
HfYO。
19. field-effect tube according to claim 18, wherein doping hafnium oxide base (HfO) the ferroelectric material gate medium
The ferroelectric properties power of layer is also closely related with the content of doped chemical therein, such as the optimization of Zr, Si, Y, Al, Gd, Sr and La
Percentage composition is respectively 30-60%, 3-6%, 4-6.5%, 3.5-6.5%, 1.5-5%, 8-12% and 3-6% than range.
20. field-effect tube according to claim 15, wherein the material of first Metal gate layer includes in following material
One kind or combinations thereof: Mo, Ti, W, TiN, TiC, TiAl, TiAlC, TaC, TaN, TaAlC, TaAl, TaCN, NbAlC,
TiMoN、MoN、WN、TiWN。
21. field-effect tube according to claim 15, wherein second Metal gate layer includes multiple layer metal material,
In against the first Metal gate layer the good metal of metal material selection oxygen absorption performance, comprising: at least one of Ti, TiAl, Ta；
Followed by potential barrier barrier metal, comprising: one or both of TiN, TaN, Ta, MoN, AlN or WN；It is finally filling gold
Belong to, comprising: W, Al, one of TiAl, TiAlC or Mo or a variety of.
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| US16/822,175 US11217694B2 (en) | 2019-03-18 | 2020-03-18 | Field-effect transistor and method for manufacturing the same |
| US17/371,142 US11694901B2 (en) | 2019-03-18 | 2021-07-09 | Field-effect transistor and method for manufacturing the same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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