CN108288642A - Tunneling field effect transistor and preparation method thereof - Google Patents
Tunneling field effect transistor and preparation method thereof Download PDFInfo
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- CN108288642A CN108288642A CN201711342142.6A CN201711342142A CN108288642A CN 108288642 A CN108288642 A CN 108288642A CN 201711342142 A CN201711342142 A CN 201711342142A CN 108288642 A CN108288642 A CN 108288642A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 230000005641 tunneling Effects 0.000 title claims abstract description 31
- 238000002353 field-effect transistor method Methods 0.000 title description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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Abstract
The invention provides a tunneling field effect transistor and a preparation method thereof. The preparation method comprises the following steps: s1, forming a first fin body isolated from the substrate on the substrate, wherein the first fin body consists of a first region, a second region and a third region which are sequentially connected along the length direction; s2, forming a nanowire structure in the second region of the first fin body; s3, sequentially forming a stacked interface oxide layer, a ferroelectric layer and a gate around the exposed surface of the nanowire structure, and the preparation method further comprises the steps of: and forming a source electrode in the first region, and forming a drain electrode in the third region, wherein the source electrode and the drain electrode are respectively connected with two ends of the nanowire structure, and the doping types of the source electrode and the drain electrode are opposite. The preparation method improves the grid control capability of the device, reduces the leakage current of the device, reduces the source-drain parasitic resistance of the device, can ensure that the subthreshold slope of the device is greatly lower than 60mV/dec, and has lower power consumption.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of tunneling field-effect transistor and its preparation side
Method.
Background technology
With the continuous atrophy of device, it is special that traditional fin FET (FinFET) faces the subthreshold value seriously degenerated
Property, the Punchthrough leakage current that sharply increases and gate medium tunneling leakage, improve driveability and reduce system power dissipation to work
Make electrical parameter statistic fluctuation caused by the conflicting requirements and process variation of voltage (Statistical Fluctuations)
Etc. various severe challenges.Therefore more steep sub-threshold slope means can to obtain lower threshold voltage and lower
Power consumption, and traditional MOSFET, due to the limitation of its physical characteristic, sub-threshold slope cannot be below 60mV/dec.
How lower sub-threshold slope is provided by optimised devices structure and manufacturing process and optimize grid-control, be still fin
Type field-effect transistor has to the technical barrier solved.
Invention content
The main purpose of the present invention is to provide a kind of tunneling field-effect transistors and preparation method thereof, to solve existing skill
The higher problem of the sub-threshold slope of fin FET in art.
To achieve the goals above, according to an aspect of the invention, there is provided a kind of system of tunneling field-effect transistor
Preparation Method includes the following steps：S1 forms the first fin body being isolated with substrate on substrate, and the first fin body is by along its length
First area, second area and third region composition connected in sequence；Second area in first fin body is formed nano wire by S2
Structure；S3 sequentially forms the interface oxide layer, ferroelectric layer and grid of stacking around the exposed surface of nano thread structure, and, it prepares
Method is further comprising the steps of：Form source electrode in the first region, in third region formed drain electrode, source electrode and drain electrode respectively with
The both ends of nano thread structure connect, and source electrode is opposite with the doping type of drain electrode.
Further, step S1 includes the following steps：S11, forms fin structure on substrate, and the both sides of fin structure have phase
To groove；S12 aoxidizes fin structure, and the position of the corresponding fin structure of further groove is fully oxidized so that fin structure is formed
Independent first fin body and the second fin body, the first fin body are located at the second side of the fin body far from substrate；S13 is deposited on substrate
Insulating materials, to form the first separation layer of covering the first fin body and the second fin body；S14 planarizes the first separation layer
Processing, so that the upper surface flush of the first separation layer and the first fin body.
Further, step S11 includes following procedure：S111, sequentially form on substrate the second separation layer, sacrificial layer and
Mask layer；S112 removes partial sacrificial layer and mask layer, so that the second insulation surface of part is exposed using patterning process；
S113 removes remaining mask layer, and forms the first side wall for being covered in sacrificial layer both sides on the second separation layer；S114 is gone
The second separation layer of part and section substrate are removed except remaining sacrificial layer, and by mask of the first side wall, it is corresponding with the first side wall
Section substrate convex to form fin structure, while the both sides of fin structure form fluted, and groove is prolonged by 1/3 height of fin structure
It extends at 2/3 height.
Further, the process for forming fin structure includes：The second separation layer of part is removed using anisotropic etch process
And section substrate, so that remaining substrate has bulge-structure；Using isotropic etching technique bulge-structure both sides shape
At groove；Section substrate below groove is located at using anisotropic etch process removal, has reeded fin structure to be formed.
Further, between step S1 and step S2, preparation method is further comprising the steps of：From the table of the first separation layer
Face starts etching removal the first separation layer of part, so that part the first fin body is exposed；On remaining first separation layer formed across
The false grid of part the first fin body stack, and form the second side wall across part the first fin body in the both sides that false grid stack；Removal is false
Grid stack, and part the first fin body between the second side wall is second area.
Further, between the step of forming the second side wall and the step of the false grid of removal stack, in the first region
Source electrode is formed, and forms drain electrode in third region.
Further, step S2 includes：Keep the second area in the first fin body completely exposed, under an atmosphere of hydrogen to second
Region is made annealing treatment, and part the first fin body is formed nano thread structure, and the preferably pressure of atmosphere of hydrogen is 10~50mT,
The temperature of annealing is 650~950 DEG C, and the time is 10~300s；Or make second area partial oxidation in the first fin body, with
Second area is formed into nano thread structure and wraps up the oxide layer of nano thread structure, removes removing oxide layer so that nano thread structure is naked
Dew, it is preferred to use wet-etching technology removes removing oxide layer, and the corrosive agent of wet-etching technology includes DHF.
Further, in step s3, the exposed surface using ozone treatment around nano thread structure forms interface oxide layer.
Further, in step s3, the exposed surface using atom layer deposition process around interface oxide layer forms ferroelectricity
Layer.
Further, the material for forming ferroelectric layer includes HfZrO and/or HfSiO.
Further, between the step of forming ferroelectric layer and grid, step S3 is further comprising the steps of：Around ferroelectric layer
Periphery forms work-function layer.
Further, the exposed surface using atom layer deposition process around ferroelectric layer forms work-function layer.
Further, substrate is n-type doping, and the energy gap of work-function layer is 4.1~4.4eV, is preferably formed as work-function layer
Material is TiAl；Or substrate adulterates for p-type, the energy gap of work-function layer is 4.7~4.9eV, is preferably formed as the material of work-function layer
For TiN.
Further, after the step of forming grid, source electrode is formed in the first region, and formed in third region
Drain electrode.
According to another aspect of the present invention, a kind of tunneling field-effect transistor is provided, including：Substrate；First fin body, position
In on substrate, the first fin body is made of first area connected in sequence along its length, second area and third region, and second
Region is nano thread structure；First separation layer is set between substrate and the first fin body, for by the first fin body and substrate every
From；Interface oxide layer, around nano thread structure；Ferroelectric layer, around interface oxide layer；Grid, around ferroelectric layer；Source electrode is located at
In first area, and one end of source electrode and nano thread structure connects；And drain electrode, it is located in third region, and drain and second
The other end in region connects, and source electrode is opposite with the doping type of drain electrode.
Further, tunneling field-effect transistor further includes the work-function layer for surrounding ferroelectric layer, and work-function layer is set to iron
Between electric layer and grid.
Further, tunneling field-effect transistor further includes covering grid both sides and across the second side wall of the first fin body.
It applies the technical scheme of the present invention, provides a kind of preparation method of tunneling field-effect transistor, the preparation method
In in the first fin body for being isolated with substrate of formation, and the first fin body is by first area connected in sequence along its length, the secondth area
Behind domain and third region composition, the second area of the first fin body is formed into nano thread structure, and around nano thread structure sequence
Interface oxide layer, ferroelectric layer and grid are formed, since nano thread structure for forming trenches is wrapped up at grid four sides, to make to carry
The high grid-control ability of device, turns off, the carrier in raceway groove will be completely depleted, this makes source and drain wear in device
Logical leakage current is inhibited well；It is kept completely separate with substrate since the first fin body obtained in above-mentioned preparation method is whole, every
Substrate direction leakage path absolutely, to reducing the leakage current of device；Due to only by the part as raceway groove in fin structure
Nano wire is formed on the one hand to efficiently avoid short-channel effect to make source/drain be able to maintain that original form, optimize
Sub-Threshold Characteristic, while enabling the device to that there is lower dead resistance；Also, the material due to forming above-mentioned ferroelectric layer is negative
Capacitance material, has a polarization characteristic, and the reversed PN junction tunnel mechanism of the devices use gate control, switching speed faster, so as to
The sub-threshold slope of device is enough set to be significantly less than 60mV/dec, power consumption is lower.
Description of the drawings
The Figure of description for constituting the part of the present invention is used to provide further understanding of the present invention, and of the invention shows
Meaning property embodiment and its explanation are not constituted improper limitations of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is shown in the preparation method for the tunneling field-effect transistor that the application embodiment is provided, in substrate
On sequentially form the matrix cross-sectional view after the second separation layer, sacrificial layer and mask layer；
Fig. 2 shows removal partial sacrificial layer shown in FIG. 1 and mask layers, so that after the second insulation surface of part is exposed
Matrix cross-sectional view；
Fig. 3 shows removal remaining mask layer shown in Fig. 2, and is formed on the second separation layer and be covered in sacrificial layer two
Matrix cross-sectional view after first side wall of side；
Fig. 4 shows the matrix cross-sectional view after removing sacrificial layer shown in Fig. 3；
Fig. 5 shows the matrix cross-sectional view for being formed in matrix shown in Fig. 4 and having reeded fin structure；
Fig. 6, which is shown, aoxidizes fin structure shown in fig. 5, so that fin structure forms independent first fin body and the second fin body
Matrix cross-sectional view afterwards；
Fig. 7 shows the first separation layer to be formed and cover the first fin body and the second fin body shown in fig. 6, and makes part first
Matrix cross-sectional view after fin body is exposed；
Fig. 8 shows the matrix perspective view after forming the second side wall in matrix shown in Fig. 7；
Fig. 9 show make the second area in the first fin body shown in Fig. 7 completely it is exposed after matrix cross-section structure
Schematic diagram；
Figure 10 shows the matrix cross-section structure signal after the first fin of part body shown in Fig. 9 to be formed to nano thread structure
Figure；
Figure 11, which is shown, aoxidizes second area shown in Fig. 9 to form the matrix section after nano thread structure and oxide layer
Structural schematic diagram；
Figure 12 is shown oxide layer removal shown in Figure 11 so that the matrix cross-section structure after nano thread structure is exposed shows
It is intended to；
Figure 13 shows the matrix section that the exposed surface around nano thread structure shown in Figure 12 is formed after interface oxide layer
Structural schematic diagram；
Figure 14 shows the matrix cross-section structure that the exposed surface around interface oxide layer shown in Figure 13 is formed after ferroelectric layer
Schematic diagram；
Figure 15 shows that the matrix cross-section structure after the exposed surface formation work-function layer of ferroelectric layer shown in Figure 14 shows
It is intended to；
Figure 16 shows the matrix cross-section structure signal after the exposed surface formation grid of work-function layer shown in figure 15
Figure；
Figure 17 shows a kind of perspective views for tunneling field-effect transistor that embodiment of the present invention is provided；And
Figure 18 shows tunneling field-effect transistor median surface oxide layer, ferroelectric layer, work-function layer and grid shown in Figure 17
Cross-sectional view of the pole sequence around nano thread structure.
Wherein, above-mentioned attached drawing includes the following drawings label：
10, substrate；110, fin structure；111, the first fin body；112, the second fin body；113, oxide layer；120, nanowire-junction
Structure；210, the second separation layer；220, sacrificial layer；230, mask layer；240, the first side wall；250, the second side wall；30, the first isolation
Layer；410, source electrode；420, it drains；50, interface oxide layer；60, ferroelectric layer；70, work-function layer；80, grid.
Specific implementation mode
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
It should be noted that term " first " in description and claims of this specification and above-mentioned attached drawing, "
Two " etc. be for distinguishing similar object, without being used to describe specific sequence or precedence.It should be appreciated that using in this way
Data can be interchanged in the appropriate case, so as to the embodiment of the present invention described herein.In addition, term " comprising " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing series of steps or unit
Process, method, system, product or equipment those of are not necessarily limited to clearly to list step or unit, but may include without clear
It is listing to Chu or for these processes, method, product or equipment intrinsic other steps or unit.
As described in background technology, how the prior art is provided more by optimised devices structure and manufacturing process
Low sub-threshold slope simultaneously optimizes grid-control, is still that fin FET has to the technical barrier solved.The hair of the present invention
A person of good sense studies regarding to the issue above, it is proposed that a kind of preparation method of tunneling field-effect transistor includes the following steps：
S1 forms the first fin body 111 being isolated with substrate 10 on substrate 10, and the first fin body 111 is by connected in sequence along its length
First area, second area and third region composition, above-mentioned length direction refers to the extending direction of the first fin body 111；S2, by
Second area in one fin body 111 forms nano thread structure 120；S3, the exposed surface around nano thread structure 120 sequentially form layer
Folded interface oxide layer, ferroelectric layer and grid, and, preparation method is further comprising the steps of：Source electrode is formed in the first region
410, drain electrode 420 is formed in third region, source electrode 410 and drain electrode 420 are connect with the both ends of nano thread structure 120 respectively, and
Source electrode 410 is opposite with the doping type of drain electrode 420.
Due to forming the first fin body being isolated with substrate, and first in the preparation method of above-mentioned tunneling field-effect transistor
After fin body is made of first area connected in sequence along its length, second area and third region, by the second of the first fin body
Region forms nano thread structure, and sequentially forms interface oxide layer, ferroelectric layer and grid around the nano thread structure, due to grid
Nano thread structure for forming trenches is wrapped up at four sides, to make the grid-control ability for improving device, is turned off in device,
Carrier in raceway groove will be completely depleted, this so that Punchthrough leakage current is inhibited well；Due to above-mentioned preparation
The the first fin body obtained in method is integrally kept completely separate with substrate, has completely cut off substrate direction leakage path, to reduce device
Leakage current；Since only nano wire will be formed as the part of raceway groove in fin structure, to make source/drain be able to maintain that originally
On the one hand shape efficiently avoids short-channel effect, optimize Sub-Threshold Characteristic, while enabling the device to have lower post
Raw resistance；Also, the material due to forming above-mentioned ferroelectric layer is negative electricity capacity materials, has polarization characteristic, and the devices use grid
Control reversed PN junction tunnel mechanism, switching speed faster, so as to make the sub-threshold slope of device be significantly less than 60mV/dec,
Power consumption is lower.
It is described in more detail below according to the exemplary of the preparation method of tunneling field-effect transistor provided by the invention
Embodiment.However, these illustrative embodiments can be implemented by many different forms, and it is not construed as
It is only limited to embodiments set forth herein.It should be understood that thesing embodiments are provided so that the public affairs of the application
It opens thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art.
First, step S1 is executed：Form the first fin body 111 for being isolated with substrate 10 on substrate 10, the first fin body 111 by
First area connected in sequence, second area and third region composition along its length, as shown in Fig. 1 to 7.Above-mentioned substrate 10 can
Semiconductor substrate conventional in the prior art is thought, such as Si substrates, Ge substrates, SiGe substrate, SOI (silicon-on-insulator) or GOI
(germanium on insulator) etc..
Above-mentioned the first fin body 111 being isolated with substrate 10 in order to obtain, in a preferred embodiment, above-mentioned steps
S1 includes the following steps：S11, forms fin structure 110 on substrate 10, and the both sides of fin structure 110 have opposite groove, such as scheme
Shown in 1 to 5；S12 aoxidizes fin structure 110, and the position of the corresponding fin structure of further groove 110 is fully oxidized so that fin knot
Structure 110 forms independent first fin body 111 and the second fin body 112, and the first fin body 111 is located at the second fin body 112 far from substrate 10
Side, as shown in Figure 6；S13, the deposition of insulative material on substrate 10, to form the first fin body 111 of covering and the second fin body
112 the first separation layer 30；S14 carries out planarization process, so that the first separation layer 30 and the first fin body to the first separation layer 30
111 upper surface flush.
In above-mentioned steps S11, process conventional in the prior art may be used and form above-mentioned fin structure 110,
In a kind of preferred embodiment, above-mentioned steps S11 includes following procedure：S111 sequentially forms the second isolation on substrate 10
Layer 210, sacrificial layer 220 and mask layer 230, as shown in Figure 1；S112 using patterning process removal partial sacrificial layer 220 and is covered
Film layer 230, so that 210 surface exposure of the second separation layer of part, as shown in Figure 2；S113, removes remaining mask layer 230, and
The first side wall 240 for being covered in 220 both sides of sacrificial layer is formed on second separation layer 210, as shown in Figure 3；S114, removal are remaining
Sacrificial layer 220, and be that mask removes the second separation layer of part 210 and section substrate 10 with the first side wall 240, with the first side wall
240 corresponding section substrates 10 convex to form fin structure 110, while the both sides of fin structure 110 are formed with opposite groove, groove
It is extended at 2/3 height by 1/3 height of fin structure 110, as shown in Figure 4 and Figure 5.
In above process S111, MOCVD, PECVD etc. may be used, and conventional deposition method is formed in the prior art
The second separation layer 210, sacrificial layer 220 and mask layer 230 are stated, those skilled in the art can be according to actual demand to above-mentioned deposition
The process conditions of method carry out reasonable set；Also, those skilled in the art can be according to the prior art to above-mentioned formation second
The material of separation layer 210, sacrificial layer 220 and mask layer 230 carries out Rational choice, the material of the second separation layer of above-mentioned formation 210
Can be oxide, the material of such as silica, above-mentioned formation sacrificial layer 220 can be non-crystalline silicon (α-Si), above-mentioned formation mask
The material of layer 230 can be Si3N4。
In above process S112, patterning process may include：Photoresist is coated on 230 surface of mask layer, is then existed
Mask plate is set above photoresist, photoetching window is obtained after removing part photoresist by exposure imaging, remaining photoresist
Length and the length of required mask layer 230 are of substantially equal, are removed finally by photoetching opening etch and are not photo-etched glue on substrate 10
The part mask layer 230 and partial sacrificial layer 220 of covering, so that 210 surface exposure of the second separation layer of part, wherein above-mentioned
Two separation layers 210 are for preventing substrate to be partially etched in patterning process.
In above process S113, those skilled in the art can be according to the prior art to the first side wall of above-mentioned formation 240
Material carry out Rational choice, the material for forming above-mentioned first side wall 240 can be Si3N4。
In above process S114, those skilled in the art can be according to the prior art to the remaining sacrificial layer of above-mentioned removal
220 technique carries out Rational choice, it is preferable that removes above-mentioned sacrificial layer 220 using selective etch technology, above-mentioned selectivity is carved
Erosion can be dry etching or wet etching, by being adjusted to technological parameter so that etching gas or etching solution are to sacrificing
Layer 220 and the first side wall 240 have different etch rates, are optionally removed to sacrificial layer 220 so as to realize.
In above process S114, has reeded fin structure 110 to be effectively formed both sides, it is preferable that adopt simultaneously
With anisotropic etch process and isotropic etching technique groove is formed in the both sides of fin structure 110.Specifically, the fin is formed
The process of structure 110 may include：The second separation layer of part 210 and section substrate 10 are removed using anisotropic etch process,
So that remaining substrate 10 has bulge-structure；Groove is formed in the both sides of bulge-structure using isotropic etching technique；It adopts
It is located at the section substrate 10 below groove with anisotropic etch process removal, has reeded fin structure 110 to be formed.
It is further preferable that the etching gas of above-mentioned anisotropic etch process includes HBr, Cl2、O2With inert gas such as N2、
The mixed gas of Ar etc. or above-mentioned arbitrary gas, process conditions are：Etching temperature be 20~90 DEG C, etching power be 4~
300W, etch period are 30~500s；The etching gas of above-mentioned isotropic etching technique includes SF6、CF4、Ch2F2And inertia
Gas such as N2, Ar etc. or above-mentioned arbitrary gas mixed gas, process conditions are：Etching power is 4~300W, etch period
For 30~500s.
In above process S12, in order to enable the position of fin structure corresponding with groove 110 to be fully oxidized, preferably
Ground, the process conditions that fin structure 110 is aoxidized are rapid thermal oxidation (RTP), or are passed through oxygen or oxygen and hydrogen using boiler tube
The mixed gas of gas, and heat 30s~10h.
Above process S13 and process S14 can be shallow-trench isolation (STI) technique of routine in the prior art, this field skill
Art personnel can carry out Rational choice according to the prior art to the insulating materials that is deposited in the STI techniques, which can be with
For SiO2；Also, those skilled in the art can be according to actual demand to depositing operation and planarization process in above-mentioned STI techniques
Process conditions carry out reasonable set.
Preceding grid technique, which may be used, in the above-mentioned preparation method of the present invention can also use rear grid technique, at this time nano thread structure
Can be formed in preceding grid technique can also form in rear grid technique, in order to avoid front gate process high-temperature technique is to gate dielectric
Influence, present invention preferably employs rear grid techniques.At this point, after step S1, above-mentioned preparation method of the invention can also wrap
Include following steps：Etching removal the first separation layer of part 30 since the surface of the first separation layer 30, so that part the first fin body
111 is exposed, as shown in Figure 7；The false grid formed on remaining first separation layer 30 across part the first fin body 111 stack, and
The both sides that false grid stack form the second side wall across part the first fin body 111；The false grid of removal stack, between the second side wall
Part the first fin body 111 is second area, obtains structure as shown in Figure 8.
In above-mentioned steps, false grid stacking may include the first gate dielectric layer and false grid, in order to preferably control the first grid
The thickness of dielectric layer, it is preferable that above-mentioned first gate dielectric layer is formed using atom layer deposition process (ALD)；Also, it is formed above-mentioned
The material of first gate dielectric layer may include SiO2、HfO2、La2O3、Al2O3、TiO2Any one or more of, above-mentioned vacation grid material
Material can be non-crystalline silicon, the material and vacation that those skilled in the art can be according to the prior art to above-mentioned first gate dielectric layer of formation
The type of grid material carries out Rational choice.
Also, when using rear grid technique, between the step of the step of forming the second side wall and the false grid of removal stack,
Source electrode 410 is formed in the first region, and drain electrode 420 is formed in third region.At this point, making above-mentioned source electrode 410 and drain electrode 420
It is connect respectively with the both ends of the nano thread structure 120 formed in step S2, as shown in Figure 8.Form above-mentioned source electrode 410 and drain electrode
420 technique can be doping in situ, and those skilled in the art can be according to the prior art to the above-mentioned technique item adulterated in situ
Part carries out reasonable set.
After having executed above-mentioned steps S1, step S2 is executed：Second area in first fin body 111 is formed into nano wire
Structure 120.At this time preferably, by being used as substrate 10 using monocrystalline substrate in step sl, above-mentioned nanowire-junction can be made
Structure 120 is single crystal silicon material makes raceway groove be improved for single crystal silicon material since raceway groove is formed in above-mentioned nano thread structure 120
The mobility of device carrier.
In order to which the second area in the first fin body 111 is formed nano thread structure 120, in a kind of preferred embodiment
In, above-mentioned steps S2 includes：Keep the second area in the first fin body 111 completely exposed, under an atmosphere of hydrogen to second area into
Part the first fin body 111 is formed nano thread structure 120, as shown in Figure 9 and Figure 10 by row annealing.Under an atmosphere of hydrogen
It is made annealing treatment, can make silicon face that atom reconstruct occur in the case where depressurizing hot environment, thus by 111 rib of part the first fin body
Si atoms at angle are moved to the lower position of energy, to form nano thread structure 120.Above-mentioned nanowire-junction is formed in order to improve
The efficiency of structure 120, it is preferable that the pressure of above-mentioned atmosphere of hydrogen is 10~50mT, and the temperature of annealing is 650~950 DEG C, when
Between be 10~300s.
In another preferred embodiment, above-mentioned steps S2 includes：Make the second area part in the first fin body 111
Second area is formed nano thread structure 120 and wraps up the oxide layer 113 of nano thread structure 120, removes removing oxide layer by oxidation
113 so that nano thread structure 120 is exposed, as is illustrated by figs. 11 and 12.Second area in first fin body 111 is opened from outer surface
Oxidation begin to form oxide layer, not oxidized part constitutes the nano thread structure 120 of drops in second area.In order to improve
Form the efficiency of above-mentioned nano thread structure 120, it is preferable that rapid thermal oxidation (RTP) may be used, can also use pure oxygen or
Oxygen and hydrogen gas mixture aoxidize the part of second area；And, it is preferable that using in wet-etching technology removal
Oxide layer 113 is stated, the corrosive agent of above-mentioned wet-etching technology may include DHF.
When being formed across above-mentioned second side wall 250 of the first fin body 111 of part between above-mentioned steps S1 and step S2,
In above-mentioned steps S2, it is preferable that etching removes first between the second side wall 250 since the surface of the first separation layer 30
Separation layer 30, so that the second area in the first fin body 111 is completely exposed, as shown in figure 9, then by right under an atmosphere of hydrogen
The second area is made annealing treatment, or by aoxidizing the second area in the first fin body 111 since outer surface, and is removed
Part the first fin body 111 is formed nano thread structure 120 by the oxide layer 113 on surface, and source/drain is located at nanowire-junction at this time
The both sides of structure 120, obtained structure are as shown in figure 12；It is further preferable that removing part above-mentioned first using wet-etching technology
Separation layer 30, the corrosive agent used in wet-etching technology can be DHF.
After having executed above-mentioned steps S2, step S3 is executed：Exposed surface around nano thread structure 120 sequentially forms layer
Folded interface oxide layer 50, ferroelectric layer 60 and grid 80, as shown in figure 13 to figure 16.It is negative due to forming above-mentioned ferroelectric layer 60
Capacitance material has polarization characteristic, so as to make the sub-threshold slope of device be significantly less than 60mV/dec；Also, due to upper
Stating grid 80 can be wrapped in nanowire channel entirely, and grid-control ability is most strong, be turned off in device, the carrier in raceway groove
It will be completely depleted, this so that Punchthrough leakage current is inhibited well.
In above-mentioned steps S3, in order to more effectively form above-mentioned interface oxide layer 50, it is preferable that use ozone treatment
Exposed surface around nano thread structure 120 forms interface oxide layer 50, and obtained structure is as shown in figure 13；Also, in order to more
It is effectively formed above-mentioned ferroelectric layer 60, it is preferable that using atom layer deposition process (ALD) around the exposed surface of interface oxide layer 50
Ferroelectric layer 60 is formed, obtained structure is as shown in figure 14.Those skilled in the art can according to the prior art to above-mentioned ozone at
The process conditions of reason and atomic layer deposition carry out Rational choice.
In above-mentioned steps S3, in order to ensure the polarization characteristic of above-mentioned ferroelectric layer 60, so as to make the subthreshold value of device
Slope is significantly less than 60mV/dec, it is preferable that the ferroelectric material for forming ferroelectric layer 60 includes HfZrO and/or HfSiO.But not
It is confined to above-mentioned preferred type, those skilled in the art can carry out rationally according to the prior art to forming above-mentioned ferroelectric material
It chooses.
In above-mentioned steps S3, formed grid 80 metal gate material can be TaC, TiN, TaTbN, TaErN, TaYbN,
TaSiN、HfSiN、MoSiN、RuTax、NiTax, MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、
Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu and RuOxAny one or more of, those skilled in the art can bases
The prior art carries out Rational choice to the type of above-mentioned metal gate material.
In a preferred embodiment, between the step of forming ferroelectric layer 60 and grid 80, step S3 further includes
Following steps：Work-function layer 70 is formed around the periphery of ferroelectric layer 60, obtained structure is as shown in figure 15, at this time 80 ring of above-mentioned grid
It is arranged around the surface of above-mentioned work-function layer 70.Threshold voltage of the above-mentioned work-function layer 70 for device adjusts, and meets high-performance device
The requirement of part and low energy-consumption electronic device.
In order to more effectively form above-mentioned work-function layer 70, it is preferable that using atom layer deposition process around ferroelectric layer 60
Exposed surface formed work-function layer 70.Also, it is excellent in order to make above-mentioned work-function layer 70 realize effective adjustment to cut-in voltage
Selection of land, when substrate 10 is n-type doping, the energy gap of above-mentioned work-function layer 70 is 4.1~4.4eV, is preferably formed as work-function layer 70
Material be TiAl；When substrate 10 adulterates for p-type, the energy gap of above-mentioned work-function layer 70 is 4.7~4.9eV, is preferably formed as work content
Several layers 70 of material is TiN.
Also, when using preceding grid technique, after the step of forming grid 80, the in above-mentioned first fin body 111
Source electrode 410 is formed in one region, and drain electrode 420 is formed in the third region in above-mentioned first fin body 111.At this point, making source/drain
Pole is connect with the both ends of the nano thread structure 120 formed in step S3.The technique for forming above-mentioned source/drain can be in situ mix
Miscellaneous, those skilled in the art can carry out reasonable set according to the prior art to the above-mentioned process conditions adulterated in situ.
According to another aspect of the present invention, a kind of tunneling field-effect transistor is provided, as shown in Figure 17 and Figure 18, packet
It includes：Substrate 10；First fin body 111, be located at substrate 10 on, the first fin body 111 by first area connected in sequence along its length,
Second area and third region composition, and second area is nano thread structure 120；First separation layer 30, be set to substrate 10 with
Between first fin body 111, for the first fin body 111 to be isolated with substrate 10；Interface oxide layer 50, around nano thread structure 120；
Ferroelectric layer 60, around interface oxide layer 50；Grid 80, around ferroelectric layer 60；Source electrode 410 is located in first area, and source electrode
410 connect with one end of nano thread structure 120；And drain electrode 420, it is located in third region, and drain electrode 420 and second area
The other end connects, and source electrode 410 is opposite with the doping type of drain electrode 420.
The grid 80 in above-mentioned tunneling field-effect transistor, interface oxide layer 50, ferroelectric layer and 60 and are not shown in Figure 17
80 sequence of grid is as shown in figure 18 around the cross-sectional view of nano thread structure.
Since nano wire for forming trenches is wrapped up at grid four sides in the above-mentioned tunneling field-effect transistor of the present invention
Structure turns off, the carrier in raceway groove will be consumed completely to make the grid-control ability for improving device in device
To the greatest extent, this so that Punchthrough leakage current is inhibited well；It is kept completely separate, completely cuts off with substrate since above-mentioned first fin body is whole
Substrate direction leakage path, to reducing the leakage current of device；Due to only by the part shape as raceway groove in fin structure
Short-channel effect is on the one hand efficiently avoided, Asia is optimized to make source/drain be able to maintain that original form at nano wire
Threshold property, while enabling the device to that there is lower dead resistance；Also, the material due to forming above-mentioned ferroelectric layer is negative electricity
Capacity materials have polarization characteristic, so as to make the sub-threshold slope of device be significantly less than 60mV/dec.
The above-mentioned tunneling field-effect transistor of the present invention can be prepared by above-mentioned preparation method, and tunneling field-effect is brilliant
Body pipe further includes covering 80 both sides of grid and the second side wall 250 across the first fin body 111, second side wall 250 can play grid
The effect of pole 80 and source/drain isolation.
In the above-mentioned tunneling field-effect transistor of the present invention, it is preferable that the tunneling field-effect transistor further includes work content
Several layers 70, work-function layer 70 is set between ferroelectric layer 60 and grid 80, as shown in figure 18.Above-mentioned work-function layer 70 is used for device
Threshold voltage adjustment, meet the requirement of high performance device and low energy-consumption electronic device.
It can be seen from the above description that the above embodiments of the present invention realize following technique effect：
1, since nano thread structure for forming trenches is wrapped up at the grid four sides in grid stacked structure, to make to improve
The grid-control ability of device is turned off in device, and the carrier in raceway groove will be completely depleted, this makes Punchthrough leak
Electric current is inhibited well；
2, it is kept completely separate with substrate since the first fin body obtained in above-mentioned preparation method is whole, has completely cut off the leakage of substrate direction
Electric pathway, to reduce the leakage current of device；
3, since only nano wire will be formed as the part of raceway groove in fin structure, to make source/drain be able to maintain that original
Carry out shape, on the one hand efficiently avoid short-channel effect, optimize Sub-Threshold Characteristic, while enabling the device to have lower
Dead resistance；
4, since the material for forming above-mentioned ferroelectric layer is negative electricity capacity materials, there is polarization characteristic, and the devices use grid-control
Make reversed PN junction tunnel mechanism, switching speed faster, so as to make the sub-threshold slope of device be significantly less than 60mV/dec, work(
Consumption is lower；
5, tunneling field-effect transistor further includes work-function layer, and threshold voltage of the above-mentioned work-function layer for device adjusts,
Meet the requirement of high performance device and low energy-consumption electronic device.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (17)
1. a kind of preparation method of tunneling field-effect transistor, which is characterized in that include the following steps：
S1, forms the first fin body (111) for being isolated with the substrate (10) on substrate (10), the first fin body (111) by
First area connected in sequence, second area and third region composition along its length；
The second area in the first fin body (111) is formed nano thread structure (120) by S2；
S3 sequentially forms interface oxide layer (50), the ferroelectric layer (60) of stacking around the exposed surface of the nano thread structure (120)
With grid (80),
And the preparation method is further comprising the steps of：
Source electrode (410) is formed in the first area, and drain electrode (420), the source electrode (410) are formed in the third region
It is connect respectively with the both ends of the nano thread structure (120) with the drain electrode (420), and the source electrode (410) and the drain electrode
(420) doping type is opposite.
2. preparation method according to claim 1, which is characterized in that the step S1 includes the following steps：
S11, forms fin structure (110) on substrate (10), and the both sides of the fin structure (110) have opposite groove；
S12 aoxidizes the fin structure (110), wherein the position of the corresponding fin structure (110) of the groove is by complete oxygen
Change so that the fin structure (110) forms the independent first fin body (111) and the second fin body (112), the first fin body
(111) it is located at side of the second fin body (112) far from the substrate (10)；
S13, the deposition of insulative material on the substrate (10) cover the first fin body (111) and second fin to be formed
The first separation layer (30) of body (112)；
S14 carries out planarization process to first separation layer (30), so that first separation layer (30) and first fin
The upper surface flush of body (111).
3. preparation method according to claim 2, which is characterized in that the step S11 includes following procedure：
S111 sequentially forms the second separation layer (210), sacrificial layer (220) and mask layer (230) on the substrate (10)；
S112, using the patterning process removal part sacrificial layer (220) and the mask layer (230), so that described in part
Second separation layer (210) surface exposure；
S113 removes the remaining mask layer (230), and formed on second separation layer (210) be covered in it is described sacrificial
First side wall (240) of domestic animal layer (220) both sides；
S114, removes the remaining sacrificial layer (220), and is that mask removes part described the with first side wall (240)
Two separation layers (210) and the part substrate (10), part corresponding with the first side wall (240) substrate (10) protrusion
The fin structure (110) is formed, while the both sides of the fin structure (110) are formed with the groove, the groove is by the fin
It is extended at 1/3 height of structure (110) at 2/3 height.
4. preparation method according to claim 3, which is characterized in that the process for forming the fin structure (110) includes：
Using anisotropic etch process removal part second separation layer (210) and the part substrate (10), so that surplus
The remaining substrate (10) has bulge-structure；
The groove is formed in the both sides of the bulge-structure using isotropic etching technique；
The part substrate (10) below the groove is located at using anisotropic etch process removal, to be formed with described
The fin structure (110) of groove.
5. preparation method according to claim 2, which is characterized in that between the step S1 and the step S2, institute
It is further comprising the steps of to state preparation method：
Etching removal part first separation layer (30) since the surface of first separation layer (30), so that described in part
First fin body (111) is exposed；
The false grid formed on remaining first separation layer (30) across part the first fin body (111) stack, and in institute
State second side wall of the both sides formation across part the first fin body (111) of false grid stacking；
It removes the false grid to stack, part the first fin body (111) between second side wall is secondth area
Domain.
6. preparation method according to claim 5, which is characterized in that in the step of forming second side wall and removal
Between the step of vacation grid stack, the source electrode (410), and the shape in the third region are formed in the first area
At the drain electrode (420).
7. preparation method according to claim 1, which is characterized in that the step S2 includes：
Keep the second area in the first fin body (111) completely exposed, under an atmosphere of hydrogen to the second area into
Part the first fin body (111) is formed nano thread structure (120), the pressure of the preferably described atmosphere of hydrogen by row annealing
It is 10~50mT by force, the temperature of the annealing is 650~950 DEG C, and the time is 10~300s；Or
Make the second area partial oxidation in the first fin body (111), the second area is formed into nanowire-junction
The oxide layer (113) of structure (120) and the package nano thread structure (120), removes the oxide layer (113) so that described receive
Nanowire structure (120) is exposed, it is preferred to use wet-etching technology removes the oxide layer (113), the wet-etching technology
Corrosive agent includes DHF.
8. preparation method according to claim 1, which is characterized in that in the step S3, using ozone treatment around institute
The exposed surface for stating nano thread structure (120) forms the interface oxide layer (50).
9. preparation method according to claim 1, which is characterized in that in the step S3, using atomic layer deposition work
Skill forms the ferroelectric layer (60) around the exposed surface of the interface oxide layer (50).
10. preparation method according to claim 1, which is characterized in that the material for forming the ferroelectric layer (60) includes
HfZrO and/or HfSiO.
11. preparation method according to claim 1, which is characterized in that forming the ferroelectric layer (60) and the grid
(80) between the step of, the step S3 is further comprising the steps of：
Work-function layer (70) is formed around the periphery of the ferroelectric layer (60).
12. preparation method according to claim 11, which is characterized in that using atom layer deposition process around the ferroelectric layer
(60) exposed surface forms the work-function layer (70).
13. preparation method according to claim 11, which is characterized in that
The substrate (10) is n-type doping, and the energy gap of the work-function layer (70) is 4.1~4.4eV, is preferably formed as the work content
The material of several layers (70) is TiAl；Or
The substrate (10) is adulterated for p-type, and the energy gap of the work-function layer (70) is 4.7~4.9eV, is preferably formed as the work content
The material of several layers (70) is TiN.
14. preparation method according to claim 1, which is characterized in that after the step of forming grid (80),
The source electrode (410) is formed in the first area, and the drain electrode (420) is formed in the third region.
15. a kind of tunneling field-effect transistor, which is characterized in that including：
Substrate (10)；
First fin body (111) is located on the substrate (10), and the first fin body (111) is by connected in sequence along its length
First area, second area and third region composition, and the second area is nano thread structure (120)；
First separation layer (30) is set between the substrate (10) and the first fin body (111), is used for first fin
Body (111) is isolated with the substrate (10)；
Interface oxide layer (50), around the nano thread structure (120)；
Ferroelectric layer (60), around the interface oxide layer (50)；
Grid (80), around the ferroelectric layer (60)；
Source electrode (410) is located in the first area, and the source electrode (410) and one end of the nano thread structure (120) connect
It connects；And
It drains (420), is located in the third region, and the drain electrode (420) connect with the other end of the second area, and
The source electrode (410) is opposite with the drain electrode doping type of (420).
16. tunneling field-effect transistor according to claim 15, which is characterized in that the tunneling field-effect transistor is also
Include the work-function layer (70) around the ferroelectric layer (60), the work-function layer (70) is set to the ferroelectric layer (60) and institute
It states between grid (80).
17. tunneling field-effect transistor according to claim 15, which is characterized in that the tunneling field-effect transistor is also
Including covering grid (80) both sides and across the second side wall (250) of the first fin body (111).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711342142.6A CN108288642A (en) | 2017-12-14 | 2017-12-14 | Tunneling field effect transistor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN109616519A (en) * | 2018-12-06 | 2019-04-12 | 贵阳学院 | One kind zero subthreshold amplitude of oscillation, zero ionization by collision transistor device and manufacturing method |
| CN109904219A (en) * | 2019-03-18 | 2019-06-18 | 上海新微技术研发中心有限公司 | Manufacturing method of field effect transistor and field effect transistor |
| CN111704101A (en) * | 2020-05-13 | 2020-09-25 | 中国科学院微电子研究所 | Flexible sensor and preparation method thereof |
| US20210273081A1 (en) * | 2018-08-17 | 2021-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device |
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| US20210273081A1 (en) * | 2018-08-17 | 2021-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device |
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