CN107492487A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN107492487A CN107492487A CN201610420475.5A CN201610420475A CN107492487A CN 107492487 A CN107492487 A CN 107492487A CN 201610420475 A CN201610420475 A CN 201610420475A CN 107492487 A CN107492487 A CN 107492487A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
A kind of forming method of semiconductor devices, including：Substrate is provided, formed with grid structure in the substrate；Pre-amorphous processing is carried out to the substrate of the grid structure both sides, amorphous area is formed in the substrate of the grid structure both sides；Source and drain doping area is formed in the substrate of the grid structure both sides；Stress cap is formed on the amorphous area, the stress cap and amorphous area are made annealing treatment, the annealing is suitable to make the amorphous area form dislocation during recrystallizing, and the dislocation is suitable to provide tension to the channel region below the grid structure.The present invention improves the tension size for acting on channel region, so as to improve the carrier mobility of channel region, improves the electric property of semiconductor devices.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor devices.
Background technology
In semiconductor devices especially MOS device, improving a kind of main method of the switching frequency of field-effect transistor is
Driving current is improved, and the main path for improving driving current is to improve carrier mobility.
In existing semiconductor device fabrication process, because stress can change the energy gap and carrier mobility of silicon materials,
Therefore the means that the performance of semiconductor devices turns into more and more conventional are improved by stress.Specifically, should by suitable control
Power, carrier (electronics in nmos device, the hole in PMOS device) mobility can be improved, and then improve driving current,
The performance of semiconductor devices is greatly enhanced with this.Stable stress is formed in channel region by scene effect transistor, is improved
Carrier mobility in channel region.In general, tensile stress (tensile stress) can arrange the molecule in channel region
Cloth is more loose, so as to improve electron mobility, suitable for nmos device；Compression stress (comprehensive tress) can
So that the molecular arrangement in channel region is even closer, hole mobility is favorably improved, suitable for PMOS device.
Improving the mode of the carrier mobility of field-effect transistor at present mainly includes two kinds：One kind is using embedded
Germanium silicon technology and embedded carbon silicon technology improve the mobility of channel region, and lattice mismatch is formed between embedded germanium silicon material and silicon
Compression, to improve the performance of PMOS device；Lattice mismatch forms tension between embedded carbon silicon materials and silicon, to improve
The performance of nmos device.Another kind be strain memory technique (SMT, Stress Memorization Technique), by
The channel region of field-effect transistor forms stable stress, improves the carrier mobility in channel region, the stress memory technique
Specifically include and use annealing process so that the grid knot of stress cap (ACL, Activation Capping Layer) bottom
Structure recrystallizes so that the stress memory that stress cap is induced is in MOS device so that the electrical property of MOS device improves.
However, the performance for the semiconductor devices that prior art is formed using SMT technologies still needs further to be improved.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of forming method of semiconductor devices, improve semiconductor device channel area
Carrier mobility.
To solve the above problems, the present invention provide it is a kind of substrate is provided, formed with grid structure in the substrate；To described
The substrate of grid structure both sides carries out pre-amorphous processing, and amorphous area is formed in the substrate of the grid structure both sides；Institute
State and source and drain doping area is formed in the substrate of grid structure both sides；Stress cap is formed on the amorphous area；To the stress
Cap and amorphous area are made annealing treatment, and the annealing is suitable to make the amorphous area be formed during recrystallizing
Dislocation, the dislocation are suitable to provide tension to the channel region below the grid structure.
Optionally, the pre-amorphous processing is carried out using ion implantation technology.
Optionally, the injection ion of the ion implantation technology is Ge, C or N.
Optionally, the technological parameter of the pre-amorphous processing includes：Injection ion is Ge, Implantation Energy be 35kev~
50kev, implantation dosage 1E14atom/cm2~2E15atom/cm2。
Optionally, before the annealing is carried out, the source and drain doping area is located at the intrabasement depth ratio institute
It is deep positioned at the intrabasement depth to state amorphous area；After the annealing is carried out, the source and drain doping area parcel is described non-
Crystalline region.
Optionally, the annealing includes spike annealing and the laser annealing carried out successively.
Optionally, the technological parameter of the spike annealing includes：Annealing temperature is 950 DEG C~1050 DEG C；The laser moves back
The technological parameter of fire includes：Annealing temperature is 1000 DEG C~1200 DEG C.
Optionally, the material of the stress cap is silicon nitride.
Optionally, the thickness of the stress cap is 50 angstroms~1000 angstroms.
Optionally, the stress cap is also located at the top of the grid structure and in side wall.
Optionally, formed with isolation structure in the substrate, wherein, the grid structure is between adjacent isolation structures
Substrate on；And before pre-amorphous processing is carried out, edge grid are formed also on the isolation structure, the edge grid are at least
Covering and the adjacent portions of isolation structure of the substrate.
Optionally, on the direction for the isolation structure for pointing to opposite side in the isolation structure along grid structure side, the side
The width dimensions of edge grid are more than or equal to the 1/4 of isolation structure top dimension.
Optionally, before the amorphous area is formed, in addition to step：Mask side is formed on the gate structure sidewall
Wall；Using the mask side wall as mask, etching is located at the substrate of the segment thickness of the grid structure both sides, in the substrate
Form groove；Form the doped epitaxial layer in situ of the full groove of filling, in the doped epitaxial layer in situ doped with N-type from
Son；Wherein, the pre-amorphous processing is carried out to the doped epitaxial layer in situ and forms the amorphous area.
Optionally, the amorphous area of formation is located in the doped epitaxial layer in situ.
Optionally, the material of the doped epitaxial layer in situ is the silicon containing phosphonium ion, wherein, the doping concentration of phosphonium ion
For 5E20atom/cm3~2.5E21atom/cm3。
Optionally, before the stress cap is formed, the mask side wall is removed.
Optionally, the mask side wall includes the first mask side wall and second covering in the first mask side wall side wall
Film side wall, wherein, the material of the first mask side wall is silica, and the material of the second mask side wall is silicon nitride.
Optionally, before the mask side wall is formed, in addition to step：Skew is formed on the gate structure sidewall
Side wall；Using the offset side wall as mask, the substrate of the grid structure both sides is doped, forms source and drain lightly doped district；
Wherein, the mask side wall is located in the offset side wall side wall.
Optionally, after an annealing treatment, interlayer dielectric layer also is formed in the stress cap, and described in formation
After interlayer dielectric layer, in addition to step：Interlayer dielectric layer and stress cap of the etching positioned at the grid structure both sides
Contact hole is formed, the contact hole exposes source and drain doping area surface；Form the contact plunger of the full contact hole of filling.
Optionally, the grid structure is pseudo- grid structure；After an annealing treatment, also formed in the stress cap
Interlayer dielectric layer, and after the interlayer dielectric layer is formed, in addition to step：The grid structure is removed, in the interlayer
Opening is formed in dielectric layer；Form the high-k/metal gate of the full opening of filling.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the forming method of semiconductor devices provided by the invention, the substrate of grid structure both sides is carried out
Pre-amorphous processing, form amorphous area；And source and drain doping area is formed in grid structure；Then, being formed on amorphous area should
Power cap, then stress cap and amorphous area are made annealing treatment, therefore amorphous area converts from amorphous state to crystalline state
During its volume be difficult to become big so that amorphous area recrystallizes to form dislocation under the conditions of annealing, and the dislocation is suitable to
Tension is provided into the channel region below grid structure, so as to improve the carrier mobility in channel region, and is avoided existing
Have in technology by grid structure to channel region apply stress the drawbacks of, improve the electric property of the semiconductor devices to be formed.
Alternative, before being made annealing treatment, source and drain doping area is located at amorphous described in the intrabasement depth ratio
Area is located at intrabasement depth depth, ensures that source and drain doping area wraps amorphous area after the annealing process, avoids amorphous area from causing
Current leakage, further improve semiconductor devices electric property.
In alternative, before pre-amorphous processing is carried out, edge grid, the edge grid are formed also on isolation structure
At least covering and the adjacent portions of isolation structure of the substrate.In annealing process, because edge grid are to isolation structure
With the squeezing action for pointing to substrate bottom direction, therefore amorphous area is during amorphous state is converted into crystalline state, amorphous area
Volumetric expansion is difficult to be transferred to the external world by isolation structure so that formation dislocation as much as possible in amorphous area, so as to improve position
Mistake is applied to the size of the tension of grid structure underlying channel region.
Brief description of the drawings
Fig. 1 to Figure 12 is the cross-sectional view of semiconductor devices forming process provided in an embodiment of the present invention.
Embodiment
From background technology, the performance for the semiconductor devices that prior art is formed still needs further to be improved.
Common, the principle of the semiconductor devices formed using SMT technologies is, forms the stress lid of covering grid structure
Cap layers, then using annealing process, the grid structure of stress cap bottom is recrystallized, is carried by grid structure to channel region
For tension.However, the stress that the grid structure applies to channel region is limited, and when the grid structure is removed
When, grid structure will also disappear to the stress that channel region applies.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, there is provided substrate, in the substrate
Formed with grid structure；Pre-amorphous processing is carried out to the substrate of the grid structure both sides, in the grid structure both sides
Amorphous area is formed in substrate；Source and drain doping area, and the source and drain doping position are formed in the substrate of the grid structure both sides
It is deep positioned at the intrabasement depth in amorphous area described in the intrabasement depth ratio；Stress lid is formed on the amorphous area
Cap layers；The stress cap and amorphous area are made annealing treatment, the annealing is suitable to make the amorphous area in weight
Dislocation is formed in new crystallization process, the dislocation is suitable to provide tension to the channel region below the grid structure.
The present invention in the substrate of grid structure both sides by forming dislocation, by the dislocation to below grid structure
Channel region in provide action of pulling stress, so as to avoid by grid structure to channel region provide tension have the drawbacks of,
Improve the electric property of the semiconductor devices formed.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 12 is the cross-sectional view of semiconductor devices forming process provided in an embodiment of the present invention.
With reference to figure 1, there is provided substrate 201, formed with grid structure 203 in the substrate 201.
In the present embodiment, the substrate 201 is silicon substrate.In other embodiments, the substrate can also be germanium substrate,
Silicon substrate on silicon-Germanium substrate, silicon carbide substrates, gallium arsenide substrate, gallium indium substrate or insulator.In other embodiment
In, when the semiconductor devices of formation is fin field effect pipe, the substrate can also include substrate and the fin on substrate
Portion, wherein, grid structure covers the atop part and side wall of fin across the fin.
In the present embodiment, be also formed with isolation structure 202 in the substrate 201, the grid structure 202 positioned at it is adjacent every
From in the substrate 201 between structure 202.Wherein, the isolation structure 202 is that shallow trench isolates (STI, shallow trench
Isolation) structure or carrying out local oxide isolation (LOCOS, Local Oxidation of Silicon) structure.The present embodiment
In, the material of the isolation structure 202 is silica, and in other embodiments, the material of the isolation structure can also be nitrogen
SiClx or silicon oxynitride.In the present embodiment, the top of the isolation structure 202 flushes with the top of substrate 201, in other embodiment
In, it can be above base top at the top of the isolation structure.
In the present embodiment, boundary layer 205 is also formed with the surface of substrate 201, the boundary layer 205 is to the substrate
201 play a protective role, and reduce follow-up ion implantation technology lattice damage to caused by the surface of substrate 201.The boundary layer
205 material is silica or silicon nitride.In other embodiments, the boundary layer can also be only located at grid structure and substrate
Between.
It should be noted that in order to which the dislocation for preventing from being subsequently formed provides larger stress into isolation structure 202, ensure
Dislocation is as much as possible to apply stress into the channel region of the lower section of grid structure 203, can also on the isolation structure 202 shape
Into edge grid 204.
The effect of the edge grid 204 includes：On the one hand, offset side wall is formed subsequently in the side wall of edge grid 204 and is covered
Amorphous area is re-formed after film side wall so that there is a certain distance between amorphous area and isolation structure 202, be subsequently formed accordingly
Dislocation and isolation structure 202 between will also have a certain distance, carried so as to effectively reduce dislocation to isolation structure 202
The stress of confession so that dislocation is greater concentration of to provide tension into the channel region of the lower section of grid structure 203；On the other hand, institute
State edge grid 204 and be located at the top of isolation structure 202, the volume that the edge grid 204 can limit isolation structure 202 becomes
Change, main can avoid the material volume of isolation structure 202 from expanding so that the amorphous area being subsequently formed is difficult to pass through isolation structure
Volumetric expansion is transferred to the external world by 202, ensures to produce substantial amounts of dislocation in amorphous area.
In the present embodiment, the edge grid 204 have relative the first side wall and second sidewall, wherein, second sidewall
The distance between grid structure 203 is less than the distance between the first side wall and grid structure 203, and the second sidewall is at least
On interface between isolation structure 202 and substrate 201, that is to say, that the edge grid 204 at least cover and the substrate
201 adjacent portions of isolation structure 202, ensure the isolation structure 202 between edge grid 204 and substrate 201 by edge grid 204
Covering.In other embodiments, the edge grid may be located on and the isolation structure phase in addition on isolation structure
On adjacent part of substrate.
In order to reduce processing step, the edge grid 204 and grid structure 203 can in the processing step with along with shape
Into, and the edge grid 204 and the grid structure 203 are mutually discrete.In the present embodiment, to use rear grid technique (gate
Last) being formed exemplified by semiconductor devices, the grid structure 203 is pseudo- grid structure, in the present embodiment, the grid structure 203
Material be polysilicon, the material of the edge grid 204 is polysilicon.In other embodiments, the material of the grid structure
Can also be amorphous carbon, the material of the edge grid can also be amorphous carbon.
In the present embodiment, the isolation structure 202 of opposite side is pointed in the isolation structure 202 along the side of grid structure 203
On direction, the width dimensions of the edge grid 204 are unsuitable too small, and otherwise subsequent edges grid 204 limit the volume of isolation structure 202 and become
The ability of change is excessively weak, causes isolation structure 202 that the volumetric expansion of amorphous area is transferred into the external world.Therefore, in the present embodiment, on edge
The isolation structure 202 of the side of grid structure 203 is pointed on the direction of the isolation structure 202 of opposite side, the width of the edge grid 204
Spend size is more than or equal to the top width size of isolation structure 202 1/4.In other embodiments, the edge grid can be with
Cover all tops of isolation structure.
It should be noted that in other embodiments, first grid technique (gate first) can also be used to form semiconductor
Device, accordingly, the grid structure are high-k/metal gate, the material of the edge grid and the material phase of the grid structure
Together.
In order to improve hot carrier's effect problem, further improve the electric property of semiconductor devices, in the present embodiment
Formed before amorphous area, source and drain lightly doped district is formed also in substrate.It is described in detail below with reference to accompanying drawing.
With reference to figure 2, offset side wall is formed in the side wall of grid structure 203；Using the offset side wall as mask, to institute
The substrate 201 for stating the both sides of grid structure 203 is doped, and forms source and drain lightly doped district (not shown).
In the present embodiment, the offset side wall is laminated construction, including the first skew in the side wall of grid structure 203
Side wall 213 and the second offset side wall 223 in the side wall of the first offset side wall 213, wherein, first offset side wall
213 material is different from the material of the second offset side wall 223, wherein, the material of the first offset side wall 213 is silica, second
The material of offset side wall 223 is silicon nitride.In another embodiment, the offset side wall can also be ONO (oxide-
Nitride-oxide) the offset side wall of structure.
It should be noted that in other embodiments, the offset side wall can also be single layer structure, the offset side wall
Material be silica, silicon nitride or silicon oxynitride.
In the present embodiment, in the side wall of grid structure 203 formed offset side wall technical process in, formation it is described
Offset side wall is also located in the side wall of edge grid 204.
After the offset side wall is formed, ion implanting work is carried out to the substrate 201 of the both sides of grid structure 203
Skill, the injection ion of ion implantation technology are N-type ion, for example, P, As or Sb, the substrate in the both sides of grid structure 203
Source and drain lightly doped district is formed in 201, wherein, the source and drain lightly doped district is used for LDD (the Low Doped as semiconductor devices
Drain) structure.
After being doped to the substrate 201 of the grid structure both sides, in order to repair the lattice damage that substrate 201 is subject to
Wound, and make it that the Doped ions concentration in source and drain lightly doped district is redistributed, the substrate 201 is made annealing treatment, institute
It can be spike annealing (spike anneal) to state annealing.
With reference to figure 3, mask side wall is formed in the side wall of grid structure 203；Using the mask side wall as mask, etching
Positioned at the substrate 201 of the segment thickness of the both sides of grid structure 203, groove 206 is formed in the substrate 201.
Due to being also formed with offset side wall in the side wall of grid structure 203, therefore the mask side wall formed is positioned at described
In offset side wall side wall.In other embodiments, when not forming offset side wall on the gate structure sidewall, then what is formed is described
Mask side wall is on gate structure sidewall.
In the present embodiment, the mask side wall includes the first mask side wall 233 and positioned at the side wall of the first mask side wall 233
On the second mask side wall 243, wherein, the material of the first mask side wall 233 is silica, the second mask side wall
244 material is silicon nitride.In another embodiment, the mask side wall can also be the side wall of ONO structure.
In other embodiments, the mask side wall can also be single layer structure, and the material of the mask side wall is oxidation
Silicon, silicon nitride or silicon oxynitride.
In the present embodiment, the section shape of the groove 206 is U-shaped.In other embodiments, the section shape of the groove
Shape can also be square or sigma shapes.
Using dry etch process, etching positioned at the segment thickness of the mask side wall both sides substrate 201, described in formation
Groove 206, wherein, the dry etch process is anisotropic etch process.In other embodiments, the section of the groove
When being shaped as sigma shapes, pre-groove is first formed using the substrate of anisotropic etch process etching grid structure both sides；Then,
Isotropic etching processing is carried out to the pre-groove, forms the sigma connected in stars.
The depth of the groove 206 is more than or equal to the depth for the amorphous area being subsequently formed.It is advantageous in that rear extended meeting exists
The full doped epitaxial layer in situ of filling in the groove 206；Because the depth of groove 206 is more than or equal to the amorphous area being subsequently formed
Depth, the depth of the doped epitaxial layer in situ formed accordingly also above or equal to the depth for the amorphous area being subsequently formed,
So that pre-amorphous processing subsequently is carried out to doped epitaxial layer in situ, you can to form the amorphous area；In same pre- amorphous
Under the process conditions for changing processing, the non-crystallization degree of doped epitaxial layer in situ is more than the non-crystallization degree of substrate 201 so that this reality
Applying the amorphous area being subsequently formed in example has higher non-crystallization degree, applies so as to improve the dislocation being subsequently formed to channel region
Tension.
In the present embodiment, the depth of the groove 206 is 10 nanometers~30 nanometers.
With reference to figure 4, the doped epitaxial layer 207 in situ of the full groove 206 (with reference to figure 3) of filling is formed, the original position is mixed
Doped with N-type ion in miscellaneous epitaxial layer 207.
The doped epitaxial layer 207 in situ is formed using selective epitaxial process (selective epi), specifically, institute
State doped epitaxial layer 207 in situ material be doped with the silicon of N-type ion, germanium, carborundum or SiGe, wherein, N-type ion bag
Include phosphonium ion, arsenic ion or antimony ion.
In the present embodiment, the material of the doped epitaxial layer 207 in situ is the silicon doped with phosphonium ion.The doping in situ
The effect of epitaxial layer 207 includes：First, due to being passed through in doped epitaxial layer 207 in situ doped with N-type ion, therefore with substrate 201
The non-crystallization degree for going through pre-amorphous processing formation amorphous area is compared, after doped epitaxial layer 207 in situ undergoes pre-amorphous processing
The non-crystallization degree of the amorphous area of formation is higher, and the stress that the dislocation being accordingly subsequently formed provides is bigger；Second, the original position is mixed
Miscellaneous epitaxial layer 207 provides Process ba- sis to be subsequently formed source and drain doping area.
In the present embodiment, the material of the doped epitaxial layer 207 in situ is the silicon containing phosphonium ion, wherein, phosphonium ion
Doping concentration is 5E20atom/cm3~2.5E21atom/cm3, such as the doping concentration of phosphonium ion is 2.2E21atom/cm3。
The depth of the doped epitaxial layer 207 in situ is more than or equal to the depth for the amorphous area being subsequently formed, and its benefit can
Referring to the foregoing corresponding description to groove 206.
In the present embodiment, the top of the doped epitaxial layer 207 in situ is higher than the top of substrate 201.In other embodiments,
The top of the doped epitaxial layer in situ can also flush with base top.
With reference to figure 5, pre-amorphous processing 208 is carried out to the substrate 201 of the both sides of grid structure 203, in the grid
Amorphous area 209 is formed in the substrate 201 of the both sides of structure 203.
The pre-amorphous processing 208 is carried out using ion implantation technology, the injection ion of the ion implantation technology is
Ge, C or N, the injection ion of ion implantation technology can destroy the lattice structure of substrate 201 so that the substrate 201 of segment thickness from
Crystalline state is converted into amorphous state, so as to form amorphous area 209.
Due to foregoing interior formed with doped epitaxial layer 207 in situ in substrate 201, therefore in fact, it is pair in the present embodiment
The doped epitaxial layer 207 in situ of the both sides of grid structure 203 carries out pre-amorphous processing 208, in the doped epitaxial layer 207 in situ
Interior formation amorphous area 209.
In the present embodiment, the amorphous area 209 is located in the doped epitaxial layer 207 in situ, that is to say, that the amorphous
The depth in area 209 is less than or equal to the depth of the doped epitaxial floor 207 in situ so that the lattice in amorphous area 209 is decrystallized
Degree is larger, is advantageous to improve the tension size that the dislocation being subsequently formed applies to the channel region of the lower section of grid structure 203.
In other embodiment, the depth of the amorphous area can also be more than doped epitaxial layer in situ, accordingly, a part for formation it is non-
Crystalline region is converted by doped epitaxial layer in situ and formed, and the amorphous area of another part is converted by substrate to be formed.
In a specific embodiment, the technological parameter of the pre-amorphous processing 208 includes：Injection ion is Ge, note
It is 35kev~50kev, implantation dosage 1E14atom/cm to enter energy2~2E15atom/cm2.Need, it is described pre- non-
The technological parameter of Crystallizing treatment, it can be determined according to the depth of the doped epitaxial layer in situ of formation.
In the present embodiment, the depth of the amorphous area 209 is 15 nanometers~50 nanometers.
It should be noted that the doped epitaxial layer 207 in situ can be as a part for substrate 201, therefore " to grid
The doped epitaxial layer 207 in situ of the both sides of structure 203 carries out pre-amorphous processing and 208 " still can be regarded as " to 203 liang of grid structure
The substrate 201 of side carries out pre-amorphous processing 20, forms amorphous area 209 ".
It should also be noted that, in other embodiments, it can also be formed after mask side wall, directly to grid structure two
The substrate of side carries out pre-amorphous processing, and amorphous area is formed in the substrate of the grid structure both sides.
With continued reference to Fig. 5, after the amorphous area 209 is formed, in the substrate 201 of the both sides of grid structure 203
Form source and drain doping area 210, and amorphous area 209 be located at depth ratio in substrate 201 described in source and drain doping area 210 be located at substrate
Depth as shallow in 201.
Specifically, using the mask side wall as mask, ion note is carried out to the substrate 201 of the both sides of grid structure 203
Enter technique, form the source and drain doping area 210, wherein, the Doped ions in the source and drain doping area 201 are N-type ion, such as
For phosphonium ion, arsenic ion or antimony ion.
The amorphous area 209 is located at source and drain doping area 210 described in the depth ratio in substrate 201 and is located at the depth in substrate 201
Spend shallow, ensure after follow-up made annealing treatment, live through the amorphous area that the source and drain doping area 210 that ion spreads again is wrapped to form
209, so as to suppress current leakage caused by dislocation.
With reference to figure 6, the mask side wall is removed.
Specifically, remove the first mask side wall 233 (with reference to figure 5) and the second mask side wall 243 (with reference to figure 5).
With reference to figure 7, stress cap 211, the stress are formed on the amorphous area 209 and on grid structure 203
The material density of cap 211 is more than the material density of the amorphous area 209.
In the present embodiment, the stress cap 211 is covered in the top of grid structure 203 and side wall, the stress lid
Cap layers 211 are also covered in the top of edge grid 204 and side wall.
The effect of the stress cap 211 includes：In follow-up annealing process, the material of the amorphous area 209
Material lattice changes and becomes big trend with volume, and the material density of the stress cap 211 is big, plays and suppresses non-
The effect of the volumetric expansion of crystalline region 209, due to the volumetric expansion difficulty increase of amorphous area 205, and then to be formed in amorphous area 209
Dislocation.
In the present embodiment, the material of the stress cap 211 is silicon nitride, and using plasma strengthens chemical vapor deposition
Product technique is formed.In other embodiments, the material of the stress cap can also be formed using low pressure gas phase deposition technique
Silicon nitride, the tetraethyl orthosilicate that is formed using chemical vapor deposition method or pass through the high vertical wide oxidation formed than technique
Silicon.
In the present embodiment, the thickness of the stress cap 211 is 50 angstroms~1000 angstroms.
With reference to figure 8, to the stress cap 211 and amorphous area 209) carry out annealing 301, the annealing
301 are suitable to make the amorphous area 209 form dislocation 30 during recrystallizing, and the dislocation 30 is suitable to grid structure 203
The channel region of lower section provides tension.
In the present embodiment, the annealing 301 includes spike annealing and the laser annealing carried out successively, wherein, institute
Stating the technological parameter of spike annealing includes：Annealing temperature is 950 DEG C~1050 DEG C；The technological parameter of the laser annealing includes：
Annealing temperature is 1000 DEG C~1200 DEG C.
During the annealing 301, the Doped ions in the source and drain doping area 210 are diffused redistribution.
In addition, during annealing 301, the material in the amorphous area 209 is converted from amorphous state to crystalline state, and the amorphous area
209 volumes have inflationary spiral；Due to being covered at the top of amorphous area 209 by stress cap 211 so that amorphous area 209 is difficult to send out
Raw volumetric expansion, and then splay dislocation 30 is formed in amorphous area 209, wherein, the dislocation 30 is suitable to grid structure
The channel region of 203 lower sections provides tension.
Wherein, the dislocation 30 is upwardly formed along [111] crystalline substance, so that forming splay position in amorphous area 209
Mistake 30.
It is also, described due to being formed on the basis of amorphous area 209 in the original location doped epitaxial layer 207 in the present embodiment
The non-crystallization degree of amorphous area 209 is higher, therefore amorphous area 209 is converted into crystalline state by amorphous state during annealing 301
The quantity of caused dislocation 30 also will be larger, so that the drawing that dislocation 30 provides to the channel region of the lower section of grid structure 203
The effect of stress is significantly enhanced.
In addition, during annealing 301, isolation structure 202 top adjacent with amorphous area 209 is formed with edge grid
204, the edge grid 204 have squeezing action to isolation structure 202 so that the volumetric expansion of amorphous area 209 be difficult to by every
Passed from structure 202, ensure that the caused quantity of dislocation 30 during annealing 301 of amorphous area 209 is larger.
If not forming edge grid on isolation structure, in annealing process, the amorphous area volume expands
The isolation structure adjacent with amorphous area is extruded afterwards so that the volumetric expansion of amorphous area is transferred in isolation structure and then is transferred to outer
Boundary, therefore amorphous area amorphous state is converted into the quantity of caused dislocation during crystalline state and will reduced, corresponding dislocation is to grid knot
The tension that channel region below structure provides will also reduce.
With reference to figure 9, interlayer dielectric layer 303 is formed in the stress cap 211, the interlayer dielectric layer 303 is located at
In the side wall of grid structure 203.The material of the interlayer dielectric layer 303 is silica, silicon nitride or silicon oxynitride.
In the present embodiment, the top of the interlayer dielectric layer 303 flushes with the top of grid structure 203, forms the interlayer
The processing step of dielectric layer 303 includes：Interlayer deielectric-coating, the inter-level dielectric film top are formed in the stress cap 211
Portion is higher than the top of grid structure 203；Using chemical mechanical milling tech, grinding removes the interlayer higher than the top of grid structure 203
Deielectric-coating, the interlayer dielectric layer 203 is formed, also grinding removes the stress cap 211 higher than the top of grid structure 203, cruelly
Expose the top of grid structure 203；And also grinding removes the stress cap 211 higher than the top of edge grid 204, exposes edge grid
204 tops.
With reference to figure 10, the grid structure 203 (with reference to figure 9) is removed, opening is formed in the interlayer dielectric layer 303；
Form the high-k/metal gate of the full opening of filling.
In the present embodiment, in the technical process for removing the grid structure 203, the edge grid 204 (reference is also removed
Fig. 9)；In the technical process for forming the high-k/metal gate, the high k gold in edge is formed in the position where the edge grid 204
Belong to grid.
The high-k/metal gate includes：High-k gate dielectric layer 311, the metal level 312 on high-k gate dielectric layer 311, its
In, the material of high-k gate dielectric layer 311 includes HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3, gold
The material of category layer 312 includes Cu, Al or W.In order to improve the threshold voltage of semiconductor devices, the high-k gate dielectric layer 311 and gold
Work-function layer can also be formed between category layer 312, the material of the work-function layer is TiAl, TiAlN, TiAlC or AlN.
The edge high-k/metal gate includes：Edge high-k gate dielectric layer 411, on edge high-k gate dielectric layer 411
Edge metal layer 412.
With reference to figure 11, etching is located at the interlayer dielectric layer 303 and stress cap 211 of the both sides of grid structure 203,
Form the contact hole 304 for exposing the surface of source and drain doping area 210.
The interlayer dielectric layer 303 and stress cap 211 are etched using dry etch process.In a specific embodiment
In, forming the processing step of the contact hole 304 includes：Graph layer, the graph layer are formed on the interlayer dielectric layer 303
Define the positions and dimensions of contact hole；Using the graph layer as mask, the interlayer dielectric layer 303 and stress block are etched
Layer 211, forms the contact hole 304；Remove the graph layer.
, can also be described in order to reduce the contact resistance between source and drain doping area 210 and the contact plunger being subsequently formed
The surface of source and drain doping area 210 that contact hole 304 exposes forms metal silicide layer (not shown).
With reference to figure 12, the contact plunger 305 for filling the full contact hole 304 (with reference to figure 11) is formed.
The material of the contact plunger 305 is copper, aluminium or tungsten.
In the present embodiment, the material of the contact plunger 305 is tungsten., can be with before the contact plunger 305 is formed
Barrier layer is formed on the bottom of contact hole 304 and side wall, the material on the barrier layer is TiN or TaN.
In the forming method for the semiconductor devices that the present embodiment provides, the substrate progress to grid structure both sides is pre-amorphous
Processing, form amorphous area；And source and drain doping area is formed in grid structure, and source and drain doping area is located at the intrabasement depth
Degree be located at intrabasement depth depth than the amorphous area, ensure subsequent anneal handle after source and drain doped region by the amorphous area bag of formation
Wrap, avoid current leakage caused by amorphous area；Then, stress cap is formed on amorphous area, then to stress block
Layer and amorphous area are made annealing treatment, because the material density of stress cap is more than the material density of amorphous area, therefore
Amorphous area is from amorphous state, into crystalline state conversion process, its volume is difficult to become big so that dislocation, the dislocation are formed in amorphous area
Suitable for providing tension into the channel region below grid structure, so as to improve the carrier mobility in channel region, and avoid
In the prior art by grid structure to channel region apply stress the drawbacks of, improve the electrical property of the semiconductor devices to be formed
Energy.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Substrate is provided, formed with grid structure in the substrate；Pre-amorphous processing is carried out to the substrate of the grid structure both sides, formed in the substrate of the grid structure both sides non- Crystalline region；Source and drain doping area is formed in the substrate of the grid structure both sides；Stress cap is formed on the amorphous area；The stress cap and amorphous area are made annealing treatment, the annealing is suitable to make the amorphous area again Dislocation is formed in crystallization process, the dislocation is suitable to provide tension to the channel region below the grid structure.
- 2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that institute is carried out using ion implantation technology State pre-amorphous processing.
- 3. the forming method of semiconductor devices as claimed in claim 2, it is characterised in that the injection of the ion implantation technology Ion is Ge, C or N.
- 4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the technique of the pre-amorphous processing Parameter includes：Injection ion is Ge, and Implantation Energy is 35kev~50kev, implantation dosage 1E14atom/cm2~ 2E15atom/cm2。
- 5. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that carrying out the annealing Before, it is deep positioned at the intrabasement depth that the source and drain doping area is located at amorphous area described in the intrabasement depth ratio；Entering After the row annealing, the amorphous area is wrapped up in the source and drain doping area.
- 6. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the annealing includes entering successively Capable spike annealing and laser annealing.
- 7. the forming method of semiconductor devices as claimed in claim 6, it is characterised in that the technological parameter of the spike annealing Including：Annealing temperature is 950 DEG C~1050 DEG C；The technological parameter of the laser annealing includes：Annealing temperature be 1000 DEG C~ 1200℃。
- 8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the material of the stress cap is Silicon nitride.
- 9. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the thickness of the stress cap is 50 angstroms~1000 angstroms.
- 10. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the stress cap is also located at At the top of the grid structure and in side wall.
- 11. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that formed with isolation in the substrate Structure, wherein, the grid structure is in the substrate between adjacent isolation structures；And before pre-amorphous processing is carried out, Edge grid are formed also on the isolation structure, the edge grid at least cover the part isolation junction adjacent with the substrate Structure.
- 12. the forming method of semiconductor devices as claimed in claim 11, it is characterised in that along grid structure side every On direction from the isolation structure that structure points to opposite side, the width dimensions of the edge grid are more than or equal to width at the top of isolation structure Spend the 1/4 of size.
- 13. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that before the amorphous area is formed, Also include step：Mask side wall is formed on the gate structure sidewall；Using the mask side wall as mask, etching is located at the substrate of the segment thickness of the grid structure both sides, in the substrate Interior formation groove；The doped epitaxial layer in situ of the full groove of filling is formed, doped with N-type ion in the doped epitaxial layer in situ；Wherein, the pre-amorphous processing is carried out to the doped epitaxial layer in situ and forms the amorphous area.
- 14. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that the amorphous area of formation is located at In the doped epitaxial layer in situ.
- 15. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that the doped epitaxial layer in situ Material is the silicon containing phosphonium ion, wherein, the doping concentration of phosphonium ion is 5E20atom/cm3~2.5E21atom/cm3。
- 16. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that forming the stress cap Before, the mask side wall is removed.
- 17. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that the mask side wall includes first Mask side wall and the second mask side wall in the first mask side wall side wall, wherein,The material of the first mask side wall is silica, and the material of the second mask side wall is silicon nitride.
- 18. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that formed the mask side wall it Before, in addition to step：Offset side wall is formed on the gate structure sidewall；Using the offset side wall as mask, the substrate of the grid structure both sides is doped, forms source and drain lightly doped district；Wherein, the mask side wall is located in the offset side wall side wall.
- 19. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that after an annealing treatment, in addition to Step：Interlayer dielectric layer is formed in the stress cap；Interlayer dielectric layer and stress cap of the etching positioned at the grid structure both sides form contact hole, the contact hole dew Go out source and drain doping area surface；Form the contact plunger of the full contact hole of filling.
- 20. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the grid structure is pseudo- grid knot Structure；After an annealing treatment, interlayer dielectric layer also is formed in the stress cap,And after the interlayer dielectric layer is formed, in addition to step：The grid structure is removed, in the interlayer dielectric layer Form opening；Form the high-k/metal gate of the full opening of filling.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444473A (en) * | 2019-08-29 | 2019-11-12 | 上海华力集成电路制造有限公司 | The manufacturing method of embedded SiGe device and embedded SiGe device structure |
| CN115547936A (en) * | 2022-12-02 | 2022-12-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635312A (en) * | 2008-07-24 | 2010-01-27 | 国际商业机器公司 | Device structures with a self-aligned damage layer and methods for forming such device structures |
| US7777284B2 (en) * | 2007-05-28 | 2010-08-17 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of forming the same |
| CN102339859A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Metal-oxide-semiconductor (MOS) transistor and formation method thereof |
| US20120190216A1 (en) * | 2011-01-20 | 2012-07-26 | International Business Machines Corporation | Annealing techniques for high performance complementary metal oxide semiconductor (cmos) device fabrication |
| CN102867784A (en) * | 2011-07-06 | 2013-01-09 | 台湾积体电路制造股份有限公司 | Semiconductor device with a dislocation structure and method of forming the same |
| CN103515238A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and formation method, CMOS structure and formation method thereof |
| CN103943504A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104241366A (en) * | 2013-06-07 | 2014-12-24 | 台湾积体电路制造股份有限公司 | Dislocation formation in source electrode region and drain electrode region of FinFET device |
| CN104934324A (en) * | 2014-03-18 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
-
2016
- 2016-06-13 CN CN201610420475.5A patent/CN107492487B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7777284B2 (en) * | 2007-05-28 | 2010-08-17 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of forming the same |
| CN101635312A (en) * | 2008-07-24 | 2010-01-27 | 国际商业机器公司 | Device structures with a self-aligned damage layer and methods for forming such device structures |
| CN102339859A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Metal-oxide-semiconductor (MOS) transistor and formation method thereof |
| US20120190216A1 (en) * | 2011-01-20 | 2012-07-26 | International Business Machines Corporation | Annealing techniques for high performance complementary metal oxide semiconductor (cmos) device fabrication |
| CN102867784A (en) * | 2011-07-06 | 2013-01-09 | 台湾积体电路制造股份有限公司 | Semiconductor device with a dislocation structure and method of forming the same |
| CN103515238A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and formation method, CMOS structure and formation method thereof |
| CN103943504A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104241366A (en) * | 2013-06-07 | 2014-12-24 | 台湾积体电路制造股份有限公司 | Dislocation formation in source electrode region and drain electrode region of FinFET device |
| CN104934324A (en) * | 2014-03-18 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444473A (en) * | 2019-08-29 | 2019-11-12 | 上海华力集成电路制造有限公司 | The manufacturing method of embedded SiGe device and embedded SiGe device structure |
| CN115547936A (en) * | 2022-12-02 | 2022-12-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
| CN115547936B (en) * | 2022-12-02 | 2023-06-16 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
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