CN110034181A - A kind of iron/piezoelectricity field-effect tube and its preparation method - Google Patents

A kind of iron/piezoelectricity field-effect tube and its preparation method Download PDF

Info

Publication number
CN110034181A
CN110034181A CN201910159715.4A CN201910159715A CN110034181A CN 110034181 A CN110034181 A CN 110034181A CN 201910159715 A CN201910159715 A CN 201910159715A CN 110034181 A CN110034181 A CN 110034181A
Authority
CN
China
Prior art keywords
layer
effect tube
substrate
material layer
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910159715.4A
Other languages
Chinese (zh)
Inventor
陕皓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN201910159715.4A priority Critical patent/CN110034181A/en
Publication of CN110034181A publication Critical patent/CN110034181A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

The present invention provide a kind of iron/piezoelectricity field-effect tube and its preparation method, including substrate, source-drain electrode and grid;Grid includes: the silica from bottom to top stacked gradually, high dielectric layer, piezoelectric material layer, titanium nitride layer, ferroelectric material layer and tantalum nitride layer.The preparation method comprises the following steps: providing silicon substrate, the doped p-type ion in silicon substrate forms substrate;Source electrode and drain electrode is formed in the two sides of substrate;Above substrate, silicon dioxide layer and high dielectric layer are sequentially formed between source electrode and drain electrode;Piezoelectric material layer, titanium nitride layer, ferroelectric material layer and tantalum nitride layer are sequentially formed on high dielectric layer.The present invention is based on field effect transistor, ferroelectric material and piezoelectric material are introduced in the gate, realize the function of voltage amplification jointly using the negative capacitance effect of ferroelectric material and the electrostriction effect of piezoelectric material.The operating voltage of device is reduced, subthreshold swing is reduced, improves the ON/OFF speed of device, further decrease operating power consumption.

Description

A kind of iron/piezoelectricity field-effect tube and its preparation method
Technical field
The present invention relates to semiconductor device design manufacturing field, more particularly to a kind of iron/piezoelectricity field-effect tube and its Preparation method.
Background technique
With the promotion of cmos device integration density, growing power consumption will become restriction integrated circuit and further develop Important bottleneck.It is a kind of effective hand for reducing and using power consumption that operating voltage is reduced by reducing the subthreshold swing of device Section.Field effect transistor with negative capacitance effect is the effective technology scheme for realizing this purpose.
Subthreshold swing is reduced by the adjustment to gate oxide structure and thickness composition, channel design and material at present Value, to reduce device power consumption.But these modes can not all make subthreshold swing be less than a 60mV/decade (quantity Grade).
Subthreshold swing SS meets following equation:
Wherein,For the variation of gate source voltage,For the variation of silicon face potential, IdFor source-drain current,For source-drain current varied number grade, CinsTo aoxidize layer capacitance, usually positive value.It is, in general, that the limiting value of SS About 60mV/decade.It, can be by by C but to make SS be less than 60mV/decadesBecome the mode of negative value to obtain.
Therefore it provides a kind of new field effect transistor and preparation method thereof based on negative capacitance, becomes this field urgently The important technological problems solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of iron/piezoelectricity field-effect tube and Its preparation method, for solving the problems, such as high working voltage, high power consumption in MOS device in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of iron/piezoelectricity field-effect tube, includes at least: Substrate;Source electrode and drain electrode positioned at the substrate two sides;Grid above the substrate, between the source electrode and drain electrode; The grid includes: the silicon dioxide layer from bottom to top stacked gradually, high dielectric layer, piezoelectric material layer, titanium nitride layer, ferroelectricity material The bed of material and tantalum nitride layer.
Preferably, the substrate is P-type substrate.
Preferably, the high dielectric layer includes HfO2、ZrO2、Ta2O5、TiO2In any one.
Preferably, the piezoelectric material layer be electrostriction material, including aluminium nitride/gallium nitride, lead titanates, barium titanate, Any one in lead niobate.
Preferably, the ferroelectric material layer includes HfO2、HfAlO2、HfZrO2In any one.
Preferably, the field-effect tube is NMOS tube.
A kind of preparation method of iron/piezoelectricity field-effect tube, this method at least include the following steps: Step 1: providing silicon substrate Plate, the doped p-type ion in the silicon substrate form substrate;Step 2: forming source electrode and drain electrode in the two sides of the substrate; Step 3: sequentially forming silicon dioxide layer and high dielectric layer between side, the source electrode and drain electrode on the substrate;Step 4: Piezoelectric material layer, titanium nitride layer, ferroelectric material layer and tantalum nitride layer are sequentially formed on the high dielectric layer.
Preferably, the method that the silicon dioxide layer and high dielectric layer are formed in step 3 is atom deposition method.
Preferably, high dielectric layer in step 3, including HfO2、ZrO2、Ta2O5、TiO2In any one.
Preferably, the method that the piezoelectric material layer is formed in step 4 is atom deposition method.
Preferably, the method that the titanium nitride layer is formed in step 4 is physical vaporous deposition or atom deposition method.
Preferably, the method that the ferroelectric material layer is formed in step 4 is atom deposition method.
Preferably, the method that the tantalum nitride layer is formed in step 4 is physical vaporous deposition.
Preferably, piezoelectric material layer described in step 4 be electrostriction material, including aluminium nitride/gallium nitride, lead titanates, Any one in barium titanate, lead niobate.
As described above, iron of the invention/piezoelectricity field-effect tube and its preparation method, have the advantages that this hair It is bright to be intended to based on field effect transistor FET, introduce ferroelectric material and piezoelectric material in the gate, and with existing FET processing procedure into Row integration realizes the function of voltage amplification using the negative capacitance effect of ferroelectric material and the electrostriction effect of piezoelectric material jointly Energy.The operating voltage of device is reduced, subthreshold swing is reduced, improves the ON/OFF speed of device, further decrease operating power consumption.
Detailed description of the invention
Fig. 1 is shown as iron/piezoelectricity field-effect tube structural schematic diagram of the invention;
Fig. 2 is shown as iron/piezoelectricity field-effect tube preparation method flow chart of the invention.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Fig. 2.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout kenel may also be increasingly complex.
Fig. 1 is shown as iron/piezoelectricity field-effect tube structural schematic diagram of the invention.In the present embodiment preferably, the field Effect pipe is NMOS tube.The iron/piezoelectricity field-effect tube includes: substrate 01 in the present embodiment;Further, the substrate exists In the present embodiment be P-type substrate, that is to say, that the formation of the P-type substrate be by the injecting p-type ion in silicon materials plate, from And P-type substrate 01 as shown in Figure 1 is formed, therefore obtain the NMOS field-effect tube of the present embodiment.
The field-effect tube further includes the source electrode 021 and drain electrode 022 positioned at 01 two sides of substrate;It and further include being located at institute State the grid between 01 top of substrate, the source electrode 021 and drain electrode 022;As shown in Figure 1, the grid is in the present invention at least It include: the silicon dioxide layer 03 from bottom to top stacked gradually, high dielectric layer 04, piezoelectric material layer 05, titanium nitride layer 06, ferroelectricity material The bed of material 07 and tantalum nitride layer 08.That is, the silicon dioxide layer 03 is located at the institute between the source electrode 021 and drain electrode 022 01 upper surface of substrate is stated, is high dielectric layer 04 in the upper surface of the silicon dioxide layer 03, in the upper table of the high dielectric layer 04 Face is piezoelectric material layer 05, is titanium nitride layer 06 in the upper surface of the piezoelectric material layer 05, in the upper of the titanium nitride layer 06 Surface is ferroelectric material layer 07, is tantalum nitride layer 08 in the upper surface of the ferroelectric material layer 07, and the tantalum nitride layer 08 is constituted The top layer of the stepped construction.
Further, 04 material of high dielectric layer includes HfO2、ZrO2、Ta2O5、TiO2In any one.More into one Step, the piezoelectric material layer 05 in the present embodiment is electrostriction material, and piezoelectric material has electrostriction effect, in electricity Under the action of, material generates stress and is compressed, to change the conduction band structure of material internal, enhances charge density, to rise To the effect of voltage amplification.Piezoelectric material layer 05 described in the present embodiment includes aluminium nitride/gallium nitride, lead titanates, barium titanate, niobium Any one in lead plumbate.The ferroelectric material layer 07 in the present embodiment has negative capacitance effect, under the action of electric field, material The polarization direction of material can invert, to there is voltage amplification.Therefore, the present embodiment preferably, the ferroelectricity material The bed of material 07 includes HfO2、HfAlO2、HfZrO2In any one.
The present invention acts on the comprehensive magnification of voltage by ferroelectric material and piezoelectric material, can be effectively reduced work electricity Pressure, while the subthreshold swing of device is reduced to 60mV/decade hereinafter, reducing device uses power consumption.
The invention also includes the iron/piezoelectricity field-effect tube preparation methods, are shown as of the invention with reference to Fig. 2, Fig. 2 Iron/piezoelectricity field-effect tube preparation method flow chart.This method at least includes the following steps:
Step 1: providing silicon substrate, the doped p-type ion in the silicon substrate forms substrate 01;That is the P The formation of type substrate to form P-type substrate 01 as shown in Figure 1, therefore is obtained by the injecting p-type ion in silicon materials plate To the NMOS field-effect tube of the present embodiment.
Step 2: forming source electrode 021 and drain electrode 022 in the two sides of the substrate 01, the source electrode 021 and drain electrode 022 are made For the source electrode and drain electrode of NMOS field-effect tube;
Step 3: sequentially forming silicon dioxide layer 03 above the substrate 01, between the source electrode 021 and drain electrode 022 With high dielectric layer 04;In the present embodiment preferably, the method for the silicon dioxide layer 03 and high dielectric layer 04 is formed in step 3 To be formed using the method for atom deposition method.Further, high dielectric layer 04 includes HfO in step 32、ZrO2、Ta2O5、TiO2 In any one.High dielectric layer 04 described in the embodiment of the present invention iron/piezoelectricity field-effect tube preparation method is preferably HfO2
Step 4: sequentially forming piezoelectric material layer 05, titanium nitride layer 06, ferroelectric material layer 07 on the high dielectric layer 04 With tantalum nitride layer 08.That is, the silicon dioxide layer 03 is located at the substrate between the source electrode 021 and drain electrode 022 01 upper surface forms high dielectric layer 04 in the upper surface of the silicon dioxide layer 03, in the upper surface shape of the high dielectric layer 04 At piezoelectric material layer 05, piezoelectric material layer 05 described in the present embodiment is electrostriction material, and piezoelectric material has electrostriction Effect, under the action of electric field, material generates stress and is compressed, to change the conduction band structure of material internal, enhancing charge is close Degree, to play the role of voltage amplification.In the iron/piezoelectricity field-effect tube preparation method of the invention, the institute of step 4 Stating piezoelectric material layer is electrostriction material, including any one in aluminium nitride/gallium nitride, lead titanates, barium titanate, lead niobate Kind.Piezoelectric material layer 05 described in the step of the present embodiment four is aluminium nitride/gallium nitride or lead titanates.
Further, the method that the piezoelectric material layer 05 is formed in step 4 is atom deposition method (ALD).In the pressure The upper surface of material layer 05 forms titanium nitride layer 06, and the method that the titanium nitride layer is formed in step four of the invention is physics Vapour deposition process or atom deposition method.Further, the method for the titanium nitride layer 06 is formed in the step of the present embodiment four For physical vaporous deposition.Ferroelectric material layer 07 is formed in the upper surface of the titanium nitride layer 06, is preferably formed in the step The method of the ferroelectric material layer 07 is atom deposition method (ALD).Tantalum nitride is formed in the upper surface of the ferroelectric material layer 07 Layer 08, the tantalum nitride layer 08 are top layer.The method that the tantalum nitride layer 08 is formed in the step is physical vaporous deposition.This The ferroelectric material layer 07 in embodiment has negative capacitance effect, and under the action of electric field, the polarization direction of material can occur Reversion, to there is voltage amplification.Therefore, preferably, the ferroelectric material layer 07 is HfO to the present embodiment2
The method of the iron/piezoelectricity field-effect tube made above puts the synthesis of voltage by ferroelectric material and piezoelectric material Big effect, can be effectively reduced operating voltage, while the subthreshold swing of device is reduced to 60mV/decade hereinafter, drop Low device uses power consumption.
The present invention gives another embodiment about the iron/piezoelectricity field-effect tube preparation method, specifically includes following Step:
Iron/piezoelectricity field-effect tube preparation method flow chart of the invention is shown as with reference to Fig. 2, Fig. 2.This method is at least wrapped Include following steps:
Step 1: providing silicon substrate, the doped p-type ion in the silicon substrate forms substrate 01;That is the P The formation of type substrate to form P-type substrate 01 as shown in Figure 1, therefore is obtained by the injecting p-type ion in silicon materials plate To the NMOS field-effect tube of the present embodiment.
Step 2: forming source electrode 021 and drain electrode 022 in the two sides of the substrate 01, the source electrode 021 and drain electrode 022 are made For the source electrode and drain electrode of NMOS field-effect tube;
Step 3: sequentially forming silicon dioxide layer 03 above the substrate 01, between the source electrode 021 and drain electrode 022 With high dielectric layer 04;In the present embodiment preferably, the method for the silicon dioxide layer 03 and high dielectric layer 04 is formed in step 3 To be formed using the method for atom deposition method.Further, high dielectric layer 04 includes HfO in step 32、ZrO2、Ta2O5、TiO2 In any one.High dielectric layer 04 is ZrO in the step2Or Ta2O5
Step 4: sequentially forming piezoelectric material layer 05, titanium nitride layer 06, ferroelectric material layer 07 on the high dielectric layer 04 With tantalum nitride layer 08.That is, the silicon dioxide layer 03 is located at the substrate between the source electrode 021 and drain electrode 022 01 upper surface forms high dielectric layer 04 in the upper surface of the silicon dioxide layer 03, in the upper surface shape of the high dielectric layer 04 At piezoelectric material layer 05, piezoelectric material layer 05 described in the present embodiment is electrostriction material, and piezoelectric material has electrostriction Effect, under the action of electric field, material generates stress and is compressed, to change the conduction band structure of material internal, enhancing charge is close Degree, to play the role of voltage amplification.In the iron/piezoelectricity field-effect tube preparation method of the invention, the institute of step 4 Stating piezoelectric material layer is electrostriction material, including any one in aluminium nitride/gallium nitride, lead titanates, barium titanate, lead niobate Kind.Piezoelectric material layer 05 described in the step of the present embodiment four is barium titanate or lead niobate.
Further, the method that the piezoelectric material layer 05 is formed in step 4 is atom deposition method (ALD).In the pressure The upper surface of material layer 05 forms titanium nitride layer 06, and the method that the titanium nitride layer is formed in step four of the invention is physics Vapour deposition process or atom deposition method.Further, the method for the titanium nitride layer 06 is formed in the step of the present embodiment four For atom deposition method (ALD), which, which forms titanium nitride layer 06 using atom deposition method (ALD), keeps its consistency high, and defect is few, But also have process costs higher compared to other deposition techniques, the disadvantages of time-consuming.
Ferroelectric material layer 07 is formed in the upper surface of the titanium nitride layer 06, preferably forms the ferroelectricity material in the step The method of the bed of material 07 is atom deposition method (ALD).Tantalum nitride layer 08, the nitrogen are formed in the upper surface of the ferroelectric material layer 07 Change tantalum layer 08 is top layer.The method that the tantalum nitride layer 08 is formed in the step is physical vaporous deposition.In the present embodiment The ferroelectric material layer 07 has negative capacitance effect, and under the action of electric field, the polarization direction of material can be inverted, to have The effect of voltage amplification.Therefore, preferably, the ferroelectric material layer 07 is HfAlO to the present embodiment2Or HfZrO2.It is made above The iron/piezoelectricity field-effect tube method acts on the comprehensive magnification of voltage by ferroelectric material and piezoelectric material, can be effective Ground reduces operating voltage, while the subthreshold swing of device is reduced to 60mV/decade hereinafter, reducing device uses power consumption.
In conclusion ferroelectric material and piezoelectric material are introduced in the gate the present invention is based on field effect transistor FET, and It is integrated with existing FET processing procedure, is total to using the negative capacitance effect of ferroelectric material and the electrostriction effect of piezoelectric material With the function of realizing voltage amplification.The operating voltage of device is reduced, subthreshold swing is reduced, improves the ON/OFF speed of device, into One step reduces operating power consumption.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.

Claims (14)

1. a kind of iron/piezoelectricity field-effect tube, which is characterized in that include at least:
Substrate;
Source electrode and drain electrode positioned at the substrate two sides;
Grid above the substrate, between the source electrode and drain electrode;The grid includes: from bottom to top to stack gradually Silicon dioxide layer, high dielectric layer, piezoelectric material layer, titanium nitride layer, ferroelectric material layer and tantalum nitride layer.
2. iron according to claim 1/piezoelectricity field-effect tube, it is characterised in that: the substrate is P-type substrate.
3. iron according to claim 1/piezoelectricity field-effect tube, it is characterised in that: the high dielectric layer includes HfO2、ZrO2、 Ta2O5、TiO2In any one.
4. iron according to claim 1/piezoelectricity field-effect tube, it is characterised in that: the piezoelectric material layer is electrostriction Material, including any one in aluminium nitride/gallium nitride, lead titanates, barium titanate, lead niobate.
5. iron according to claim 1/piezoelectricity field-effect tube, it is characterised in that: the ferroelectric material layer includes HfO2、 HfAlO2、HfZrO2In any one.
6. iron according to claim 1/piezoelectricity field-effect tube preparation method, it is characterised in that: the field-effect tube is NMOS tube.
7. a kind of iron/piezoelectricity field-effect tube preparation method, which is characterized in that this method at least includes the following steps:
Step 1: providing silicon substrate, the doped p-type ion in the silicon substrate forms substrate;
Step 2: forming source electrode and drain electrode in the two sides of the substrate;
Step 3: sequentially forming silicon dioxide layer and high dielectric layer between side, the source electrode and drain electrode on the substrate;
Step 4: sequentially forming piezoelectric material layer, titanium nitride layer, ferroelectric material layer and tantalum nitride layer on the high dielectric layer.
8. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: form institute in step 3 The method for stating silicon dioxide layer and high dielectric layer is atom deposition method.
9. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: the high dielectric layer packet Include HfO2、ZrO2、Ta2O5、TiO2In any one.
10. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: form institute in step 4 The method for stating piezoelectric material layer is atom deposition method.
11. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: form institute in step 4 The method for stating titanium nitride layer is physical vaporous deposition or atom deposition method.
12. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: form institute in step 4 The method for stating ferroelectric material layer is atom deposition method.
13. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: form institute in step 4 The method for stating tantalum nitride layer is physical vaporous deposition.
14. iron according to claim 7/piezoelectricity field-effect tube preparation method, it is characterised in that: pressed described in step 4 Material layer is electrostriction material, including any one in aluminium nitride/gallium nitride, lead titanates, barium titanate, lead niobate.
CN201910159715.4A 2019-03-04 2019-03-04 A kind of iron/piezoelectricity field-effect tube and its preparation method Pending CN110034181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910159715.4A CN110034181A (en) 2019-03-04 2019-03-04 A kind of iron/piezoelectricity field-effect tube and its preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910159715.4A CN110034181A (en) 2019-03-04 2019-03-04 A kind of iron/piezoelectricity field-effect tube and its preparation method

Publications (1)

Publication Number Publication Date
CN110034181A true CN110034181A (en) 2019-07-19

Family

ID=67235720

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910159715.4A Pending CN110034181A (en) 2019-03-04 2019-03-04 A kind of iron/piezoelectricity field-effect tube and its preparation method

Country Status (1)

Country Link
CN (1) CN110034181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312829A (en) * 2019-11-11 2020-06-19 中国科学院上海技术物理研究所 High-sensitivity negative-capacitance field effect transistor photoelectric detector and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544093A (en) * 2010-12-09 2012-07-04 中国科学院物理研究所 Semiconductor field effect structure and preparation method and application thereof
US20120305891A1 (en) * 2011-06-03 2012-12-06 Nayfeh Osama M Graphene channel transistors and method for producing same
CN106057873A (en) * 2015-04-14 2016-10-26 财团法人交大思源基金会 Semiconductor device with a plurality of semiconductor chips
CN108288647A (en) * 2017-12-14 2018-07-17 中国科学院微电子研究所 Ring gate nano line field-effect transistor and preparation method thereof
US20180374962A1 (en) * 2017-06-22 2018-12-27 The Penn State Research Foundation Two-dimensional electrostrictive field effect transistor (2d-efet)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544093A (en) * 2010-12-09 2012-07-04 中国科学院物理研究所 Semiconductor field effect structure and preparation method and application thereof
US20120305891A1 (en) * 2011-06-03 2012-12-06 Nayfeh Osama M Graphene channel transistors and method for producing same
CN106057873A (en) * 2015-04-14 2016-10-26 财团法人交大思源基金会 Semiconductor device with a plurality of semiconductor chips
US20180374962A1 (en) * 2017-06-22 2018-12-27 The Penn State Research Foundation Two-dimensional electrostrictive field effect transistor (2d-efet)
CN108288647A (en) * 2017-12-14 2018-07-17 中国科学院微电子研究所 Ring gate nano line field-effect transistor and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312829A (en) * 2019-11-11 2020-06-19 中国科学院上海技术物理研究所 High-sensitivity negative-capacitance field effect transistor photoelectric detector and preparation method thereof
CN111312829B (en) * 2019-11-11 2023-07-04 中国科学院上海技术物理研究所 High-sensitivity negative capacitance field effect transistor photoelectric detector and preparation method thereof

Similar Documents

Publication Publication Date Title
TWI731863B (en) Oxide semiconductor transistor and manufacturing method thereof
US11701728B2 (en) Logic switching device and method of manufacturing the same
TW202027271A (en) Semiconductor device
US11749739B2 (en) Method of forming multiple-Vt FETS for CMOS circuit applications
CN106847918A (en) Ge field-effect transistors(FET)And manufacture method
CN109244073B (en) Semiconductor device structure and manufacturing method thereof
EP3996148A2 (en) Semiconductor device and semiconductor apparatus including the same
CN107845679A (en) A kind of ring grid field effect transistor based on negative capacitance and preparation method thereof
Lee et al. Hysteresis-Free Gate-All-Around Stacked Poly-Si Nanosheet Channel Ferroelectric Hf x Zr 1-x O 2 Negative Capacitance FETs With Internal Metal Gate and NH 3 Plasma Nitridation
CN110034181A (en) A kind of iron/piezoelectricity field-effect tube and its preparation method
US20240038891A1 (en) Electronic device and method of manufacturing the same
KR20200024067A (en) Logic switching device and method of manufacturing the same
CN109980013A (en) A kind of FinFET and preparation method thereof
TW201937745A (en) Method to fabricate capacitance-matching FET and related device
TWI686949B (en) Semiconductor device and the method of manufacturing the same
CN109216192A (en) Semiconductor devices and forming method thereof
KR20220060446A (en) Semiconductor device and semiconductor apparatus comprising the same
CN109727992B (en) Charge trapping memory and method of making the same
US20200328309A1 (en) Negative capacitance field effect transistor and method for manufacturing the same
JP2012080055A (en) Dielectric with praseodymium oxide, transistor including praseodymium oxide, and method of manufacturing the same
CN107591368A (en) Multi-Vt fin formula field effect transistor and forming method thereof
US11257950B2 (en) Semiconductor structure and manufacturing method for the semiconductor structure
TWI584482B (en) Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof
TW201338163A (en) FinFET and method of fabricating FinFET
CN115425074A (en) Ferroelectric negative capacitance field effect transistor and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190719

RJ01 Rejection of invention patent application after publication