KR20220060446A - Semiconductor device and semiconductor apparatus comprising the same - Google Patents

Abstract

A ferroelectric semiconductor device including ferroelectrics and having two or more electrode layers is provided. The semiconductor device may include a first electrode layer and a second electrode layer having a thermal expansion coefficient smaller than that of a ferroelectric layer. A difference in thermal expansion coefficient between the second electrode layer and the ferroelectric may be greater than a difference in thermal expansion coefficient between the first electrode layer and the ferroelectric. The second electrode layer may have a greater thickness than the first electrode layer.

Description

A semiconductor device and a semiconductor device including the same

It relates to a semiconductor device and a semiconductor device including the same.

A ferroelectric is a material having ferroelectricity that maintains spontaneous polarization by aligning electric dipole moments inside even when an external electric field is not applied. In other words, ferroelectrics are materials in which polarization (or electric field) remains semi-permanently in the material even when the voltage is brought back to 0V after applying a certain voltage. Research has been made to improve the performance of a semiconductor device by applying such a ferroelectric property to a semiconductor device. For example, research to apply the characteristic that the polarization value of a ferroelectric exhibits hysteresis with respect to a voltage change to a memory device has been conducted since the past.

In addition, recent ferroelectrics may have negative capacitance in a specific region, and when this is applied to a transistor, the subthreshold swing value can go down to 60 mV/dec or less, which is the theoretical limit value of existing silicon-based transistors. Research results have been published on the possibility that For this reason, research to utilize ferroelectrics in low-power semiconductor devices is being conducted.

In addition, since hafnium-based oxides have been found to have ferroelectric properties, research on the use of hafnium-based oxides in semiconductor devices has been conducted. Hafnium-based oxides are friendly to semiconductor processes and have ferroelectric properties even in very thin thin films of several nm, so it is expected to be useful for miniaturization of semiconductor devices.

One embodiment relates to a ferroelectric semiconductor device having an electrode structure of two or more layers.

Another embodiment relates to a ferroelectric semiconductor device having a low leakage current and a high dielectric constant.

Another embodiment relates to a semiconductor device having various threshold voltages (Vth).

A semiconductor device according to an aspect includes a substrate, a ferroelectric layer disposed parallel to the substrate, a first electrode layer spaced apart from the substrate and disposed on the ferroelectric layer, and a second electrode layer disposed on the first electrode, Both the first electrode layer and the second electrode layer may have a smaller coefficient of thermal expansion than that of the ferroelectric layer.

The difference between the coefficients of thermal expansion between the second electrode layer and the ferroelectric layer may be greater than the difference between the coefficients of thermal expansion between the first electrode layer and the ferroelectric layer. For example, the difference between the coefficients of thermal expansion between the second electrode layer and the ferroelectric layer may be 3.0x10 ^{-6 /K or more and 10.0x10 -6 /} K or less, and the difference between the thermal expansion coefficients of the first electrode layer and the ferroelectric layer is greater than 0.0, It may be 3.0x10 ^-6 /K or less.

The second electrode layer may have a greater thickness than the first electrode layer. For example, the thickness of the second electrode layer may be greater than or equal to 1.0 times and less than or equal to 30.0 times that of the first electrode layer. The first electrode layer may include TiN, and the second electrode layer may include Mo.

The ferroelectric layer may include a material represented by MO ₂ (where M is Hf, Zr, or a combination thereof). In addition, the ferroelectric layer further includes one or two or more dopant materials selected from the group consisting of Lu, Y, La, Ba and Sr, or is made of Al, Ti, Ta, Sc, and Mg. It may further include one or two or more dopant materials selected from the group.

A semiconductor device according to an aspect may include one or more semiconductor devices including the above-described ferroelectric layer. For example, the semiconductor device may include two or more semiconductor devices having different threshold voltages Vth. Specifically, the two or more semiconductor devices may have different compositions and thicknesses of the first electrode layer, the composition and thickness of the second electrode layer, and/or the composition and thickness of the ferroelectric layer.

A semiconductor device including a ferroelectric layer having a negative capacitance effect may be provided. A semiconductor device including an electrode structure capable of realizing a desired threshold voltage Vth while increasing the ferroelectricity of the ferroelectric layer may be provided. Such a semiconductor device may have a low leakage current value and a high dielectric constant, and may be applied to various electronic devices, electronic devices, electronic circuits, and the like.

1, 2, and 3 are schematic diagrams illustrating semiconductor devices (field effect transistors) according to example embodiments.
4A and 4B are schematic diagrams illustrating a semiconductor device (field effect transistor) according to another exemplary embodiment.
5A and 5B are schematic diagrams illustrating a semiconductor device (field effect transistor) according to still another exemplary embodiment.
6 is a schematic diagram illustrating a semiconductor device (capacitor) according to an exemplary embodiment.
7 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment.
8 is a schematic diagram illustrating a semiconductor device (a connection structure between a capacitor and a field effect transistor) according to another exemplary embodiment.
9 and 10 are conceptual diagrams schematically illustrating a device architecture applicable to an electronic device according to an exemplary embodiment.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the technical idea. What is described as "upper" or "upper" may include those directly above/below/left/right in contact as well as above/below/left/right in non-contact.

The singular expression includes the plural expression unless the context clearly dictates otherwise. Terms such as "comprises" or "have" are intended to indicate that the features, numbers, steps, operations, components, parts, components, materials, or combinations thereof described in the specification exist unless otherwise stated. , one or more other features, or numbers, steps, acts, elements, parts, components, materials, or combinations thereof, or combinations thereof, are not to be understood as precluding the possibility of addition.

Terms such as "first", "second", "third", etc. may be used to describe various elements, but are used only for the purpose of distinguishing one element from other elements, and the order of elements; The type and the like are not limited. In addition, terms such as “unit”, “means”, “module”, “unit” and the like mean a unit of a comprehensive configuration that processes at least one function or operation, which is implemented as hardware or software, or It can be implemented by a combination of and software.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the sizes (widths, thicknesses, etc. of layers, regions, etc.) of each component in the drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments.

According to one aspect, a semiconductor device including a ferroelectric layer and a semiconductor device including the same may be provided. The semiconductor device may be a memory device or a non-memory device, for example, a field effect transistor, a capacitor, or a combination thereof, but is not limited thereto. A semiconductor device may include a plurality of semiconductor devices, and may be used in various electronic devices. Such an electronic device may have advantages in terms of efficiency, speed, and power consumption compared to conventional devices.

1 and 2 are schematic diagrams schematically illustrating a field effect transistor according to an embodiment. 1 and 2 , the field effect transistors D10 and D20 include a substrate 100 including sources 120 and 121 and drains 130 and 131 , a gate electrode 300 disposed on the substrate 100 , and and a ferroelectric layer 200 disposed between the substrate 100 and the gate electrode 300 . The field effect transistor may be a logic switching device. A logic switching element is a concept in contrast to a memory element (memory transistor), and may have non-memory characteristics, and may be a non-memory ON/OFF switching element.

The substrate 100 may include a semiconductor material. For example, the substrate 100 may include Si, Ge, SiGe, a III-V semiconductor, or the like, and may be used after being modified in various forms such as silicon on insulator (SOI).

The substrate 100 may include sources 120 and 121 and drains 130 and 131 , and may include channels 110 and 111 electrically connected to the sources 120 and 121 and drains 130 and 131 . The sources 120 and 121 may be electrically connected or contacted with one end of the channels 110 and 111 , and the drains 130 and 131 may be electrically connected or contacted with the other end of the channels 110 and 111 .

Referring to FIG. 1 , the channel 110 may be defined as a substrate region between the source 120 and the drain 130 in the substrate 100 . The source 120 and the drain 130 may be formed by implanting impurities into different regions of the substrate 100 . In this case, the source 120 , the channel 110 , and the drain 130 may form a substrate material. It may be included as a base material.

Also, referring to FIG. 2 , the channel 111 may be implemented as a material layer (thin film) separate from the substrate region 101 . The material composition of the channel 111 may vary. For example, the channel 111 is formed of a semiconductor material such as Si, Ge, SiGe, III-V, etc., as well as an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, and a two-dimensional material. material) (2D material), quantum dots (quantum dots), organic semiconductors, and may include one or more from the group consisting of combinations thereof. For example, the oxide semiconductor may include InGaZnO, etc., the two-dimensional material may include transition metal dichalcogenide (TMD) or graphene, and the quantum dots may include colloidal QDs, nanocrystals, or the like. ) structure, and the like. In addition, the source 121 and the drain 131 may be formed of a conductive material, and for example, may each independently include a metal, a metal compound, or a conductive polymer.

The gate electrode 300 may be disposed on the substrate 100 to be spaced apart from the substrate 100 , and may be disposed to face the channels 110 and 111 .

The ferroelectric layer 200 may be disposed on the channels 110 and 111 between the substrate 100 and the gate electrode 300 . The ferroelectric layer 200 may constitute a gate stack together with the gate electrode 300 .

As described above, ferroelectronics may have negative capacitance in a specific operating region, so that when applied to a gate stack of a field effect transistor, the sub-threshold swing value SS may be lowered.

Such a field effect transistor may be manufactured by forming an amorphous layer having the same composition as that of the ferroelectric layer 200 on the substrate 100 , sequentially forming the gate electrode 300 thereon, and annealing them together. As the amorphous layer is crystallized in the annealing step, the ferroelectricity of the crystallized layer may be increased by tensile stress between the amorphous layer and the gate electrode 300 .

Meanwhile, in recent electronic devices, one semiconductor device is required to have various threshold voltages (Vth) in order to be applied to various applications. In other words, a plurality of semiconductor devices included in one semiconductor device may not all have the same threshold voltage Vth, and at least two semiconductor devices may be required to have different threshold voltages Vth. The threshold voltage Vth of the semiconductor devices D10 and D20 is determined by the composition of the ferroelectric layer 200 , the work function of the gate electrode 300 , and other constituent elements (eg, another dielectric layer (reference numeral 300 in FIG. 3 ). ) may depend on the composition of the

According to an embodiment, the structure of the gate electrode 300 capable of realizing a desired threshold voltage Vth while increasing the ferroelectricity of the ferroelectric layer may be provided. Specifically, the ferroelectric semiconductor devices D10 and D20 are gate electrodes 300 , and may include a first electrode layer 310 and a second electrode layer 320 having different coefficients of thermal expansion and thickness.

Both the first electrode layer 310 and the second electrode layer 320 may have a smaller coefficient of thermal expansion than that of the ferroelectric layer 200 . The difference in the coefficient of thermal expansion increases the tensile stress applied to the amorphous layer during the semiconductor device manufacturing process, thereby increasing the ferroelectricity of the ferroelectric layer 200 .

Also, the first electrode layer 310 disposed adjacent to the ferroelectric layer 200 may include a material having a work function corresponding to the threshold voltage Vth of the semiconductor devices D10 and D20 .

The first electrode layer 310 and the second electrode layer 320 may be disposed such that a difference in coefficient of thermal expansion with the ferroelectric layer 200 increases as the distance from the ferroelectric layer 200 increases. For example, the difference in the coefficient of thermal expansion between the second electrode layer 320 and the ferroelectric layer 200 may be greater than the difference in the coefficient of thermal expansion between the first electrode layer 310 and the ferroelectric layer 200 . In addition, the thickness of the first electrode layer 310 and the second electrode layer 320 may increase as the distance from the ferroelectric layer 200 increases. In other words, the thickness of the second electrode layer 320 may be greater than the thickness of the first electrode layer 310 . The gate electrode 300 may implement a desired threshold voltage Vth from a difference in work function on the surface of the ferroelectric layer 200 , and increase the tensile stress applied to the entire ferroelectric layer 200 to improve ferroelectricity.

For example, the difference in coefficients of thermal expansion between the second electrode layer 320 and the ferroelectric layer 200 is 3.0x10 ^-6 /K or more, 3.1x10 ^-6 /K or more, 3.2x10 ^-6 /K or more, and 3.5x10 ^-6 /K or more, 4.0x10 ^-6 /K or more, 4.5x10 ^-6 /K or more, 5.0x10 ^-6 /K or more, 5.5x10 ^-6 /K or more, 6.0x10 ^-6 /K or more, 10.0x10 ^-6 /K or more or less, 9.5x10 -6 /K or less, 9.0x10 ^{-6 /K or less, 8.5x10 -6 /K or less, 8.0x10 -6 /K or less, 7.7x10 -6 / K or less} , or 7.5x10 ^-6 /K or less can The difference between the coefficients of thermal expansion of the first electrode layer 310 and the ferroelectric layer 200 is greater than 0.0, 0.5x10 ^-6 /K or more, 1.0x10 ^-6 /K or more, 1.5x10 ^-6 /K or more, 2.0x10 ^-6 /K or more K or more, 3.0x10 ^-6 /K or less, 3.0x10 ^{-6 /K or less, 2.9x10 -6 /} K or less, or 2.8x10 ^-6 /K or less. The first electrode layer 310 and the second electrode layer 320 may both have a coefficient of thermal expansion greater than 0.0 and less than or equal to 12.0x10 ^-6 /K, and the coefficient of thermal expansion of the second electrode layer 320 may be less than or equal to 9.0x10 ^-6 /K. , 8.5x10 ^-6 /K or less, 8.0x10 ^-6 /K or less, 7.5.0x10 ^-6 /K or less, 7.0x10 ^{-6 /K or less, 6.5.0x10 -6 /K or less, 6.0x10 -6 / K} or less , 5.5.0x10 ^-6 /K or less, or 5.0x10 ^-6 /K or less, and the coefficient of thermal expansion of the first electrode layer 310 is less than 12.0x10 ^-6 /K, 11.0x10 ^-6 /K or less, 10.0x10 ^-6 /K or less, 9.8x10 ^-6 /K or less, 9.6x10 ^-6 /K or less, 6.0x10 ^-6 /K or more, 6.3x10 ^-6 /K or more, 6.5x10 ^-6 /K or more, 7.0x10 ^-6 /K or more or more, or 7.5x10 ^-6 /K or more.

In addition, the thickness of the second electrode layer 320 is 1.0 times or more, , 1.5 times or more, 2.0 times or more, 2.5 times or more, 3.0 times or more, 5.0 times or more, 7.0 times or more, 10.0 times or more of the first electrode layer 310 . , 30.0 times or less, 27.0 times or less, 25.0 times or less, 23.0 times or less, or 20.0 times or less, and the second electrode layer 320 is 10 nm or more, 15 nm or more, 20 nm or more, 25 nm or more, 30 nm or more, 35 nm or more, 200 nm or more. It may have a thickness of 170 nm or less, 160 nm or less, 150 nm or less, 140 nm or less, 130 nm or less, 120 nm or less, 110 nm or less, or 100 nm or less, and the first electrode layer 310 is 1.0 nm or more, 1.5 nm or more, 2.0 nm or less. or more, 2.5 nm or more, 3.0 nm or more, 10.0 nm or less, 9.0 nm or less, 8.0 nm or less, or 7.0 nm or less.

The first electrode layer 310 and the second electrode layer 320 may have different compositions, and may each independently include one or two or more materials selected from the group consisting of Pt, Nb, Ru, Mo, W, and TiN. For example, the first electrode layer 310 may include TiN, and the second electrode layer 320 may include Mo.

Referring back to FIGS. 1 and 2 , the ferroelectric layer 200 may include a material expressed as MO ₂ (where M is Hf _, Zr or a combination thereof). These metal oxides can exhibit ferroelectricity even in very thin thin films of several nm level, and can be applied to the existing silicon-based semiconductor device process, so the mass productivity is high.

Also, the ferroelectric layer 200 may include an orthorhombic crystal phase. For example, the ferroelectric layer 200 may include several crystalline phases, such as an orthorhombic crystalline phase and an tetragonal crystalline phase, but may include an orthorhombic crystalline phase dominantly or in the largest proportion among all crystalline phases.

The ferroelectric layer 200 may be classified into a high dielectric according to the presence and/or size of residual polarization, a composition of a metal oxide, a type and ratio of a doping element, a crystal phase, and the like. The type and content of each element may be measured according to methods known in the art, for example, X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), inductively coupled plasma (ICP), etc. may be used. . In addition, the crystalline phase distribution may be confirmed by a method known in the art, for example, TEM (Transmission electron microscopy), GIXRD (Grazing Incidence X-ray Diffraction), etc. may be used.

The ferroelectric layer 200 includes a material expressed as MO ₂ (where M is Hf _, Zr or a combination thereof) as a base material, and includes C, Si, Ge, Sn, Pb, Al, Y , La, Gd, Mg, Ca, Sr Ba, Ti, Sc, Ta, Lu, and may further include a dopant material selected from the group consisting of one or two or more dopant materials (dopant material). The dopant material content is greater than 0at%, greater than 0.2at%, greater than 0.5at%, greater than 1at%, greater than 2at%, greater than 3 at%, less than 20at%, less than 15at%, less than 12at%, less than 10at compared to the metal element of the base material % or less, 8at% or less, 7at% or less, 6at% or less.

In addition, the ferroelectric layer 200 may control the type and content of the dopant in order to control the threshold voltage Vth of the semiconductor device. For example, in order to lower the threshold voltage (Vth) of the semiconductor device, the ferroelectric layer 200 includes one or more dopant materials selected from the group consisting of Al, Ti, Ta, Sc, and Mg. In order to further include or increase the threshold voltage (Vth) of the semiconductor device, the ferroelectric layer 200 includes one or more dopant materials selected from the group consisting of Lu, Y, La, Ba, and Sr. It may include more.

The ferroelectric layer 200 may have a thickness greater than 0 and less than or equal to 20 nm. For example, the thickness of the ferroelectric layer 200 is greater than 0 nm, greater than 0.1 nm, greater than 0.2 nm, greater than 0.3 nm, greater than 0.4 nm, greater than 0.5 nm, greater than 0.6 nm, greater than 0.7 nm, greater than 0.8 nm, greater than 1.0 nm , or 1.5 nm or more, 20 nm or less, 18 nm or less, 15 nm or less, 12 nm or less, 10 nm or less, 8 nm or less, 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, 1 nm or less. The thickness may be measured according to a method known in the art, for example, an ellipsometer (SE MG-1000, Nano View) may be used.

3 is a schematic diagram illustrating a semiconductor device (D30, field effect transistor) according to another exemplary embodiment. Referring to FIG. 3 , a dielectric layer 400 may be further included between the channel 110 and the ferroelectric layer 200 . The dielectric layer 400 may suppress or prevent electrical leakage. The thickness of the dielectric layer 400 may be 0.1 nm or more, 0.3 nm or more, or 0.5 nm or more, and may be 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, or 1 nm or less. The dielectric layer 400 may include a paraelectric material or a high-k material, and may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or the like, or a two-dimensional insulator (2D) such as hexagonal boron nitride (h-BN). insulator) may be included. For example, the dielectric layer 400 may include silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), or the like. In addition, the dielectric layer 400 is hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide ( ZrSiO ₄ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), red scandium tantalum oxide (PbSc _0.5 Ta _0.5 O ₃ ), red zinc niobate (PbZnNbO ₃ ), and the like. In addition, the dielectric layer 400 may be formed of a metal such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), or the like. Nitride oxides, silicates such as ZrSiON, HfSiON, YSiON, LaSiON, or the like, or aluminates such as ZrAlON, HfAlON, and the like.

Referring to FIG. 3 , a conductive layer 500 may be further included between the channel 110 and the ferroelectric layer 200 . The conductive layer 500 may have a conductivity of about 1 Mohm/square or less. The conductive layer 500 may be a floating electrode, and may be formed of a metal or a metal compound.

The field effect transistor may be implemented in various forms, such as 2-dimension and 3-dimension. For example, the field effect transistor may have a 1-gate on channel type like a planar-FET, a 3-gate on channel type like a Fin-FET, or a 4-gate on channel type like a Gate-all-around-FET. there is.

4A is a schematic diagram showing a semiconductor device (specifically, a Fin-FET) according to another embodiment, and FIG. 4B is a cross-sectional view taken along line A-A' of FIG. 4A. 4A and 4B , the Fin-FET D40 includes a source 120 , a drain 130 , and a channel 110 or 111 defined by a region therebetween, and the channels 110 and 111 are fin may have a shape. The gate electrode 300 may be disposed on the substrate 100 including the fin shape to intersect the fin shape, and the first electrode layer 310 and the second electrode layer 320 are formed on the channel 110 or 111 on the channel 110 . Or 111) may be arranged to surround sequentially.

5A is a schematic diagram showing a semiconductor device (specifically, a gate-all-around-FET) according to another embodiment, and FIG. 5B is a cross-sectional view taken along line B-B' of FIG. 5A. 5A and 5B , the gate-all-around-FET D50 includes a source 120, a drain 130, and a channel 110 or 111 defined by a region between them, and the channel ( 110 and 111) may have the form of a wire, a sheet, or the like. The source 120 , the drain 130 , and the channels 110 and 111 may be disposed to be spaced apart from the substrate region 101 . The gate electrode 300 intersects the source 120, the drain 130, and the channel 110 or 111, and the first electrode layer 310 and the second electrode layer 320 are formed on the channel 110 or 111 with the channel ( 110 or 111) may be arranged to sequentially surround

6 is a schematic diagram schematically illustrating a capacitor according to an embodiment. Referring to FIG. 6 , the capacitor D60 includes a first electrode 301 , a second electrode 302 opposite to and spaced apart from the first electrode 301 , and a ferroelectric capacitor disposed between the first electrode 301 and the second electrode 302 . layer 200 . The first electrode 301 and the second electrode 302 may be referred to as a lower electrode and an upper electrode, respectively, and may have first electrode layers 311 and 312 and second electrode layers 312 and 322 , respectively. The first electrode layers 311 and 312 may be disposed adjacent to the ferroelectric layer 200 to be parallel to the ferroelectric layer 200 .

In the semiconductor device (eg, capacitor) according to an embodiment, an amorphous layer having the same composition as that of the ferroelectric layer 200 is formed on the first electrode 301 including a semiconductor material, and the first electrode layer 312 . It may be manufactured by sequentially forming and annealing the second electrode layer 322 at the same time. During annealing, the amorphous layer may be crystallized by tensile stress between the second electrode 302 and the amorphous layer to become the ferroelectric layer 200 . The amorphous layer, the first electrode layer 312 , and the second electrode layer 322 are formed by a conventional method known in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. can be Among them, the atomic layer deposition (ALD) method has an advantage that it can form a uniform layer in atomic units and can be performed at a relatively low temperature.

When an amorphous layer is formed through an atomic layer deposition (ALD) method, a hafnium source, a zirconium source, and an oxygen source may be conventional precursors known in the art. For example, the hafnium source is Hf (OtBu) ₄ , TEMAH (Tetrakis Ethyl Methyl Amino Hafnium), TDMAH (Tetrakis Di-Methyl Amino Hafnium), TDEAH (Tetrakis Di-Ethyl Amino Hafnium), and combinations thereof. At least one selected may be used, but is not limited thereto. In addition, as the zirconium source, Zr(OtBu) ₄ , Tetrakis Ethyl Methyl Amino Zirconium (TEMAZ), Tetrakis Di-Methyl Amino Zirconium (TDMAZ), Tetrakis Di-Ethyl Amino Zirconium (TDEAZ), and combinations thereof are selected from the group consisting of At least one may be used, but is not limited thereto. In addition, as the oxygen source, O ₃ , H ₂ O, O ₂ , N ₂ O, O ₂ At least one selected from the group consisting of plasma and combinations thereof may be used, but is not limited thereto.

The step of annealing may be performed under suitable conditions in which the amorphous layer can be converted into a ferroelectric layer. Specifically, the amorphous layer may be performed under conditions in which crystallization into an orthorhombic crystalline phase is possible. For example, the annealing may be performed at a temperature of 400° C. to 1100° C., but is not limited thereto. Annealing is 1 nano-second or more, 1 micro-second or more, 0.001 sec or more, 0.01 sec or more, 0.05 sec or more, 0.1 sec or more, 0.5 sec or more, 1 sec or more, 3 sec or more, or It is 5 seconds or more, and may be performed for a time of 10 minutes or less, 5 minutes or less, 1 minute or less, or 30 seconds or less, but is not limited thereto.

In addition, when manufacturing the field effect transistor, the step of forming a dielectric layer on the substrate including the semiconductor material may be further included, and the step of forming the source and the drain on the substrate including the semiconductor material may be further included.

The capacitor may be manufactured in a manner similar to the manufacturing method of the field effect transistor described above, except that a structure in which the second electrode layer and the first electrode layer are sequentially stacked is used instead of the semiconductor substrate.

A semiconductor device includes a plurality of semiconductor devices, and one or more of the semiconductor devices may include the aforementioned semiconductor device (capacitor, field effect transistor). For example, a semiconductor device may include a plurality of the aforementioned field effect transistors, and two or more of them may have different threshold voltages Vth. Referring to FIG. 7 , the semiconductor device D70 may include a first field effect transistor D10a and a second field effect transistor D10b on a semiconductor substrate 100 . The first field effect transistor D10a and the second field effect transistor D10b have the composition and thickness of the first electrode layers 310a and 310b, the second electrode layers 320a and 320b, and/or the ferroelectric layers 200a and 200b. etc. may be different. Specifically, the two or more field effect transistors D10a and D10b may have different compositions and/or thicknesses of the gate electrodes 300a and 300b. For example, the first electrode layer 310a of the first field effect transistor D10a may include TiN, and the first electrode layer 310b of the second field effect transistor D10b may include W. Alternatively, the first electrode layers 310a and 310b of the first field effect transistor D10a and the second field effect transistor D10b may include TiN having different thicknesses. In addition, the second electrode layer 320a of the first field effect transistor D10a may include W, and the second electrode layer 320b of the second field effect transistor D10b may include Mo. Alternatively, the second electrode layers 320a and 320b of the first field effect transistor D10a and the second field effect transistor D10b may include Mo having different thicknesses. In addition, the two or more field effect transistors D10a and D10b may have different compositions and/or thicknesses of the ferroelectric layers 200a and 200b. Specifically, the ferroelectric layers 200a and 200b of the first field effect transistor D10a and the second field effect transistor D10b are made of a material represented by MO ₂ (where M is Hf, Zr, or a combination thereof). While being included as a base material, different dopant materials may be included. For example, the ferroelectric layer 200a of the first field effect transistor D10a further includes one or two or more dopant materials selected from the group consisting of Al, Ti, Ta, Sc, and Mg. In addition, the ferroelectric layer 200b of the second field effect transistor D10b may further include at least one dopant material selected from the group consisting of Lu, Y, La, Ba, and Sr.

The semiconductor device may be configured by electrically connecting a field effect transistor and a capacitor. The semiconductor device may have a memory characteristic, and may be, for example, a DRAM. 8 is a schematic diagram illustrating a semiconductor device (a connection structure between a capacitor and a field effect transistor) according to an exemplary embodiment. These capacitors and/or field effect transistors may be semiconductor devices according to an embodiment. Referring to FIG. 8 , the semiconductor device D80 may have a structure in which a capacitor D60 and a field effect transistor D10 ′ are electrically connected by a contact 62 according to an exemplary embodiment. For example, one of the electrodes 301.302 of the capacitor D60 and one of the sources/drains 120 and 130 of the transistor D10 ′ may be electrically connected by a contact 62 . Contact 62 may comprise a suitable conductive material, for example, tungsten, copper, aluminum, polysilicon, or the like.

The field effect transistor D10 ′ includes a substrate 100 including a source 120 , a drain 130 , and a channel 110 , and a gate electrode 300 ′ disposed to face the channel 110 . . A dielectric layer 410 may be further included between the substrate 100 and the gate electrode 300 ′. The source 120 , the drain 130 , the channel 110 , and the substrate 100 are the same as those described above, and the dielectric layer 410 may refer to the contents of the dielectric layer 400 described above. The gate electrode 300 ′ may or may not include the first electrode layer 310 and the second electrode layer 320 as shown in FIG. 1 . In addition, although an example in which the field effect transistor D10 ′ does not include the ferroelectric layer 200 is illustrated, it may include the ferroelectric layer 200 as shown in FIG. 1 .

The arrangement of the capacitor D60 and the field effect transistor D10' may be variously modified. For example, the capacitor D60 may be disposed on the substrate 100 or may have a structure embedded in the substrate 100 .

A semiconductor device and a semiconductor device may be applied to various electronic devices. Specifically, the above-described field effect transistor, capacitor, or a combination thereof may be applied as a logic element or a memory element in various electronic devices. The semiconductor device according to the embodiments may be driven with low power, and thus may meet demands for miniaturization and integration of electronic devices. Specifically, semiconductor devices and semiconductor devices may be used for arithmetic operations, program execution, temporary data retention, etc. in electronic devices such as mobile devices, computers, notebook computers, sensors, network devices, and neuromorphic devices. The semiconductor device and the semiconductor device according to the embodiments may be useful for electronic devices in which a data transmission amount is large and data transmission is continuously performed.

9 and 10 are conceptual views schematically illustrating an electronic device architecture applicable to an electronic device according to an exemplary embodiment.

Referring to FIG. 9 , an electronic device architecture 1000 may include a memory unit 1010 , an arithmetic logic unit (ALU) 1020 , and a control unit 1030 . . The memory unit 1010 , the ALU 1020 , and the control unit 1030 may be electrically connected. For example, the electronic device architecture 1000 may be implemented as one chip including the memory unit 1010 , the ALU 1020 , and the control unit 1030 . Specifically, the memory unit 1010 , the ALU 1020 , and the control unit 1030 may be interconnected through a metal line in an on-chip to directly communicate with each other. The memory unit 1010 , the ALU 1020 , and the control unit 1030 may be monolithically integrated on one substrate to constitute one chip. The input/output device 2000 may be connected to the electronic device architecture (chip) 1000 .

The memory unit 1010 , the ALU 1020 , and the control unit 1030 may each independently include the above-described semiconductor device (eg, a field effect transistor or a capacitor). For example, the ALU 1020 and the control unit 1030 may each independently include the aforementioned field effect transistors, and the memory unit 1010 may include the aforementioned capacitors, field effect transistors, or a combination thereof. may include The memory unit 1010 may include both a main memory and a cache memory. The electronic device architecture (chip) 1000 may be an on-chip memory processing unit.

Referring to FIG. 10 , a cache memory 1510 , an ALU 1520 , and a control unit 1530 may constitute a Central Processing Unit (CPU) 1500 . The cache memory 1510 may be formed of a static random access memory (SRAM) and may include the aforementioned field effect transistor. Separately from the CPU 1500 , a main memory 1600 and an auxiliary storage 1700 may be provided. The main memory 1600 is formed of dynamic random access memory (DRAM) and may include the aforementioned capacitor.

In some cases, the electronic device architecture may be implemented in a form in which computing unit devices and memory unit devices are adjacent to each other in a single chip without distinction of sub-units.

Hereinafter, specific embodiments including the above-described semiconductor devices are presented.

Example 1: p-Si/SiO ₂ / HfZrO/ TiN/ Mo structure capacitor manufacturing

A polysilicon (p-Si) substrate was prepared, and the surface was partially oxidized to form a silicon oxide layer (SiO ₂ ).

On the silicon oxide layer (SiO ₂ ), an HfZrO amorphous layer was formed through atomic layer deposition (ALD). A TiN electrode and a Mo electrode were sequentially formed on the HfZrO amorphous layer through DC sputtering or ALD. The thickness of the TiN electrode is about 5 nm, and the thickness of the Mo electrode is about 100 nm.

The structure thus formed was subjected to rapid thermal annealing (RTA) at a temperature between 400° C. and 1100° C. to prepare a capacitor including a crystallized HfZrO layer.

Example 2: p-Si/SiO ₂ / La-HfZrO/ TiN/ Mo structure capacitor manufacturing

A capacitor was manufactured in the same manner as in Example 1, except that an HfZrO amorphous layer containing La as a dopant material was formed on the silicon oxide layer (SiO ₂ ) through atomic layer deposition (ALD) instead of the HfZrO amorphous layer. .

Example 3: p-Si/SiO ₂ / HfO/ TiN/ Mo structure capacitor manufacturing

A capacitor was manufactured in the same manner as in Example 1, except that an HfO amorphous layer was formed through atomic layer deposition (ALD) instead of an HfZrO amorphous layer on a silicon oxide layer (SiO ₂ ).

Example 4: Fabrication of Capacitors of Mo/ TiN/ HfZrO/ TiN/ Mo Structure

A Mo electrode and a TiN electrode were sequentially formed through DC sputtering or ALD method.

A HfZrO amorphous layer was formed on the Mo electrode through atomic layer deposition (ALD). A TiN electrode and a Mo electrode were sequentially formed on the HfZrO amorphous layer through DC sputtering or ALD.

The structure thus formed was subjected to rapid thermal annealing (RTA) at a temperature between 400° C. and 1100° C. to prepare a capacitor including a crystallized HfZrO layer.

Comparative Example 1: p-Si/SiO ₂ / HfZrO/ Mo structure capacitor manufacturing

A capacitor was manufactured in the same manner as in Example 1, except that a Mo electrode was formed on the HfZrO amorphous layer without forming a TiN electrode.

Comparative Example 2: p-Si/SiO ₂ / La-HfZrO/ Mo structure capacitor manufacturing

A capacitor was manufactured in the same manner as in Example 2, except that a Mo electrode was formed without forming a TiN electrode on the HfZrO amorphous layer containing La as a dopant material.

Comparative Example 3: TiN/HfZrO/TiN Structure Capacitor Manufacturing

A capacitor was manufactured in the same manner as in Example 4, except that the Mo electrode was not formed and only the TiN electrode was formed before and after the formation of the HfZrO amorphous layer.

Electrical Characteristics 1

The polarization versus electric field hysteresis curves (P-E hysteresis curves) of the capacitors of Examples 1, 2, 4, and Comparative Examples 1 to 2 were measured, and the residual polarization values are shown in Table 1 below. Referring to Table 1, the capacitors of Examples 1 and 2 having a TiN/Mo two-layer electrode structure have higher residual polarization values than Comparative Examples 1 and 2 having a Mo single-layer electrode structure. In addition, the capacitor of Example 4 having a TiN/Mo two-layer electrode structure has a higher residual polarization value than Comparative Example 3 having a TiN single-layer electrode structure. From this, it was confirmed that the capacitor having a two-layer electrode structure according to the embodiments has substantially increased ferroelectricity.

ferroelectric layer electrode residual polarization
(μC/cm ² ) Example 1 HfZrO TiN/Mo 14 Example 2 La-HfZrO TiN/Mo 16 Comparative Example 1 HfZrO Mo 8.3 Comparative Example 2 La-HfZrO Mo 9 Example 4 HfZrO TiN/Mo 15 Comparative Example 3 HfZrO TiN 7.24

Electrical Characteristics 2 Table 2 shows the flat-band voltage (V _FB , flat-band voltage), equivalent oxide thickness (EOT), and leakage current values of the capacitors of Examples 1 to 3 and Comparative Example 2. Referring to Table 2, it was confirmed that the capacitors of Examples 1 to 3 and Comparative Example 2 had different planarization voltages (V _FB ). Since the planarization voltage (V _FB ) is a factor that directly affects the threshold voltage (Vth) of the semiconductor device, various threshold voltages (Vth) are obtained by changing the electrode structure and/or the composition of the ferroelectric layer as in Examples 1 to 3 It can be seen that this can be implemented.

In addition, it was confirmed that the capacitors of Examples 1 to 3 having a TiN/Mo two-layer electrode structure had lower EOT and lower leakage current values compared to Comparative Example 2 having a Mo single-layer electrode structure.

For reference, it is known that a metal-oxide-silicon (MOS) capacitor as in the embodiment/comparative example has a structure similar to that of a field effect transistor, and the performance of a metal-oxide-silicon (MOS) capacitor corresponds to the performance of a field effect transistor. there is.

ferroelectric layer electrode flattening voltage
(V) EOT
(nm) leakage current
(A/cm ² @1V) Example 1 HfZrO TiN/Mo 0.064 0.73 0.049 Example 2 La-HfZrO TiN/Mo 0.005 0.69 0.074 Example 3 HfO TiN/Mo 0.092 0.75 0.067 Comparative Example 2 La-HfZrO Mo -0.144 0.86 0.248

Although the embodiments have been described in detail above, the scope of the rights is not limited thereto, and various modifications and improved forms of those skilled in the art using the basic concepts defined in the following claims also belong to the scope of the rights.

D10 to D50 semiconductor device D70, D80 semiconductor device
100 substrate 200 ferroelectric layer
300, gate electrode, 300a, 300b, 301, 302 electrode
310, 310a, 310b, 311, 312 first electrode layer
320, 320a, 320b, 321, 322 second electrode layer
400, 410 dielectric layer 500 conductor layer

Claims (20)

Board;
a ferroelectric layer disposed parallel to the substrate;
a first electrode layer spaced apart from the substrate and disposed on the ferroelectric layer; and
a second electrode layer disposed on the first electrode layer;
The first electrode layer and the second electrode layer both have a coefficient of thermal expansion smaller than that of the ferroelectric layer, and the difference between the coefficients of thermal expansion between the second electrode layer and the ferroelectric is greater than the difference between the coefficients of thermal expansion between the first electrode layer and the ferroelectric,
The thickness of the second electrode layer is greater than the thickness of the first electrode layer. According to claim 1,
The difference between the coefficient of thermal expansion between the second electrode layer and the ferroelectric is 3.0x10 ^-6 /K or more and 10.0x10 ^-6 /K or less. According to claim 1,
The difference between the coefficient of thermal expansion of the first electrode layer and the ferroelectric is greater than 0.0 and less than or equal to 3.0 x 10 ^-6 /K. According to claim 1,
The first electrode layer and the second electrode layer are each independently Pt, Nb, Ru, Mo, a semiconductor device comprising at least one material selected from the group consisting of W and TiN. According to claim 1,
A semiconductor device in which the first electrode layer includes TiN and the second electrode layer includes Mo. According to claim 1,
The thickness of the second electrode layer is greater than 1.0 times and less than or equal to 30.0 times that of the first electrode layer. According to claim 1,
The thickness of the second electrode layer is 10 nm or more and 200 nm or less. According to claim 1,
The thickness of the first electrode layer is 1.0 nm or more and 10.0 nm or less. The method of claim 1,
The ferroelectric layer is a semiconductor device including a material represented by MO ₂ (where M is Hf _, Zr or a combination thereof). 10. The method of claim 9,
The ferroelectric layer includes a material represented by MO ₂ (where M is Hf _, Zr or a combination thereof) as a base material,
A semiconductor device further comprising at least one dopant material selected from the group consisting of Lu, Y, La, Ba and Sr. 11. The method of claim 10,
The ferroelectric layer is a semiconductor device in which the content of the dopant material is greater than 0 at% and less than or equal to 20 at% compared to the metal element of the base material. The method according to claim 9,
The ferroelectric layer includes a material represented by MO ₂ (where M is Hf _, Zr or a combination thereof) as a base material,
A semiconductor device further comprising at least one dopant material selected from the group consisting of Al, Ti, Ta, Sc, and Mg. 13. The method of claim 12,
The ferroelectric layer is a semiconductor device in which the content of the dopant material is greater than 0 at% and less than or equal to 20 at% compared to the metal element of the base material. The method of claim 1,
The substrate is a semiconductor device comprising a semiconductor material. The method of claim 1,
A semiconductor device further comprising a paraelectric material between the substrate and the ferroelectric layer. 16. The method of claim 15,
The paraelectric material is at least one selected from the group consisting of aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), silicon oxide (SiO ₂ ), and combinations thereof A semiconductor device that becomes A semiconductor device comprising the semiconductor element according to any one of claims 1 to 16. 18. The method of claim 17,
comprising two or more semiconductor devices,
The two or more semiconductor devices have different threshold voltages (Vth). 19. The method of claim 18,
The two or more semiconductor devices have a composition, a thickness, or both of the first electrode layer different from each other.
At least one of the first electrode layer, the second electrode layer, and the ferroelectric layer corresponding to the two or more semiconductor devices,
A semiconductor device having at least one of a composition and a thickness different from each other. 20. The method of claim 19,
of the two or more semiconductor devices
One semiconductor device includes a ferroelectric layer further comprising at least one dopant material selected from the group consisting of Al, Ti, Ta, Sc, and Mg,
The other semiconductor device includes a ferroelectric layer further comprising a dopant material selected from the group consisting of Lu, Y, La, Ba, and Sr.

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