TWI584482B - Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents

Description

Complementary MOS half-field effect transistor structure, gold oxide half field effect transistor structure and Production Method

The invention relates to a complementary metal oxide half field effect transistor structure, in particular to a multi-gate metal oxide semiconductor field effect transistor (multi-gate MOSFET) structure and a manufacturing method thereof .

At present, the gold oxide half field effect transistor (MOSFET) is used as the main component for constructing a very large integrated circuit. Over the past few decades, as MOSFETs have continued to shrink in size, significant improvements have been made in component speed, performance, circuit density, or unit size. For a typical planar transistor component, the source/drain on both sides can adversely affect the carrier channel due to the continued reduction of the gate length and may change the channel potential. In such a case, the gate will not be able to effectively control the on/off of the carrier channel, which in turn affects the performance of the component. This phenomenon is also known as "short-channel effects" (SCE).

In order to suppress the occurrence of short-channel effects, various corresponding solutions have been proposed in the industry, such as improvement of doping concentration, reduction of gate oxide thickness, and ultra-shallow source/drain. Junctions) and so on. However, for semiconductor elements down to 30 nanometers (nm), the industry is currently tempted to use field-effect transistors with multi-gates as the primary means of solving short-channel effects. One In general, a multi-gate field effect transistor includes a raised fin structure in which an active/drain region and a channel region are disposed, and a gate dielectric layer and a gate electrode can be correspondingly coated The channel area of the fin structure. For the current multi-gate field effect transistor, it can generally meet the needs of component miniaturization and has the ability to effectively control short channels.

However, the current technology still cannot effectively overcome the problem of uneven doping of three-dimensional structures. For example, although prior art solutions utilize two ion implantation processes having different tilt angles to form a lightly doped drain (LDD) and/or a halo implant region, However, its doping uniformity still cannot meet the needs of high-end products. And as the size of the component continues to shrink, the external resistance of the fin structure needs to be further reduced. Therefore, there is still a need in the industry for a multi-gate field effect transistor having a higher light-polar-doped region uniformity and a lower external resistance and a method of fabricating the same.

In view of the above, one of the objects of the present invention is to provide a complementary gold-oxygen half field effect transistor structure, a gold-oxygen semi-transistor structure, and a fabrication method thereof to solve the defects in the prior art.

According to an embodiment of the invention, a complementary MOS field effect transistor structure is provided, comprising a substrate, a first MOS field effect transistor, and a second MOS field effect transistor. The first gold oxide half field effect crystal system is disposed in the first transistor region on the substrate, and the second gold oxide half field effect transistor system is disposed in the second transistor region on the substrate. The first oxy-half field effect transistor includes a first fin structure, two first lightly doped regions, two first doped regions, and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein the first epitaxial portions are respectively disposed on each side of the first body portion, and the first body portion and each of the first epitaxial portions have A first vertical interface, so that the first lightly doped regions are each evenly distributed over the entire surface of each of the first vertical interfaces.

According to another embodiment of the present invention, a gold oxide half field effect transistor structure is provided, comprising a substrate, a fin structure, two lightly doped regions, a second doped region, and a gate structure. The fin structure is disposed on the substrate, and the fin structure comprises a body portion and two epitaxial portions, wherein the body portion and each of the epitaxial portions have a vertical interface, so that the lightly doped regions are uniformly distributed in the vertical interfaces. On the whole face.

According to still another embodiment of the present invention, there is provided a method of fabricating a gold oxide half field effect transistor structure comprising the following steps. First, a fin-shaped semiconductor layer is formed on a substrate, and a gate electrode is formed to cover the portion of the fin-shaped semiconductor layer. Next, a gate sidewall is formed on the sidewall of the gate electrode such that a portion of the fin-shaped semiconductor layer is exposed to the gate sidewall. The fin-shaped semiconductor layer exposed to the gate sidewalls is removed, and a vertical interface is formed on at least one side of the fin-shaped semiconductor layer. Then, at least one epitaxial layer is formed on the vertical interface, and a lightly doped region is simultaneously formed on the entire surface of each vertical interface. Finally, a doped region is formed in the epitaxial layer.

10‧‧‧First transistor area

20‧‧‧Second transistor region

100‧‧‧Semiconductor structure

102‧‧‧Substrate

110‧‧‧Semiconductor substrate

112‧‧‧Fin-shaped semiconductor layer

114‧‧‧Insulation

116‧‧‧ gate dielectric layer (first gate dielectric layer)

118‧‧‧gate electrode (first gate electrode)

119‧‧‧ gate structure (first gate structure)

120‧‧‧ first mask

122‧‧‧First side wall

124‧‧‧Second side wall

140a‧‧‧Vertical interface

140b‧‧‧Semiconductor interface

142‧‧‧ Body Department

146a‧‧‧Lightly doped area (first lightly doped area)

146b‧‧‧Lightly doped area (first lightly doped area)

150a‧‧‧ surface

150b‧‧‧ surface

216‧‧‧Second gate dielectric layer

218‧‧‧second gate electrode

219‧‧‧Second gate structure

246a‧‧‧Second lightly doped area

300a‧‧‧Vertical

300b‧‧‧ horizontal department

310‧‧‧ epitaxial layer (the epitaxial part, the first epitaxial part)

312‧‧‧Doped region (first doped region)

410‧‧‧Second Epitaxy

412‧‧‧Second doped region

500‧‧‧Gold oxygen half field effect transistor

600‧‧‧Second gold oxygen half field effect transistor (first gold oxide half field effect transistor)

700‧‧‧Complementary gold oxide half field effect transistor

L‧‧‧ carrier channel length

1 to 10 are schematic views showing the fabrication of a field effect transistor according to various embodiments of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

1 is a diagram showing a field effect transistor in accordance with a first embodiment of the present invention. Schematic diagram of the pieces. As shown in Fig. 1, a semiconductor structure 100 is first provided which can be used as the starting or intermediate structure of the multi-gate field effect transistor structure in this embodiment. In the process stage, the semiconductor structure 100 can include a semiconductor substrate 110, a fin-shaped semiconductor layer 112, an insulating layer 114, a gate dielectric layer 116, a gate electrode 118, a first mask 120, and a first A side wall 122 and a second side wall 124. It is to be noted that the structure shown in FIG. 1 is for illustrative purposes, and is not drawn to scale and that other components may be included in the end product requirements. According to the first embodiment of the present invention, the semiconductor substrate 110 and the insulating layer 114 constitute a substrate 102, and the fin-shaped semiconductor layer 112 can be regarded as a protruding portion of the semiconductor substrate 110. In more detail, the semiconductor substrate 110 protrudes beyond the insulating layer 114 to form a strip structure as shown in this embodiment, and thus the semiconductor substrate 110 and the fin-shaped semiconductor layer 112 may comprise the same main component, such as germanium. But it is not limited to this. However, according to other embodiments, the fin-shaped semiconductor layer 112 may not be a protruding portion of the semiconductor substrate 110. For example, the substrate 102 may be an insulating silicon-on-insulator (SOI) or other suitable substrate, and formed into a fin pattern having a strip pattern by appropriate photolithography, etching, or the like. Semiconductor layer 112. Therefore, an insulating layer 114 is interposed between the fin-shaped semiconductor layer 112 and the semiconductor substrate 110 so that they do not directly contact each other. The semiconductor substrate 110 may also include a dopant of a specific conductivity and a doping concentration, and may be covered with other suitable semiconductor layers, such as a germanium layer or a germanium phosphor layer.

Preferably, the fin-shaped semiconductor layer 112 has a stripe pattern such that three sides of a portion thereof are covered by the gate electrode 118. The gate electrode 118 is covered by a first mask 120, and the pattern of the first mask 120 can be transferred to the gate electrode 118 by etching. Preferably, the gate electrode 118 and the fin-shaped semiconductor layer 112 have at least one gate dielectric layer 116, which may be formed by oxidation, such as a thermal oxidation process, or by deposition. For example, a chemical phase deposition process is not limited thereto. The gate electrode 118 and the gate dielectric layer 116 may constitute a gate structure 119 as a member for controlling the opening/closing of the carrier channel in the transistor element. Further, the semiconductor structure 100 can be integrated into a MOS process having a polysilicon gate or a metal gate. For example, it may be a gate first process integrated into a gate first process or integrated into a metal gate. The gate electrode 118 may include a conductive material composed of a semiconductor component and/or a metal component, such as a semiconductor material such as polysilicon or a metal material such as tungsten, copper, nickel or aluminum, but is not limited thereto. The gate dielectric layer 116 material may comprise a general dielectric constant material such as hafnium oxide or a high dielectric constant material. The material having a high dielectric constant may be selected, for example, from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), and oxidation. Aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia ( Zirconium oxide, ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), niobium oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1- A group consisting of _x TiO ₃ , BST), but is not limited thereto.

The first sidewall sub-122 and the second sidewall sub-124 may be regarded as a gate sidewall and a fin-shaped semiconductor layer sidewall, respectively. In other words, the first sidewall spacers 122 mainly cover the sidewalls of the gate structure 119, and the second sidewall spacers 124 cover the sidewalls of the fin-shaped semiconductor layer 112. The first sidewall sub-122 and the second sidewall sub-124 may be formed simultaneously or non-simultaneously. For example, if the first sidewall sub-122 and the second sidewall sub-124 are formed simultaneously, the process includes a common dielectric material deposition process and a common etching process, so that the dielectric material can be separately formed on the gate. The structure 119 and the sidewalls of the fin-shaped semiconductor layer 112 constitute the first sidewall sub-122 and the second sidewall sub-124, but are not limited thereto. It should be noted that the first sidewall sub-122 and the second sidewall sub-124 are not limited to being a single-layer structure, and Contains a multi-layer structure that looks at process requirements.

After providing the structure of Figure 1, please refer to Figure 2. Fig. 2 is a schematic view showing the fabrication of a transistor element according to a first embodiment of the present invention. In FIG. 2, the second sidewall spacer 124 (or the fin-shaped semiconductor layer sidewall spacer) is completely removed, so that part of the fin-shaped semiconductor layer 112 is completely exposed to the first sidewall sub-122 (or gate) Extreme side wall). It should be noted that the method of removing the second sidewalls 124 is through a dry etching process or a wet etching process. According to the first embodiment, since the first side wall 122 and the second side wall 124 have the same composition, a portion of the first side wall 122 may also be removed, so that part of the first mask The side wall of 120 is exposed. In other words, this embodiment controls the appropriate etching parameters and the thickness of each deposited film, so that after the etching process for removing the second sidewall 124 is completed, even a portion of the first sidewall 122 is partially removed. However, only some of the sidewalls of the first mask 120 are exposed without exposing the gate electrode 118. However, according to other embodiments, if the first sidewall sub-122 and the second sidewall sub-124 have different compositions, or an etch barrier (not shown) is covered during the removal of the second sidewall 124 Living in the first side wall 122, in this case, only the second side wall 124 will be removed, so that the first side wall 122 can retain its original full shape.

After removing the second side wall 124, it is then as shown in FIG. Using the first mask 120 and the first sidewall 122 as an etch mask, at least one etching process, such as an anisotropic dry etching process, is performed to completely remove the fin-shaped semiconductor layer exposed to the first sidewall 122 112. Through this etching process, a vertical interface 140a is formed on at least one side of the fin-shaped semiconductor layer 112. Preferably, the vertical interface 140a is a vertical plane parallel to the direction in which the gate electrode 118 extends. The vertical plane may be aligned with a portion of the edge of the first sidewall 122 or slightly inwardly toward the first sidewall 122. . In addition, since the etching process completely removes the fin-shaped semiconductor layer 112 located outside the first sidewall sub-122, one of the semiconductor substrates 110 Semiconductor interface 140b may also be exposed and flush with the surface of insulating layer 114. Preferably, the vertical interface 140a and the semiconductor interface 140b have a vertical angle, but are not limited thereto. The etching process may be a plasma etching process, and the etching gas component includes an etching gas such as hydrogen bromide/oxygen, sulfur hexafluoride/chlorine gas, but is not limited thereto.

According to the embodiment described above, after the etching process, the semiconductor interface 140b is substantially flush with the upper surface of the insulating layer 114. However, according to the embodiment shown in FIG. 4, the semiconductor interface 140b may also be slightly lower than the surface of the insulating layer 114 to meet the requirements of the process. For example, the same or different etching gases may be provided simultaneously or after removing the fin-shaped semiconductor layer 112 exposed to the first sidewall sub-122 to further remove a portion of the semiconductor exposed to the insulating layer 114. The substrate 110 is such that the semiconductor interface 140b is slightly lower than the surface of the insulating layer 114. In addition, according to still another embodiment, the etching process may also selectively remove the fin-shaped semiconductor layer outside the first sidewall sub-122, so that the fin-shaped semiconductor layer still exists in the semiconductor interface. Above 140b.

Next, as shown in FIG. 5, at least one epitaxial growth process is performed, and an epitaxial layer 310 is formed on each side of the fin-shaped semiconductor layer 112. In more detail, as shown in FIG. 5, at least one epitaxial layer 310 is formed on the vertical interface 140a and the semiconductor interface 140b to serve as a source/drain for the subsequent storage of the transistor element. The main area. It should be noted here that, according to the first embodiment, the epitaxial growth process is preferably an in-situ growth process. For example, for a PMOS device process, the epitaxial growth process may be performed while doping a germanium single crystal while doping a specific conductive electrical dopant, such as boron, so that the epitaxial layer 310 reaches the desired electrical properties. The lightly doped source/drain electrode of the PMOS device is directly formed (not shown); in contrast, for an NMOS device process, the epitaxial growth process may be simultaneously doped while forming a germanium single crystal or tantalum carbide. A specific conductive electrical dopant, such as phosphorus or arsenic, causes the epitaxial layer 310 to achieve the desired electrical properties and directly constitutes the lightly doped source/drain of the NMOS device. In addition, after the epitaxial layer 310 is formed, a doping process may be further performed to form a doping region 312, or a source/drain doping region, in each epitaxial layer 310. Preferably, the dopant concentration of the doped region 312 is higher than the dopant concentration of the lightly doped source/drain. Thus far, the transistor element 500 of the first embodiment of the present invention, or a multi-gate field effect transistor element, is completed. A main feature of the present invention is that, when the epitaxial layer 310 is formed, a lightly doped region is formed in the epitaxial layer 310 and on the vertical interface 140a in situ, and lightly doped on the vertical interface 140a. The region can serve as a lightly doped drain (LDD) for the semiconductor device. Also, since the lightly doped region diffuses from the epitaxial layer 310 toward the fin-shaped semiconductor layer 112 and the semiconductor substrate 110 by thermal diffusion, it can be uniformly distributed over the entire surface of the vertical interface 140a. With such structural characteristics, in subsequent semiconductor elements, the carrier channels on the surface (two or three sides) of the fin-shaped semiconductor layer 112 can have substantially equal carrier lengths (L _eff ). Moreover, the concentration of the lightly doped region can be correspondingly increased by the change of the epitaxial parameter, which is beneficial to the electrical performance of the transistor component. This feature is specifically illustrated in Figures 7 and 8, and is described in detail below. In addition, according to another embodiment, the epitaxial growth process may further include at least two epitaxial growth processes such that the lightly doped regions are located only below the respective epitaxial layers and exhibit an L-shape. For example, as shown in FIG. 6 and with reference to FIG. 3, an in-situ epitaxial growth process may be used to form an L-type epitaxial layer on the vertical interface 140a and the semiconductor interface 140b, respectively. A vertical portion 300a and a horizontal portion 300b. Therefore, when the L-type epitaxial layer is formed, a lightly doped region is simultaneously formed in situ on the vertical interface 140a and the semiconductor interface 140b as a light source/drain-doped region of the semiconductor device. Then, another epitaxial growth process can be continued, and an epitaxial layer (not shown) is formed on the L-type epitaxial layer. In other words, the in-situ doping step can be performed only in the initial stage of the epitaxial process, and this in-situ doping step is not necessarily performed in the entire epitaxial process.

Please refer to Fig. 7, which is a schematic diagram drawn along the line AA' in Fig. 5. First, as shown in FIG. 7 and with reference to FIG. 5, the two epitaxial portions 310 including the doped region 312 are respectively located on two sides of a body portion 142, wherein the body portion 142 is the fourth image. The finned semiconductor layer 112 covered by a sidewall 122 and a gate electrode 118; and the epitaxial portion 310 is substantially the same as the epitaxial layer 310 referred to in the above embodiments. According to FIG. 7, a vertical interface 140a is disposed between each of the epitaxial portions 310 and the body portion 142, and a lightly doped region 146a is distributed on each of the vertical interfaces 140a. The vertical interface 140a is preferably as close as possible to the gate. The sidewalls of the structure 119 are preferably the side walls of the gate structure 119. In addition, a semiconductor interface 140b is further disposed between each of the epitaxial portions 310 and the semiconductor substrate 110, and another lightly doped region 146b is also distributed on each of the semiconductor interfaces 140b. As described above, since the lightly doped regions 146a, 146b are simultaneously formed in the epitaxial process, they can be uniformly distributed on the vertical interface 140a and the semiconductor interface 140b. In addition, at least one component of the epitaxial layer 310 will be identical to at least one component of the lightly doped regions 146a, 146b. Further, since the carrier channel is located on the surface of the body portion 142 between the two vertical interfaces 140a, the lightly doped region 146a is used as the light source/drain doping region and uniformly distributed on the entire surface of the vertical interface 140a. The carrier channel on the surface (two or three sides) of the body portion 142 can have substantially equal carrier length L (channel length, L _eff ), thereby facilitating reduction of variation in channel length, thereby improving the transistor element. Electrical performance.

Please refer to Fig. 8. Fig. 8 is a schematic view taken along line BB' in Fig. 5. As shown in Figure 8, and with reference to Figure 5. A semiconductor interface 140b exists between each of the epitaxial portions 310 and the semiconductor substrate 110, and the lightly doped regions 146b are distributed on the respective semiconductor interfaces 140b. It should be noted here that the epitaxial portion 310 referred to herein is substantially the same as the epitaxial layer 310 referred to in the above embodiments. In addition, a portion of the epitaxial portion 310 will be in direct contact with the first sidewall sub-122. More precisely, the oppositely disposed surfaces 150a, 150b of the first side wall 122 directly contact portions of the respective epitaxial portions 310 to form a mosaic-like structure. According to each of the above embodiments, the lightly doped regions between the epitaxial portion and the semiconductor substrate are distributed in each On the semiconductor interface, it is roughly flush with the insulating layer. However, according to other embodiments, if the fin-shaped semiconductor layer remaining outside the first sidewall protrudes beyond the insulating layer before the formation of the epitaxial layer, or the semiconductor substrate under the fin-shaped semiconductor layer is over-etched, The position of the doped region may be slightly higher or slightly lower than the insulating layer.

The above is a schematic view of the fabrication of the transistor element of the first embodiment of the present invention, but the present invention is not limited thereto. According to a second embodiment of the invention, it is also possible to remove the fin-shaped semiconductor layer exposed to the first sidewall at different points in time. As shown in Fig. 9, with reference to Fig. 1, the structure is similar to the process structure of Fig. 1. According to the second embodiment, after the semiconductor structure 100 as shown in FIG. 1 is provided, the second sidewall sub-124 may not be removed, but the first mask 120, the first sidewall sub-122 and the second The sidewall spacers 124 serve as an etch mask to perform an etching process, such as a dry etching process, to remove the fin-shaped semiconductor layer 112 exposed to the first sidewalls 122 such that at least one side of the fin-shaped semiconductor layer 112 forms a vertical interface 140a. . Preferably, the vertical interface 140a is a vertical plane extending in a direction parallel to the gate electrode 118, and the vertical plane is aligned with the edge of the portion of the first sidewall sub-122. In addition, since the etching process completely removes the fin-shaped semiconductor layer 112 exposed to the first sidewall sub-122, one semiconductor interface 140b of the semiconductor substrate 110 is also exposed, and the semiconductor interface 140b is preferably connected to the insulating layer 114. The surface is flush. Preferably, the vertical interface 140a and the semiconductor interface 140b have a vertical angle, but are not limited thereto. Next, the second sidewall spacer 124 can be selectively removed to form a structure as shown in FIG. 3, and then an epitaxial layer is formed while simultaneously forming a lightly doped region. Since the other processes in this embodiment are substantially similar to the processes shown in the first embodiment, they will not be described herein.

So far, a multi-gate MOSFET with a fin structure has been completed. It should be noted that in the above embodiments, the body portion 142 of the fin structure and the gate dielectric layer 116 have three direct contact surfaces, for example, two connections. The contact side (not shown) and the contact top surface (not shown) may be referred to as a tri-gate MOSFET. Compared with the planar field effect transistor, the three-gate field effect crystal system has the wider carrier channel width under the same gate length by using the above three direct contact surfaces as the channel through which the carrier flows. This results in a doubled drain drive current at the same drive voltage. However, the above-mentioned multi-gate field effect transistor is not limited to the three-gate field effect transistor, and depending on the requirements of the process, the top surface of the body portion 142 of the fin structure and the gate dielectric layer 116 may also be There is a patterned hard mask layer (not shown), that is, there will be only two direct contact faces between the fin structure body portion 142 and the gate dielectric layer 116, such as two contact sides (not shown). Therefore, the multi-gate field effect crystal system having two direct contact faces constitutes a fin field effect transistor (Fin FET).

According to the above embodiments, only a single polarity transistor element is provided as an object of the invention, such as an NMOS element or a PMOS element. However, the present invention is also applicable to other transistor elements, such as complementary MOSFETs, the structure of which is described below. It is to be noted that the following description of the main differences between the present embodiment and the above embodiments is given, and the same or similar elements or structures will be denoted by the same reference numerals.

As shown in Fig. 10 and with reference to Fig. 5, a complementary MOS field effect transistor 700 is provided. The substrate 102 has a first transistor region 10, such as an NMOS region and a second transistor region 20, such as a PMOS region. A first gold oxide half field effect transistor 500, such as an NMOS, is disposed within the first transistor region 10 and has a structure similar to that shown in FIG. The first MOS field-effect transistor 500 includes a first fin structure, two first lightly doped regions 146a, two first doped regions 312, and a first gate structure 119. The first fin-shaped structure includes a first body portion 142 and two first epitaxial portions 310, wherein the first epitaxial portions 310 are respectively disposed on two sides of the first body portion 142, and the first body portion 142 has a first vertical interface 140a between each of the first epitaxial portions 310. The first lightly doped regions 146a are each uniformly distributed over the entire surface of each of the first vertical interfaces 140a to serve as a light source/drain doped region of the semiconductor device. The first doped regions 312 are each disposed in each of the first epitaxial portions 310 , and the first gate structures 119 cover the first body portions 142 . In addition, the second MOS field effect transistor 600 is disposed in the second transistor region 20. The structure of the second gold oxide half field effect transistor 600 is substantially similar to that of the first gold oxide half field effect transistor 500. However, the composition of the epitaxial portion and the polarity of the lightly doped region may vary. For example, if the second MOS field-effect transistor 600 is a PMOS, the epitaxial portion 410 includes a material that can apply a compressive stress to the carrier channel, such as bismuth telluride, and the second lightly doped region is preferably Contains P-type dopants such as boron. More precisely, the second MOS field-effect transistor 600 includes a second fin structure, two second lightly doped regions 246a, two second doped regions 412, and a second gate structure 219. The second fin structure includes a second body portion (not shown) and two second epitaxial portions 410. The second epitaxial portions 410 are respectively disposed on the respective sides of the second body portion, wherein the second body portion and each of the second epitaxial portions 410 have a second vertical interface. Each of the second lightly doped regions is distributed over the entire surface of each of the second vertical interfaces 240a to serve as a light source/drain doped region of the semiconductor device. Each of the second doped regions 412 is disposed in each of the second epitaxial portions 410. The second gate structure 219 includes a second gate dielectric layer 216 and a second gate electrode 218, and it covers the second body portion.

In summary, the present invention provides a complementary MOSFET structure, a MOSFET structure, and a method of fabricating the same. During the epitaxial process, a lightly doped region is simultaneously formed uniformly on the vertical interface between the epitaxial layer and the body portion of the fin structure as a light source/drain doping region of the semiconductor device. Therefore, the carrier channels located on the surface (two or three sides) of the fin-shaped semiconductor layer will have substantially the same carrier length (L _eff ). In addition, the concentration of the light source/germanium doping region can be correspondingly increased by the change of the epitaxial parameter, which is beneficial to the electrical performance of the transistor component.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110‧‧‧Semiconductor substrate

116‧‧‧ gate dielectric layer

118‧‧‧gate electrode

119‧‧ ‧ gate structure

120‧‧‧ first mask

122‧‧‧First side wall

140a‧‧‧Vertical interface

140b‧‧‧Semiconductor interface

142‧‧‧ Body Department

146a‧‧‧lightly doped area

146b‧‧‧lightly doped area

310‧‧‧ Epitaxial layer (Eradiation)

312‧‧‧Doped area

L‧‧‧ carrier channel length

Claims (21)

A complementary metal oxide half field effect transistor (MOSFET) structure includes: a substrate including a first transistor region and a second transistor region; and a first gold oxide half field effect transistor disposed at the first In the region of the transistor, the first MOSFET has a first fin structure including a first body portion and two first epitaxial portions, wherein the first epitaxial portions are respectively disposed on the Each of the first body portions has a first vertical interface between the first body portion and each of the first epitaxial portions; and the first lightly doped regions are uniformly distributed to each of the first vertical interfaces. And a surface between the first epitaxial portion and the substrate; two first doped regions, each disposed in each of the first epitaxial portions; and a first gate structure covering the first body portion; and a A second gold oxide half field effect transistor is disposed in the second transistor region. The complementary MOSFET structure of claim 1, wherein the first body portion comprises a first material, and at least one of the first epitaxial portions comprises a second material different from the first material. . The complementary MOSFET structure of claim 1, wherein each of the first vertical interfaces is a vertical plane. The complementary MOSFET structure of claim 1, further comprising a gate sidewall disposed on a sidewall of the first gate structure. The complementary MOSFET structure of claim 4, wherein the first gate sidewall includes two oppositely disposed surfaces, and the surfaces directly contact at least one of the first epitaxial portions Part of the area. The complementary MOSFET structure of claim 1, wherein the substrate comprises a semiconductor substrate and an insulating layer disposed on the semiconductor substrate. The complementary MOSFET structure of claim 6, wherein a portion of the semiconductor substrate protrudes from the insulating layer. The complementary MOSFET structure according to claim 1, wherein the first epitaxial portions comprise an epitaxial germanium, an epitaxial germanium germanium, a boron-doped epitaxial germanium germanium, an epitaxial phosphorous or an epitaxial germanium. carbon. The complementary MOSFET structure of claim 1, wherein the second MOS field effect transistor further comprises: a second fin structure comprising: a second body portion; and two second epitaxial layers The second light-doped regions are respectively disposed on the two sides of the second body portion, and the second light-doped regions are respectively disposed on the first a whole surface of the two vertical interfaces and between the second epitaxial portions and the substrate; two second doped regions, each disposed in each of the second epitaxial portions; and a second gate structure covering the second Body part. A metal oxide half field effect transistor (MOSFET) structure comprises: a substrate; a fin structure disposed on the substrate, wherein the fin structure comprises a body portion and two epitaxial grains And a vertical interface between the body portion and each of the epitaxial portions; two lightly doped regions are uniformly distributed on the entire surface of each of the vertical interfaces and between the epitaxial portions and the substrate; The impurity regions are respectively disposed in each of the epitaxial portions; and a gate structure covers the body portion of the fin structure. The MOSFET structure of claim 10, wherein each of the vertical interfaces is a vertical plane. The MOSFET structure of claim 10, further comprising a gate sidewall disposed on a sidewall of the gate structure. The MOSFET structure of claim 12, wherein the gate sidewall includes two oppositely disposed surfaces, and the surfaces directly contact at least one of the regions of the epitaxial portions. The MOSFET structure of claim 10, wherein the substrate comprises a semiconductor substrate and an insulating layer disposed on the semiconductor substrate. A method for fabricating a metal oxide half field effect transistor (MOSFET) structure, comprising: providing a substrate; forming a fin-shaped semiconductor layer on the substrate; forming a gate electrode covering a portion of the fin-shaped semiconductor layer Forming a gate sidewall disposed on a sidewall of the gate electrode, wherein a portion of the fin-shaped semiconductor layer is exposed to the gate sidewall; removing the exposed sidewall of the gate a fin-shaped semiconductor layer, and forming a vertical interface on at least one side of the fin-shaped semiconductor layer; Forming at least one epitaxial layer on the vertical interface, wherein a lightly doped region is formed on the entire surface of the vertical interface while forming the epitaxial layer; and forming a doping in the epitaxial layer Area. The method of fabricating a MOSFET structure according to claim 15, wherein the gate sidewall is used as an etch mask when the fin semiconductor layer exposed to the gate sidewall is removed. The method for fabricating a MOSFET structure according to claim 15, wherein each of the vertical interfaces is a vertical plane. The method for fabricating a MOSFET structure according to claim 15, wherein after forming the epitaxial layer, the gate sidewall includes two oppositely disposed surfaces, and the surfaces directly contact at least one of the plurality of Lei Part of the crystal part. The method of fabricating a MOSFET structure according to claim 15, wherein the substrate comprises a semiconductor substrate and an insulating layer disposed on the semiconductor substrate. The method for fabricating a MOSFET structure according to claim 19, wherein a bottom surface of the epitaxial layer is lower than a top surface of the insulating layer. The method for fabricating a MOSFET structure according to claim 15 , further comprising another lightly doped region disposed between the at least one of the epitaxial portions and the semiconductor substrate.