TWI527227B - Semiconductor structure and process thereof - Google Patents

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and a process thereof, and more particularly to a semiconductor structure and a process for directly forming an epitaxial structure in a contact hole.

Epitaxial technology is commonly used in semiconductor devices. The function of epitaxial technology can not only form a monolithic germanium layer, but also solve the problems caused by other semiconductor processes, or to make special functional components. For example, when the metal telluride process is performed, a metal layer is covered on the source/drain region, and the metal in the metal layer reacts with the underlying germanium to form a metal germanide layer for electrically connecting the source below. The / bungee zone (usually a coffin or bismuth compound) and the metal column above, and buffering the difference in material structure between the two reduces the sheet resistance. However, when the metal layer reacts too much with the ruthenium in the source/drain region or the region of the source/drain region is too shallow, it may often cause the source/drain regions after the reaction to be few and damage the pn junction (pn junction). ). Therefore, an improved method can form an epitaxial layer before forming a metal layer on the source/drain regions. Taking the enamel substrate as an example, it can be combined with enamel epitaxy or bismuth telluride. Thus, the epitaxial layer between the source/drain region and the metal layer allows the metal layer to directly react with the epitaxial layer without limiting the volume of the source/drain region.

In addition, as semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. One of the common strained-silicon techniques is to grow a strained epitaxial layer on the source/drain regions of a semiconductor substrate. Since the lattice constant of the strained epitaxial layer is different from the lattice constant of the semiconductor substrate, the lattice constant of the strained germanium epitaxial layer can be changed, and the lattice constant of the MOS transistor can be changed. Stress is generated.

As the size of the semiconductor component is reduced, the method of growing the epitaxial layer on the source/drain region is more important but also has some negative effects. For example, for a fin field effect transistor, the source/drain regions are formed in the fin structure, and the epitaxial structure covers the source/drain regions. However, the epitaxial structure enlarges the volume of the entire fin structure, resulting in a reduction in space between the fin structures, and may even cause adjacent fin structures to be joined together, resulting in short-circuiting of the components. In other words, if the adjacent fin structures are to be joined together, a certain distance needs to be maintained between the fin structures, but this distance will limit the size of the semiconductor component. This problem is particularly noticeable in Static Random Access Memory (SRAM) where the fin structure is densely distributed.

The invention provides a semiconductor structure and a process thereof, and solves the above problems by a method of forming an epitaxial structure in a contact hole.

The present invention provides a semiconductor structure including at least one fin structure, a gate, a source/drain region, an interlayer dielectric layer, and an epitaxial structure. At least one fin structure is located on a substrate. The gate is covered on the fin structure. The source/drain regions are located in the fin structure on the side of the gate. The interlayer dielectric layer covers the gate and the fin structure, wherein the interlayer dielectric layer has a plurality of contact holes exposing at least a portion of the source/drain regions. The epitaxial structure is located in the contact hole and is in direct contact and only on the source/drain region.

The present invention provides a semiconductor process comprising the steps described below. First, a substrate is provided. Next, a MOS transistor is formed on the substrate, wherein the MOS transistor includes a gate on the substrate and a source/drain region in the substrate on the side of the gate. Successively, an inter-layer dielectric layer is formed to cover the substrate on the side of the gate. Further, a plurality of contact holes are formed in the interlayer dielectric layer and expose at least a portion of the source/drain regions. Then, an epitaxial structure is formed in each contact hole, and is directly in contact with and only on the source/drain region. Thereafter, a metal telluride is formed on the epitaxial structure in each contact hole. Thereafter, a dielectric layer is deposited over the interlayer dielectric layer and overlying the gate. Then, a plurality of corresponding contact holes are formed in the dielectric layer, and the contact holes are connected. Finally, a metal material is filled in each of the contact holes and the metal halides in the corresponding contact holes.

The present invention provides a semiconductor process comprising the steps described below. First, a substrate is provided. Next, a MOS transistor is formed on the substrate, wherein the MOS transistor includes a gate on the substrate and a source/drain region in the substrate on the side of the gate. Subsequently, an interlayer dielectric layer and a dielectric layer are formed to cover the gate and the substrate. Further, a plurality of contact holes are formed in the interlayer dielectric layer and the dielectric layer to expose at least a portion of the source/drain regions. Then, an epitaxial structure is formed in each contact hole. Thereafter, a metal telluride is formed on each of the epitaxial structures in each contact hole. Thereafter, a metal material is separately filled in the metal halide in each contact hole.

Based on the above, the present invention provides a semiconductor structure and a process thereof, which can effectively control the range of growth of an epitaxial structure by forming an epitaxial structure in a contact hole. For example, the present invention can effectively control the size and shape of the epitaxial structure growth and the like. Therefore, according to the present invention, the range of growth of the epitaxial structure can be controlled, and the adjacent epitaxial structures are prevented from being connected together to cause short circuit of the semiconductor element. Furthermore, by effectively controlling the range in which the epitaxial structure grows, the layout of the semiconductor elements can be refined, and the size of the semiconductor elements can be miniaturized.

1-7 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention. First, as shown in Fig. 1, a MOS transistor M is formed on a substrate 110. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. It should be noted that the semiconductor process illustrated in Figures 1-7 and 8-11 of the subsequent description may be a process of a fin field effect transistor, so the substrate 110 is a substrate block, and The substrate 110 may include a substrate 112 and at least one fin structure 114 on the substrate 112. However, the present invention may also be a planar transistor process because the fin field effect transistor and the planar transistor have the same cross-sectional structure. Moreover, the present invention can be applied to the structure of both, so it is shown in combination. However, in order to make the description of the present invention clearer, the following is a description of the process of a fin field effect transistor, but the scope of application of the present invention is not limited thereto. In addition, the present invention can also be applied to other semiconductor processes, such as various planar transistor processes and non-planar transistor processes, etc., and the spirit of the present invention is also within the scope of the present invention.

Please continue to refer to FIG. 1. First, the method of forming the fin structure 114 on the substrate 112 may, for example, provide a piece of substrate (not shown) on which a hard mask layer (not shown) is formed. And patterning to define the position of the fin structure 114 to be formed correspondingly in the underlying bulk substrate. Next, an etching process is performed to form the fin structure 114 in a bulk substrate (not shown). Thus, the fabrication of the fin structure 114 on the substrate 112 is completed. In one embodiment, after forming the fin structure 114, the hard mask layer (not shown) is removed, and a three-gate tri-gate MOSFET can be formed in a subsequent process. As a result, since the fin structure 114 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed dielectric layers, it is called a tri-gate field effect transistor (tri-gate). MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage. In another embodiment, a hard mask layer (not shown) may be left, and another multi-gate MOSFET-fin field having a fin structure is formed in a subsequent process. Fin field effect transistor (Fin FET). In a fin field effect transistor, since a hard mask layer (not shown) is left, there are only two contact sides between the fin structure 114 and a dielectric layer to be formed later.

In addition, as described above, the present invention can also be applied to other kinds of semiconductor substrates. For example, in another embodiment, an insulating substrate (not shown) is provided and etched by etching and lithography. The formation of the fin structure on the insulating substrate can be completed by covering the single crystal germanium layer on the insulating substrate (not shown) and stopping at the oxide layer.

In addition, in order to clearly disclose the present invention, only one of the fin structures 114 of the present embodiment is shown, but the fin structure 114 to which the present invention can be applied may also be plural.

Next, a gate 120 is overlaid on the fin structure 114. The method for forming the gate 120 may include sequentially forming a buffer layer (not shown), a gate dielectric layer (not shown), an electrode layer (not shown), and a cap layer (not shown). Patterning is performed to form a buffer layer 122 on the fin structure 114, a gate dielectric layer 124 on the buffer layer 122, an electrode layer 126 on the gate dielectric layer 124, and a cap layer 128 on the electrode. On the layer 126; a spacer 129 is then formed on the sides of the buffer layer 122, the gate dielectric layer 124, the electrode layer 126, and the cap layer 128. In this way, the fabrication of the gate 120 is completed. Next, a source/drain region 130 is formed in the fin structure 114 on the side of the gate 120 by, for example, ion implantation. The gate 120 and the source/drain regions 130 constitute an MOS transistor M.

At this time, the buffer layer 122 can be, for example, a germanium dioxide layer; the gate dielectric layer 124 can be, for example, an oxide layer or a high-k dielectric layer, and the material thereof can be selected from hafnium oxide (HfO _{2 ).} ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La _{2 )} O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicate oxides _{(zirconium silicon oxide, ZrSiO 4)} , hafnium zirconium _{(hafnium zirconium oxide, HfZrO 4)} , tantalum oxide bismuth strontium _{(strontium bismuth tantalate, SrBi 2 Ta} 2 O 9, SBT), lead zirconate titanate (lead zirconate titanate, PbZr _x Ti _1-x O ₃ , PZT) and a group consisting of barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST); the electrode layer 126 can be, for example, a The polysilicon layer; the cap layer 128 and the spacer 129 may be composed of tantalum nitride, but the invention is not limited thereto In this embodiment, a gate high dielectric constant layer (Gate Last for high-K Last) process is used, so the gate dielectric layer 124 is only a dielectric layer such as a general oxide layer. Moreover, since the electrode layer 126 is a polysilicon layer, the gate 120 formed is a polysilicon gate. Then, in other embodiments, a gate high potential dielectric layer (Gate Last for high-K First) process, a front gate process (Gate First) or a polysilicon gate process may be used. The invention is not limited to this.

As shown in FIG. 2, a contact hole etch stop layer 140 may be selectively formed to cover the gate 120 and the substrate 110. Subsequently, a planarized interlayer dielectric layer 150 is formed to cover the substrate 110 on the side of the gate 120. In the present embodiment, the gate 120 is a polysilicon gate, which is also a sacrificial gate, which is replaced by a gate replacement process to form a metal gate 160. In detail, an interlayer dielectric layer (not shown) is formed to cover the gate 120 and the substrate 110. Then, for example, a chemical mechanical polishing process is performed to polish an interlayer dielectric layer (not shown), and a planarized interlayer dielectric layer 150 is formed to cover the substrate 110 on the side of the gate 120, wherein the interlayer dielectric is interposed. While the layer (not shown) is also removed, the cap layer 128 is also removed to expose the underlying electrode layer 126. Then, the electrode layer 126 and the gate dielectric layer 124 are sequentially removed, and then a high-k dielectric layer 162 is sequentially filled, a bottom barrier layer (not shown), a work function metal layer 164, A top barrier layer (not shown) and a low resistivity material 166 form a metal gate 160. The low resistivity material 166 may comprise a metal such as aluminum, copper, tungsten, or the like.

As shown in FIG. 3, a plurality of contact holes R1 are formed in the interlayer dielectric layer 150 by, for example, an etching and lithography process, and at least a portion of the source/drain regions 130 are exposed. Then, as shown in Fig. 4, an epitaxial structure 170 is formed in the contact hole R1, respectively. As shown, the epitaxial structure 170 is located only in the contact hole R1 and is in direct contact with and located on a portion of the source/drain region 130. Furthermore, in this embodiment, the epitaxial structure 170 does not extend over the contact hole R1, but in other embodiments, the epitaxial structure 170 may also extend over the contact hole R1. The epitaxial structure 170 may include a germanium epitaxial layer suitable for a PMOS transistor, a germanium carbon epitaxial layer suitable for an strained germanium epitaxial layer such as an NMOS transistor, or a tantalum epitaxial layer for use without The applied stress may be only one litre source/dip (s) and used as part of the formation of metal telluride.

Referring to FIG. 4, a metal germanide 180 is formed on the epitaxial structure 170 in the contact hole R1. In detail, a metal layer (not shown) may be formed on the epitaxial structure 170, and then, for example, at least one heat treatment is performed to diffuse the metal of the metal layer (not shown) into the partial epitaxial structure 170. A metal telluride 180 is formed. The metal layer (not shown) may be, for example, a material containing nickel, cobalt, titanium metal or the like. Preferably, after completion of the metal telluride 180, there is still a partial epitaxial structure 170 between the source/drain region 130 and the metal telluride 180.

As shown in FIG. 5, a dielectric layer 190 is deposited over the interlayer dielectric layer 150 and overlying the metal gate 160. The material of the dielectric layer 190 is preferably the same as that of the interlayer dielectric layer 150, which may be an extension of the interlayer dielectric layer 150.

As shown in FIG. 6, a plurality of corresponding contact holes R2 are formed in the dielectric layer 190, and the contact holes R1 are connected. In this embodiment, the contact hole R2 is aligned downward with the contact hole R1 to form a contact hole R with the contact hole R1. Moreover, in the embodiment, while forming the corresponding contact hole R2, a gate contact hole R3 is also formed directly above the metal gate 160, and at least a portion of the metal gate 160 is exposed.

As shown in Fig. 7, a metal material 198 is filled in the contact hole R and the gate contact hole R3, respectively, and planarized to complete the semiconductor process of the present invention. The metal material 198 may include a barrier layer (not shown) of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like, and a metal such as tungsten, copper or aluminum.

8-11 are schematic cross-sectional views showing a semiconductor process according to a second embodiment of the present invention. First, as shown in FIG. 1-2, after the interlayer dielectric layer 150 is formed to cover the substrate 110 on the side of the gate 120 and the metal gate 160 is further formed, as shown in FIG. 8, the dielectric layer 190 is formed between the layers. The dielectric layer 150 is covered and covered with a metal gate 160. Similarly, the substrate 110 can be a semiconductor substrate such as a substrate block or a silicon-on-insulator (SOI) substrate, and can have at least one fin structure thereon, so that the second embodiment of the present invention can be applied to various planar transistor processes and non- Semiconductor process such as planar transistor process.

Next, as shown in FIG. 9, a plurality of contact holes R are formed in the interlayer dielectric layer 150 and the dielectric layer 190 to expose at least a portion of the source/drain regions 130, for example, by an etching and lithography process. As shown in FIG. 10, an epitaxial structure 170 is formed in the contact hole R, respectively, wherein the epitaxial structure 170 is located only in the contact hole R and is in direct contact with and located on a portion of the source/drain region 130. Moreover, in this embodiment, the epitaxial structure 170 does not extend over the contact hole R, but in other embodiments, the epitaxial structure 170 may also extend over the contact hole R. The epitaxial structure 170 may comprise a germanium epitaxial layer suitable for PMOS transistors, a germanium carbon epitaxial layer suitable for strained germanium epitaxial layers such as NMOS transistors, or a tantalum epitaxial layer for no external stress It may be only a raised source/dip (s) and used as part of the formation of metal halides. Next, metal telluride 180 is formed on each of the epitaxial structures 170 in the contact hole R, respectively. In detail, a metal layer (not shown) may be formed on the epitaxial structure 170, and then, for example, at least one heat treatment is performed to diffuse the metal of the metal layer (not shown) into the partial epitaxial structure 170. A metal telluride 180 is formed. The metal layer (not shown) may be, for example, a material containing nickel, cobalt, titanium metal or the like. Then, an etching and lithography process can be performed to form a gate contact hole (not shown). Finally, a metal material (not shown) is filled in the contact hole R and the gate contact hole (not shown), and planarized to complete the semiconductor process of the present invention. The metal material (not shown) may include a barrier layer (not shown) of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like, and a metal such as tungsten, copper or aluminum. .

In addition, a plurality of contact holes R and gate contact holes (not shown) may be simultaneously formed in the interlayer dielectric layer 150 and the dielectric layer 190, for example, by etching and lithography, to expose at least part of the source/ The drain region 130 and the low resistivity material 166. Next, an epitaxial structure 170 is formed in the contact hole R, respectively. Since the low resistivity material 166 is a metal material, the epitaxial structure does not grow. Thereafter, a metal material (not shown) may be separately and simultaneously filled in the contact hole R and the gate contact hole (not shown), and planarized to complete the semiconductor process of the present invention.

A semiconductor structure of the present invention can be formed by both the first embodiment and the second embodiment of the present invention. 11 is a cross-sectional view showing a semiconductor structure according to an embodiment of the present invention. A semiconductor structure 200 includes a fin structure 114, a gate 210, a source/drain region 130, an interlayer dielectric layer 220, and an epitaxial structure 170. The fin structure 114 is located on a substrate 112. The gate 120 covers the fin structure 114. The source/drain region 130 is located in the fin structure 114 on the side of the gate 120. The interlayer dielectric layer 220 (including the interlayer dielectric layer 150 and the dielectric layer 190 in the first embodiment and the second embodiment) covers the gate 210 and the fin structure 114. A contact hole etch stop layer (not shown) is selectively interposed between the interlayer dielectric layer 220 and the fin structure 114. The interlayer dielectric layer 220 has a plurality of contact holes R and a gate contact hole R3 exposing at least a portion of the source/drain regions 130 and at least a portion of the gates 210, respectively. The epitaxial structure 170 is located in the contact hole R and is in direct contact with only the source/drain region 130. A metal telluride 180 is located on the epitaxial structure 170 in the contact hole R. A metal post 230 is located on the metal telluride 180 in the contact hole R and in the gate contact hole R3. The fin structure 114 and the substrate 112 may be a substrate 110 composed of the same material, such as a coffin. The gate 210 can be a polysilicon gate or a sacrificial gate, which can be formed by a metal gate after forming a portion of the interlayer dielectric layer 220 (corresponding to the interlayer dielectric layer 150 in the first embodiment and the second embodiment). Extremely replaced. The epitaxial structure 170 includes a strained epitaxial layer or a tantalum epitaxial layer. The metal post 230 may be formed of a metal such as copper or aluminum.

According to the first embodiment and the second embodiment of the present invention, after the contact hole R is formed, the epitaxial structure 170 is formed in the contact hole R, so that the epitaxial structure 170 can be restricted from growing. Contact the hole R. In this way, the present invention can effectively control the growth range of the epitaxial structure 170 by restricting the epitaxial structure 170 from growing into the contact hole R, and prevent the epitaxial structures 170 on the fin structures 114 from being joined together. Moreover, the function of the micro-semiconductor structure 200 can be further achieved by completely controlling the size and shape of the epitaxial structure 170 grown by forming the epitaxial structure 170 only in the contact hole R.

In addition, the semiconductor structure 200 formed by the semiconductor process of the first embodiment and the second embodiment of the present invention can also be applied to various semiconductor devices, for example, to form a static random access memory (SRAM). ). In other words, when the number of MOS transistors of the semiconductor structure 200 is plural, and a specific layout distribution is performed according to actual needs, a static random access memory (SRAM) can be formed. FIG. 12 is a schematic diagram showing the layout of a conventional random access memory according to an embodiment of the present invention, wherein the above figure is a schematic diagram of a conventional static random access memory, and the following figure is an implementation of the present invention. A schematic diagram of the layout of a static random access memory. As shown in the lower diagram of FIG. 12, a static random access memory 300 formed by the semiconductor structure 200 of the present invention includes two double fin structures 310 and 350, and four single fin structures 320, 330, 340 and 360. When the size of the SRAM 300 is smaller, the distance between the double fin structures 310 and 350 is denser than that of the single fin structures 320, 330, 340, and 360, and the double fin structure 310 and Adjacent fin structures in 350 are more easily joined together, resulting in a short circuit of the SRAM 300. Therefore, the present invention can prevent each epitaxial structure (not shown) from being connected in the contact hole (not shown) by limiting the epitaxial structure (not shown) in the double fin structures 310 and 350. Together, the short circuits of the double fin structures 310 and 350 are prevented from being short-circuited. Furthermore, the SRAM 300 (below) formed by the semiconductor process of the present invention and the conventional SRAM 400 (above) can be compared without changing other process parameters, and can be found. The size of the SRAM 300 formed by the semiconductor process of the present invention can be much smaller than that of the SRAM 400, for example, the distance d can be reduced in length.

In summary, the present invention provides a semiconductor structure and a process thereof. By forming an epitaxial structure only in a contact hole, the range of growth of the epitaxial structure can be effectively controlled. For example, the present invention can effectively control the size and shape of the epitaxial structure growth and the like. Specifically, in the process of forming the semiconductor structure of the present invention, the contact hole can be formed first, and then the epitaxial structure is filled therein. In detail, a two-stage method of forming a contact hole may be employed, which first forms an underlying contact hole and forms an epitaxial structure and a metal telluride therein, and then forms an upper contact hole and a gate contact hole together; or The contact hole can be formed by a one-step method, and the contact hole can be directly produced in one time, and then the epitaxial structure, the metal telluride and the metal column are sequentially formed.

Thus, by the method of the present invention, the range of growth of the epitaxial structure can be controlled to prevent the adjacent epitaxial structures from being joined together to cause short circuit of the semiconductor element. Furthermore, by effectively controlling the range in which the epitaxial structure grows, the layout of the semiconductor element can be refined, and the size of the semiconductor element can be reduced.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110. . . Base

112. . . Substrate

114. . . Fin structure

120, 210. . . Gate

122. . . The buffer layer

124. . . Gate dielectric layer

126. . . Electrode layer

128. . . Cover

129. . . Clearance wall

130. . . Source/bungee area

140. . . Contact hole etch stop layer

150, 220. . . Interlayer dielectric layer

160. . . Metal gate

162. . . High dielectric constant dielectric layer

164. . . Work function metal layer

166. . . Low resistivity material

170. . . Epitaxial structure

180. . . Metal telluride

190. . . Dielectric layer

198. . . metallic material

200. . . Semiconductor structure

230. . . Metal column

300, 400. . . Static random access memory

310, 350. . . Double fin structure

320, 330, 340, 360. . . Single fin structure

d. . . distance

M. . . MOS transistor

R, R1. . . Contact hole

R2. . . Corresponding contact hole

R3. . . Gate contact hole

1-7 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention.

8-10 are schematic cross-sectional views showing a semiconductor process of a second embodiment of the present invention.

11 is a cross-sectional view showing a semiconductor structure according to an embodiment of the present invention.

FIG. 12 is a schematic diagram showing the layout of a conventional random access memory according to an embodiment of the present invention.

110‧‧‧Base

112‧‧‧Substrate

114‧‧‧Fin structure

122‧‧‧buffer layer

130‧‧‧Source/Bungee Zone

150‧‧‧Interlayer dielectric layer

160‧‧‧Metal gate

162‧‧‧High dielectric constant dielectric layer

164‧‧‧Work function metal layer

166‧‧‧ Low resistivity materials

170‧‧‧ epitaxial structure

180‧‧‧Metal Telluride

190‧‧‧ dielectric layer

198‧‧‧Metal materials

R, R1‧‧‧ contact hole

R2‧‧‧ corresponding contact hole

R3‧‧‧ gate contact hole

Claims (25)

A semiconductor structure comprising: at least one fin structure on a substrate; a gate covering the fin structure; a source/drain region in a fin structure on a side of the gate; An electric layer covers the gate and the fin structure, wherein the interlayer dielectric layer has a plurality of contact holes exposing at least a portion of the source/drain regions, and a top surface of the interlayer dielectric layer and the gate A top surface is flush; and an epitaxial structure is located in each of the contact holes and is in direct contact with and only on the source/drain region. The semiconductor structure of claim 1, wherein the gate comprises a polysilicon gate or a metal gate. The semiconductor structure of claim 1, further comprising a contact etch stop layer between the interlayer dielectric layer and the fin structure. The semiconductor structure of claim 1, further comprising a metal telluride on the epitaxial structure in each of the contact holes, and a metal pillar on the metal germanide in each of the contact holes . The semiconductor structure of claim 1, wherein the epitaxial structure comprises a strained epitaxial structure. A semiconductor process comprising: providing a substrate; forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate on the substrate and a source/drain region on the side of the gate Forming an interlayer dielectric layer covering the substrate on the side of the gate; forming a plurality of contact holes in the interlayer dielectric layer and exposing at least a portion of the source/drain regions; respectively forming an epitaxial structure filling Filling each of the contact holes and directly contacting and only located on the source/drain regions; forming a metal germanide on the epitaxial structure in each of the contact holes; depositing a dielectric layer on the interlayer And electrically covering the gate; forming a plurality of corresponding contact holes in the dielectric layer and connecting the contact holes; and respectively filling a metal material in each of the contact holes and each of the corresponding contacts The metal telluride in the hole. The semiconductor process of claim 6, wherein the gate comprises a polysilicon gate. The semiconductor process of claim 6, wherein the gate comprises a sacrificial gate, and after forming the interlayer dielectric layer to cover the substrate on the side of the sacrificial gate, further comprising: a metal gate The pole replaces the sacrificial gate. The semiconductor process of claim 6, wherein the forming the interlayer dielectric layer to cover the gate side of the substrate further comprises: forming a contact hole etch stop layer on the substrate and the interlayer dielectric layer between. The semiconductor process of claim 6, wherein the substrate comprises a substrate block. The semiconductor process of claim 6, wherein the substrate comprises a substrate and at least one fin structure on the substrate, and the gate and the source/drain region are formed on the fin structure. on. The semiconductor process of claim 6, wherein the number of the MOS transistors is plural, and the layout of the MOS transistors forms a static random access memory (SRAM). . The semiconductor process of claim 6, wherein the epitaxial structure comprises a strained epitaxial structure. The semiconductor process of claim 6, wherein the epitaxial structure is formed in each of the contact holes, respectively, and each of the contact holes is formed in the epitaxial structure filling portion. The semiconductor process of claim 6, wherein forming a plurality of corresponding contact holes further comprises simultaneously forming a gate contact hole in the dielectric layer to expose the gate. A semiconductor process comprising: providing a substrate; forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate on the substrate and a source/drain region on the side of the gate Forming an interlayer dielectric layer and a dielectric layer to cover the gate and the substrate; forming a plurality of contact holes in the interlayer dielectric layer and the dielectric layer to expose at least a portion of the source/germanium a pole region; respectively forming an epitaxial structure filling each of the contact holes; respectively forming a metal germanide on the epitaxial structure in each of the contact holes; and respectively filling a metal material in each of the contacts The metal telluride in the hole. The semiconductor process of claim 16, wherein the gate comprises a polysilicon gate. The semiconductor process of claim 16, wherein the gate comprises a sacrificial gate, and the step of forming the interlayer dielectric layer and the dielectric layer covering the sacrificial gate and the substrate comprises: Forming the interlayer dielectric layer on the substrate on the side of the sacrificial gate; replacing the sacrificial gate with a metal gate; The dielectric layer is formed on the interlayer dielectric layer and covers the metal gate. The semiconductor process of claim 16, wherein before sequentially forming the interlayer dielectric layer and the dielectric layer covering the gate and the substrate, further comprising: forming a contact hole etch stop layer on the substrate And between the interlayer dielectric layers. The semiconductor process of claim 16, wherein the substrate comprises a substrate block. The semiconductor process of claim 16, wherein the substrate comprises a substrate and at least one fin structure on the substrate, and the gate and the source/drain region are formed on the fin structure. on. For example, in the semiconductor process described in claim 16, the number of the MOS transistors is plural, and the layout of the MOS transistors forms a static random access memory (SRAM). The semiconductor process of claim 16, wherein the epitaxial structure comprises a strained epitaxial structure. The semiconductor process of claim 16, wherein the epitaxial structure is formed in each of the contact holes, respectively, and the epitaxial structure filling portion is formed respectively. Divide each of these contact holes. The semiconductor process of claim 16, wherein forming a plurality of contact holes further comprises simultaneously forming a gate contact hole in the dielectric layer to expose the gate.