TWI524472B - Resistor and manufacturing method thereof - Google Patents

Description

Resistance and manufacturing method thereof

The invention relates to a resistor and a manufacturing method thereof, in particular to a resistor integrated with a transistor having a metal gate and a manufacturing method thereof.

In the semiconductor industry, in order to improve the operational efficiency of the transistor, there has been a way of using metal as a transistor to control the gate. The metal gate has the advantages of low resistance and no depletion effect, and can improve the shortcomings such as poor operation performance caused by the use of high-resistance polysilicon material in the conventional gate. The metal gate can be roughly divided into a gate first process and a gate last process, wherein the back gate process is in accordance with the thermal budget of the metal material and provides a wider material selection. Gradually replaced the front gate process.

In addition, in the integrated circuit, it is often necessary to add settings of other circuit components such as resistors to perform functions such as voltage stabilization or noise filtering. The main body of the resistor is generally made of polycrystalline germanium, doped regions or metal oxides.

Due to the high complexity of the integrated circuit process and the high precision of various component products, in addition to trying to improve the process technology, the demand for process integration is also an important part in the pursuit of improvement in yield. Reduce process steps while increasing productivity. Therefore, there is still a need in the industry for a method of fabricating a transistor that successfully integrates a resistor and has a metal gate.

Accordingly, the present invention provides an integrated resistor and a method of fabricating a transistor having a metal gate.

According to the patent application scope provided by the present invention, a method for fabricating a transistor and a resistor having a metal gate is provided. The fabrication method first provides a substrate, and the substrate defines a transistor region and a resistance region. Next, a transistor and a resistor are respectively formed in the transistor region and the resistor region, and the transistor has a dummy gate. Subsequently, the dummy gate and a portion of the resistor are removed to form a first trench and two second trenches respectively in the transistor and the resistor, and respectively in the first trench and the second trench At least one high dielectric constant gate dielectric layer is formed. Thereafter, a metal gate and a metal structure are respectively formed in the first trench and the second trenches.

According to the scope of the invention provided by the present invention, there is further provided a resistor comprising a substrate, a polysilicon portion disposed on the substrate, and a metal portion, the metal portions being respectively disposed at opposite ends of the polysilicon portion And the bottoms of the metal portions respectively comprise a U-type high dielectric constant material layer.

According to the integrated manufacturing method of the transistor and the resistor having the metal gate provided by the invention, the resistor and the transistor having the metal gate can be integrated without increasing the complexity of the process. In addition, since the resistor has a metal portion, in the subsequent fabrication of the contact plug, the material selection of the contact plug can be increased due to less material contact with the contact plug, and the process window can be improved. More importantly, the resistance itself has a high thermal stability of the metal portion, so that the stability and electrical performance of the resistor can be further improved.

Please refer to FIG. 1 to FIG. 8 . FIG. 1 to FIG. 8 are schematic diagrams showing a preferred embodiment of a method for fabricating a transistor and a resistor having a metal gate according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100 having a transistor region 102 and a resistive region 104 defined therein. The substrate 100 is formed with a plurality of shallow electrodes for providing electrical isolation. Shallow trench isolation (STI) 106. As shown in FIG. 1, the resistor region 104 includes an STI 106 for use as a place for the resistor element to be placed. Next, a dielectric layer 107, a polysilicon layer 108, and a patterned hard mask 110 are sequentially formed on the substrate 100. The patterned hard mask 110 is used to define a gate position of a transistor element and a gate. The position at which the resistive element is formed. The dielectric layer 107 formed between the substrate 100 and the polysilicon layer 108 may comprise a general dielectric material such as hafnium oxide.

Please refer to Figure 2. Subsequently, an etching process is performed, using the patterned hard mask 110 as an etch mask to etch the polysilicon layer 108 and the dielectric layer 107, and forming a dummy gate 112 in the transistor region 102 and the resistor region 104, respectively. With a resistor 114. Next, a lightly doped drain (LDD) 120 is formed in the substrate 100 on both sides of the dummy gate 112, and after the LDD 120 is formed, the dummy gate 112 and the resistor are connected. A side wall 122, 124 is formed on each side wall of the 114. Then, a source/drain 126 is formed on both sides of the dummy gate 112, especially the substrate 100 on both sides of the sidewall 122 to complete the fabrication of a transistor 130, and the transistor 130 has a dummy gate. Extreme 112. In addition, a metal telluride 128 may be formed on the surface of the source/drain 126 of the transistor 130, respectively. After the fabrication of the transistor 130 and the resistor 114 is completed, a contact etch stop layer (CESL) 140 covering the transistor 130 and the resistor 114 is sequentially formed on the substrate 100 and an inner dielectric is formed. (inter-layer dielectric, ILD) layer 142. The fabrication steps and material selection of the above-mentioned components, and even the source/drain 126 formed by the selective epitaxial growth (SEG) method in the semiconductor industry to provide a stress-improving electrical performance and improve the electrical performance are Those in the field are well known and will not be described here.

Please refer to Figure 3. After forming the CESL 140 and the ILD layer 142, a portion of the CESL 140, the ILD layer 142, and the partially patterned hard mask 110 are removed by a planarization process, and then an etching process, such as a dry etching process, is further utilized. In addition to patterning the hard mask 110, the dummy gate 112 of the transistor 130 and the resistor 114 are exposed. Subsequently, another patterned hard mask 144 is formed on the substrate 100 that covers a portion of the resistor 114 to expose both ends of the resistor 114. After forming the patterned hard mask 144, the dummy gate 112 of the transistor 130 and the exposed resistor 114 are removed by a suitable etching process, and a first trench 146 is formed in the transistor 130 while the resistor is A second trench 148 is formed at each end of the 114. It should be noted that the preferred embodiment is a post-gate process and a high-k last process integration. Therefore, when the dummy gate 112 of the transistor 130 and a portion of the resistor 114 are removed, The dielectric layer 107 is used to protect the underlying substrate 100 and is exposed to the bottom of the first trench 146 and the second trench 148 after removing the dummy gate 112 of the transistor 130 and a portion of the resistor 114.

Please refer to Figure 4. After forming the first trench 146 and the second trench 148, the dielectric layer 107 exposed to the bottom of the first trench 146 and the second trench 148 can serve as an interfacial layer. Then, the patterned hard mask 144 is removed, and a high dielectric constant (high dielectric constant layer hereinafter referred to as high-k) gate dielectric layer 150 and a bottom barrier layer are sequentially formed on the substrate 100. Layer) (not shown). The high-k gate dielectric layer 150 can be a metal oxide layer, such as a rare earth metal oxide layer. The high-k gate dielectric layer 150 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST). The bottom barrier layer may include titanium nitride (TiN), but is not limited thereto. In addition, after forming the high-k gate dielectric layer 150 and the bottom barrier layer, an etch stop layer (not shown) may be formed on the bottom barrier layer, which may include tantalum nitride (TaN). , but not limited to this.

Please continue to see Figure 4. Next, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process is performed to form a work function metal layer 152 in the first trench 146 and the second trench 148. The work function metal layer 152 may be a p-type work function metal layer having a p-type conductivity type or an n-type work function metal layer having an n-type conductivity type depending on the conductivity type of the transistor 130. In addition, the work function metal layer 152 may be a single layer structure or a composite layer structure.

Please still refer to Figure 4. Next, a barrier layer 154 is formed on the substrate 100, which may include a photoresist material, but is not limited thereto. The barrier layer 154 is formed in the first trench 146 and the second trench 148. More importantly, the height of the barrier layer 154 is lower than the depth of the first trench 146 and the second trench 148. In other words, the surface of the barrier layer 154 is lower than the opening of the first trench 146 and the second trench 148.

Please refer to Figure 5. Subsequently, an etching process is performed to remove the work function metal layer 152 and the high-k gate dielectric layer 150 that are not covered by the barrier layer 154 with a suitable etchant. As shown in FIG. 5, after the etching process, the high-k gate dielectric layer 150 and the work function metal layer 152 comprise a U-shaped shape, and the U-type high-k gate dielectric layer 150 and the U-type work function. The highest portion of one of the metal layers 152 is lower than the openings of the first trench 146 and the second trench 148. In other words, the high-k gate dielectric layer 150 and the work function metal layer 152 remain only in the first trench 146 and the second trench 148, particularly the bottom and sidewalls of the first trench 146 and the second trench 148. By this etching process, the high-k gate dielectric layer 150 does not completely cover the second trench 148, so that a complete conduction path of the subsequently formed metal layer can be provided. In addition, a high-k gate dielectric layer is formed. The overhang (not shown) formed by the opening of the first trench 146 when the work function metal layer 152 is formed can be removed by the etching process described above, so that the filling ability of the subsequent metal film layer can be increased.

Please refer to Figure 6. Next, the first trench 146 and the barrier layer 154 in the second trench 148 are removed, and a filler metal layer 156 is formed on the work function metal layer 152 in the first trench 146 and the second trench 148. In addition, a top barrier layer (not shown) may be disposed between the work function metal layer 152 and the fill metal layer 156, and the top barrier layer may include TiN, but is not limited thereto. The fill metal layer 156 is used to fill the first trench 146 and the second trench 148, and may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (aluminum, Al), titanium aluminide ( Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto.

Please refer to Figure 7. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 156 to complete the fabrication of a metal gate 162, and a transistor having a metal gate 162 is formed in the transistor region 102. 130. More importantly, while the metal gate 162 is completed, a metal structure 164 is formed in the second trench 148 of the resistor region 104, and a polysilicon portion 108 and two metal portions are formed in the resistor region 104. Resistor 114 of 164. As shown in FIG. 7, the metal portions 164 of the resistor 114 are respectively disposed at both ends of the polysilicon portion 108, and a U-shaped work function metal layer 152 and a U-type high having a highest portion lower than the surface of the metal portion 164 are formed at the bottom portion thereof. -k gate dielectric layer 150. In addition, in this embodiment, the ILD layer 142 and the CESL 140 and the like can be selectively removed, and then the CESL and the dielectric layer are reformed to effectively improve the electrical performance of the transistor. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

Please refer to Figure 8. Next, a dielectric layer 170 is formed on the substrate, preferably a composite film layer, and a plurality of first contact plugs 172 and two second contact plugs 174 are formed in the dielectric layer 170, and the first contact plugs are formed. The plug 172 is electrically connected to the metal gate 162 of the transistor 140 and the source/drain 126; and the second contact plug 174 is electrically connected to the two metal portions 164 of the resistor 114. It should be noted that, in the preferred embodiment, the metal portion 164 at both ends of the resistor 114 has the same composite metal film layer as the metal gate 162. Therefore, when the contact plug is fabricated, the contact plug only needs two materials. Contact: metal gate 162 and metal portion 164 and metal germanide 128 (formed on the surface of source/drain 126). Compared with the prior art, the contact plug must be different from metal materials (such as metal gates), polysilicon materials (such as polysilicon resistors), and metal tellurides (formed on the source/drain surface of the transistor). Material contact, while limiting the material of the contact plug, this preferred embodiment, the preferred embodiment can simplify the material limitations of the contact plug by reducing the amount of material in contact with the contact plug, ie, increasing the material selection of the contact plug And process window. In addition, since the two ends of the resistor 114 are in contact with the second contact plug 174 as the metal portion 164, the surface resistance (Rs) between the second contact plug 174 and the metal portion 164 is lowered, and the resistor 114 itself The stability can be improved. At the same time, due to the arrangement of the metal portion 164, the thermal stability of the resistor 114 can be further increased.

According to the integrated manufacturing method of the transistor and the resistor having the metal gate provided by the invention, the resistor and the transistor having the metal gate can be integrated without increasing the complexity of the process. In addition, since the resistor has a metal portion, in the subsequent fabrication of the contact plug, the material selection of the contact plug can be increased due to the less material contact with the contact plug, and the process tolerance can be improved. More importantly, the resistance itself has a high thermal stability of the metal portion, so that the stability and electrical performance of the resistor can be further improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . Transistor region

104. . . Resistance zone

106. . . Shallow trench isolation

107. . . Dielectric layer

108. . . Polycrystalline layer

110. . . Patterned hard mask

112. . . Virtual gate

114. . . resistance

120. . . Lightly doped bungee

122, 124. . . Side wall

126. . . Source/bungee

128. . . Metal telluride

130. . . Transistor

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

144. . . Patterned hard mask

146. . . First ditches

148. . . Second ditches

150. . . High dielectric constant gate dielectric layer

152. . . Work function metal layer

154. . . Barrier layer

156. . . Filled metal layer

162. . . Metal gate

164. . . Metal part

170. . . Dielectric layer

172. . . First contact plug

174. . . Second contact plug

1 to 8 are schematic views showing a preferred embodiment of a method for fabricating a transistor and a resistor having a metal gate according to the present invention.

100. . . Base

102. . . Transistor region

104. . . Resistance zone

106. . . Shallow trench isolation

107. . . Dielectric layer

108. . . Polycrystalline layer

114. . . resistance

120. . . Lightly doped bungee

122, 124. . . Side wall

126. . . Source/bungee

128. . . Metal telluride

130. . . Transistor

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

144. . . Patterned hard mask

146. . . First ditches

148. . . Second ditches

Claims (6)

A resistor comprising: a substrate; a polysilicon portion disposed on the substrate; and a second metal portion disposed at each end of the polysilicon portion, the bottom portions of the metal portions each comprising a U-type high dielectric constant material Floor. The resistor of claim 1, wherein the highest portion of the U-type high dielectric constant material layer is lower than the surface of the metal portion. The resistor of claim 1, wherein the metal portion comprises a composite film layer structure. The resistor of claim 3, wherein the metal portion further comprises a work function metal layer and a filler metal layer. The resistor of claim 4, wherein the work function metal layer comprises a U-shaped work function metal layer. The resistor of claim 5, wherein the highest portion of the U-shaped work function metal layer is lower than the surface of the metal portion.