TW201301444A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.

Description

Method for fabricating semiconductor components

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal-gate complementary metal oxide semiconductor (CMOS) transistor device and a method of fabricating the same.

As the size of semiconductor components continues to shrink, the conventional method utilizes a tunneling effect that reduces the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-K) materials have an effective reduction in physical limit thickness and are under the same equivalent oxide thickness (EOT). It effectively reduces the leakage current and achieves the equivalent capacitance to control the channel switch. It is used to replace the traditional germanium dioxide layer or the yttria layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching High-K gate dielectric layer. Control electrode.

However, how to continuously increase the efficiency of semiconductor components even if the high-k gate dielectric layer is used to replace the conventional germanium dioxide or yttrium oxide gate dielectric layer, and the metal gate with matching work function is substituted for the conventional polysilicon gate. And to ensure that its reliability is still the problem that the semiconductor industry wants to solve.

Therefore, the present invention discloses a method for fabricating a dual work function metal gate CMOS device to improve the overall performance of existing components.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device. First, a substrate is provided. The substrate has a first region and a second region, and then a high-k dielectric layer, a barrier layer and a first metal layer are sequentially formed on the surface of the substrate. And then removing the first metal layer of the second region, forming a polysilicon layer and covering the first metal layer of the first region and the barrier layer of the second region, and patterning the polysilicon layer, the first metal layer, the barrier The layer and the high-k dielectric layer respectively form a first gate structure and a second gate structure in the first region and the second region. Finally, a source/drain is formed in the substrate on both sides of the first gate structure and the second gate structure, respectively.

Another embodiment of the present invention provides a method of fabricating a semiconductor device. Firstly, a substrate is provided, the substrate has a first region and a second region, and then a first gate structure and a second gate structure are respectively formed on the first region and the second region to form a dielectric layer. And covering the first gate structure and the second gate structure, performing a first planarization process to remove a portion of the dielectric layer such that the first gate structure and the second gate structure surface are flush with the surface of the dielectric layer, respectively forming a The groove is in the first gate structure and the second gate structure. Forming a high-k dielectric layer and a first metal layer on the dielectric layer and the groove surface of the first region and the second region, removing the first metal layer of the second region, and forming a second metal Laminating the first metal layer of the first region and the surface of the dielectric layer of the second region.

Yet another embodiment of the present invention is directed to a method of fabricating a semiconductor device. First, a substrate is provided. The substrate has a first region and a second region, and then a first gate structure and a second gate structure are respectively formed in the first region and the second region. Forming a dielectric layer and covering the first gate structure and the second gate structure, performing a first planarization process to remove a portion of the dielectric layer to make the first gate structure and the second gate structure surface and the dielectric layer surface Forming a recess in the first gate structure and the second gate structure, sequentially forming a high-k dielectric layer and a metal layer in the first region and the second region And the surface of the groove. Finally, the first metal layer of the second region is removed.

Another embodiment of the present invention is directed to a semiconductor device including a substrate having a first region and a second region; a first gate structure disposed in the first region, the first gate structure Having a first high-k dielectric layer, a first work function layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function layer; a pole structure is disposed in the second region, the second gate structure has a second high-k dielectric layer, a second work function layer, and a second metal layer is disposed on the second high-k dielectric Between the layer and the second work function layer, and the thickness of the second metal layer is lower than the thickness of the first metal layer; a first source/drain is disposed on the substrate on both sides of the first gate structure And a second source/drain is disposed in the substrate on both sides of the second gate structure.

Please refer to FIG. 1 to FIG. 9 . FIG. 1 to FIG. 9 are schematic diagrams showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention. In the present embodiment, the semiconductor device is preferably a CMOS transistor, and the preferred embodiment uses a gate-last process in conjunction with a high-k first process. As shown in FIG. 1, a substrate 100 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. A first region and a second region are defined on the substrate 100, such as a PMOS region 104 and an NMOS region 102, and a plurality of shallow trench isolations for providing electrical isolation of the two transistor regions are formed in the substrate 100 (shallow Trench isolation, STI) 106.

Then, an interfacial layer 108 composed of a dielectric material such as an oxide or a nitride is formed on the surface of the substrate 100, and a high-k dielectric layer 110, a barrier layer 112, and a barrier layer 112 are sequentially formed. A stacked film of a metal layer 114 is on the dielectric layer 108.

The high-k dielectric layer 110 may be one or more layers having a dielectric constant of substantially greater than 20. The high-k dielectric layer 110 of the present embodiment may include a metal oxide layer, such as a rare earth. Metal oxide layer, and optionally free hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum) Oxide, AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta ₂ O ₃ ), zirconium oxide (ZrO ₂ ), Zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (lead) Zirconate titanate, PbZr _x Ti _1-x O ₃ , PZT) and a group consisting of barium strontium titanate (BaxSr _1-x TiO ₃ , BST).

The barrier layer 112 is preferably made of titanium nitride (TiN), and the metal layer 114 is preferably made of tantalum nitride (TaN). In the present embodiment, the metal layer 114 is preferably formed on the barrier layer 112 by atomic layer deposition (ALD), and the thickness of the metal layer 114 is between several angstroms and several tens of angstroms, preferably 20 Angstrom.

Next, as shown in FIG. 2, a patterned photoresist layer (not shown) is formed on the metal layer 114, and a pattern transfer process is performed using the patterned photoresist layer as a mask to remove portions of the PMOS region 104. The metal layer 114 is stripped of the patterned photoresist layer to form a patterned metal layer 114 on the NMOS region 102.

Then, as shown in FIG. 3, a polysilicon layer 116 and a hard mask 118 are sequentially formed on the surface of the metal layer 114 and the barrier layer 112, and then a patterned photoresist layer (not shown) is used as a mask. Performing a pattern transfer process to remove portions of the hard mask 118, the polysilicon layer 116, the metal layer 114, the barrier layer 112, the high-k dielectric layer 110, and the dielectric layer 108 by a single etching or successive etching step, and The patterned photoresist layer is stripped to form a first gate structure 120 and a second gate structure 122 on the PMOS region 104 and the NMOS region 102, respectively, as a dummy gate structure.

The polysilicon layer 116 is used as a sacrificial layer, and may also be composed of a polycrystalline germanium material having no undoped, a polycrystalline germanium material having an N+ dopant, or an amorphous germanium material. The hard mask 118 is composed of cerium oxide (SiO ₂ ), cerium nitride (SiN), tantalum carbide (SiC) or cerium oxynitride (SiON).

Then, as shown in FIG. 4, a first sidewall 124 and a second sidewall 126 are formed on sidewalls of the first gate structure 120 and the second gate structure 122, respectively, and the first sidewall 124 and the second sidewall are A lightly doped drain 128 and a source/drain 130 of a corresponding conductivity type are respectively formed in the substrate 100 on both sides of the 126.

Then, a selective epitaxial growth process can be performed on the PMOS and/or the NMOS. For example, an epitaxial layer 132 is formed in the substrate 100 on both sides of the second sidewall 126 in the PMOS region 104. In this embodiment, the epitaxial layer 132 preferably comprises germanium germanium, and may be formed in a single layer or multiple layers; when the epitaxial layer is grown, it may be doped in-situly, and the doping may be performed in a gradual manner (for example) , the bottom layer has no dopant, the first layer is lightly doped, the second layer is thicker, the third layer is rich, ... the top layer has no dopant or light dopant; the hetero atom (in this case) The concentration of germanium atoms can also be changed in a gradual manner, and the concentration thereof will vary depending on the lattice constant and the surface characteristics. However, the surface may be expected to have a lighter germanium atom concentration or no germanium atoms for subsequent germanium formation. In addition, the ion implantation of the source/drain 130 in this embodiment is performed before the epitaxial layer 132, but may be performed after the epitaxial layer 132 is formed according to the process requirements.

Subsequently, a metal telluride process can be performed, for example, forming a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum or a combination thereof on the substrate 100 and covering the source/drain 130 and the epitaxial layer 132, and then reacting the metal layer with the source/drain 130 and the epitaxial layer 132 by using at least one rapid thermal anneal (RTP) process for the NMOS region 102 and the PMOS region 104 A surface of the substrate 100 and the epitaxial layer 132 respectively form a deuterated metal layer 134. Finally, the unreacted metal is removed.

A masking layer 136 is then formed on the surface of the substrate 100 and covers the first gate structure 120 and the second gate structure 122, and then an interlayer dielectric layer 138 is formed on the surface of the substrate 100 and covers the PMOS region 104 and the NMOS region 102. In this embodiment, the capping layer 136 is preferably made of tantalum nitride, and may have different stresses in the PMOS region 104 and the NMOS region 102, and the interlayer dielectric layer 138 is preferably composed of hafnium oxide, and The thickness may range from 1500 to 5000 angstroms, preferably about 3,000 angstroms.

A planarization process is then performed, such as removing a portion of the interlayer dielectric layer 138, the partial mask layer 136, and a portion of the hard mask 118 by a chemical mechanical polishing process and stopping on the polysilicon layer 116. Then, an etching process is performed and the polysilicon layer 116 of the PMOS region 104 and the NMOS region 102 is hollowed out to form a recess 140 in each region. It should be noted that, in this embodiment, although the polycrystalline germanium layer of two regions is simultaneously hollowed out, the polycrystalline germanium layer of one of the regions may be first hollowed out to form a groove and filled with metal, and then another region is removed. The polysilicon layer is filled with metal.

Then, as shown in FIG. 5, a metal layer 142 and a P-type work function metal layer 144 are sequentially deposited on the interlayer dielectric layer 138 and cover the bottom and sidewalls of each of the grooves 140. Then, the metal layer 142 and the P-type work function metal layer 144 at the opening of the recess 140 of the PMOS region 104 are selectively removed, for example, an anti-Reflection Coating (ARC) 146 is integrally formed on the P-type work function. The metal layer 144 is surfaced and filled with recesses 140, and then a patterned photoresist layer 148 is formed over the anti-reflective layer 146 of the NMOS region 102.

Then, an etching process is performed by using the patterned photoresist layer 148 as a mask to remove the anti-reflective layer 146 of the portion of the PMOS region 104, so that the anti-reflective layer 146 partially remaining in the recess 140 serves as a protective layer for protecting the recess 140. The P-type work function metal layer 144 and the metal layer 142 of the bottom and lower sidewalls. Then, an etching process is performed to remove the exposed metal layer 142 and the P-type work function metal layer 144 in the PMOS region 104. Finally, the anti-reflection layer 146 is removed, as shown in FIG.

The metal layer 142 and the P-type work function metal layer 144 at the opening of the recess 140 of the NMOS region 102 are then selectively removed in a manner similar to that described above. For example, an anti-reflective layer 147 is formed comprehensively and fills the recesses 140, and then a patterned photoresist layer 149 is formed on the anti-reflective layer 147 of the PMOS region 104, and then patterned by using the patterned photoresist layer 149 as a mask. The anti-reflective layer 147 of the NMOS region 102 is removed, and the anti-reflective layer 147 partially remaining in the recess 140 serves as a protective layer for protecting the P-type work function metal layer 144 and the metal layer of the bottom and lower sidewalls of the recess 140. 142. Then, an etching process is performed to remove the exposed metal layer 142 and the P-type work function metal layer 144 in the NMOS region 102. Thereafter, as shown in FIG. 7, the anti-reflective layer 147 remaining in the recess 140 of the NMOS region 102 and the remaining P-type work function metal layer are sequentially removed by the protection of the patterned photoresist layer 149 of the PMOS region 104. 144. Finally, all of the patterned photoresist layer 149 and the anti-reflective layer 147 are removed. So far, the bottom and lower half sidewalls of the recess 140 of the PMOS region 104 have a metal layer 142 and a P-type work function metal layer 144, and the bottom and lower sidewalls of the recess 140 of the NMOS region 102 have only the metal layer 142, and The height of the metal layers is less than the depth of each of the grooves 140.

Then, the above steps may be repeated to form an N-type work function metal layer 150 on the surface of the P-type work function metal layer 144 in the recess 140 of the NMOS region 102. Finally, in FIG. 8, a low-resistance conductive layer 152 is formed to fill the recess. The trench 140 is subjected to one or more planarization processes to planarize the NMOS and the PMOS together, for example, by a chemical mechanical polishing process and a portion of the low-impedance conductive layer 152, and a portion of the N-type and P-type work function metal layers 150. And a portion of the metal layer 142 and the portion of the interlayer dielectric layer 138 to form a first metal gate 154 and a second metal gate 156 in the PMOS region 104 and the NMOS region 102, respectively.

In the present embodiment, the metal layer 142 is preferably composed of TaN and has a thickness of several angstroms to ten angstroms, preferably about 10 angstroms. The P-type work function metal layer 144 is a metal that satisfies the required work function of the P-type transistor, and is, for example, titanium nitride (TiN) or tantalum carbide (TaC), but not limited to the above. . The N-type work function metal layer 150 is a metal that satisfies the required work function of the N-type transistor, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl). Or aluminum bismuth (HfAl), but not limited to the above. In addition, the low-impedance conductive layer 152 includes aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), A composite metal layer such as titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN), but is not limited thereto.

It should be noted that, in the above embodiment, although the high-k first process is used to complete the fabrication of the semiconductor device, the spirit of the present invention can be applied to the post-high-k dielectric layer (high- k last) Process, which is also within the scope of the present invention.

For example, as shown in FIG. 9, a dummy gate structure as shown in FIG. 3 may be formed on the substrate 100, wherein the dummy gate includes only a dielectric layer, a polysilicon layer, and a hard mask. It does not have a high dielectric constant dielectric layer and a barrier layer. Then, the process of FIG. 4 is sequentially performed, including forming a first sidewall portion 124 and a second sidewall spacer 126 around the dummy gate, and forming the substrate in the substrate 100 on both sides of the first sidewall spacer 124 and the second sidewall spacer 126. Corresponding to the light-doped drain 128 and the source/drain region 130 of the conductive type, forming a contact etch stop layer 136 and the interlayer dielectric layer 138 on the surface of the dummy gate and the substrate 100, and removing portions by the planarization process The contact hole etch stop layer 136 and the interlayer dielectric layer 138 are contacted and the polysilicon layer or the like in the dummy gate is hollowed out. Then, as shown in FIG. 9, a high-k dielectric layer 110, a barrier layer 112, and a first metal layer 114 are sequentially formed in the recesses of the PMOS region 104 and the NMOS region 102, and then the PMOS is removed. The first metal layer 114 of the region 104 is further formed with a second metal layer 142 on the NMOS region 102 and the interlayer dielectric layer 138 of the PMOS region 104.

The first metal layer 114 and the second metal layer 142 are preferably made of TaN. The thickness of the first metal layer 114 is between several angstroms and several tens of angstroms, preferably 20 angstroms, and the thickness of the second metal layer 142 is between Preferably, the number of angstroms to ten angstroms is 10 angstroms. Since the first metal layer 114 of the PMOS region 104 has been removed first, the total thickness of the TaN of the NMOS region 102 is, for example, about 30 angstroms and the TaN thickness of the PMOS region 104 is, for example, only about 10 angstroms.

It should be noted that, according to another embodiment of the present invention, if the thickness of the first metal layer deposited at the beginning is 30 angstroms, only one etching process is required to remove the first metal layer of the PMOS region 104 without A second metal layer is formed. According to this process, the NMOS region 102 has a 30 angstrom TaN metal layer and the PMOS region 104 does not have any TaN metal layer.

Then, an N-type work function metal layer 150 and a P-type work function metal layer 144 are respectively formed in the NMOS region 102 and the PMOS region 104 according to the first embodiment to form a low-impedance conductive layer 152 on the P-type work function metal layer. The 144 and N-type work function metal layers are filled with recesses and another planarization process is performed to form a metal gate 154, 156 in the NMOS region 102 and the PMOS region 104, respectively.

In summary, since the TaN metal layer deposited in the general metal gate transistor process easily affects the work function metal layer of the PMOS transistor, the present invention preferably precedes or after forming the dummy gate formed by the polysilicon. At least a portion of the TaN metal layer of the PMOS region is removed by etching to minimize the thickness of the TaN metal layer of the PMOS region, so that the component performance of the PMOS transistor is not affected. According to an embodiment of the present invention, a TaN metal layer may be deposited and a TaN metal layer may be removed at a time point before or after forming a dummy gate, and optionally a TaN metal layer may be deposited twice to remove a TaN metal layer of a portion of the PMOS region. The fabrication of the semiconductor device is completed by depositing only a TaN metal layer and then completely removing the TaN metal layer of the PMOS region.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . NMOS region

104. . . PMOS area

106. . . Shallow trench isolation

108. . . Dielectric layer

110. . . High dielectric constant dielectric layer

112. . . Barrier layer

114. . . Metal layer

116. . . Polycrystalline layer

118. . . Hard mask

120. . . First gate structure

122. . . Second gate structure

124. . . First side wall

126. . . Second side wall

128. . . Lightly doped bungee

130. . . Source/bungee

132. . . Epitaxial layer

134. . . Deuterated metal layer

136. . . Cover layer

138. . . Interlayer dielectric layer

140. . . Groove

142. . . Metal layer

144. . . P type work function metal layer

146. . . Antireflection layer

147. . . Antireflection layer

148. . . Patterned photoresist layer

149. . . Patterned photoresist layer

150. . . N-type work function metal layer

152. . . Low impedance conductive layer

154. . . First metal gate

156. . . Second metal gate

1 to 9 are schematic views showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention.

100. . . Base

102. . . NMOS region

104. . . PMOS area

106. . . Shallow trench isolation

108. . . Dielectric layer

110. . . High dielectric constant dielectric layer

112. . . Barrier layer

114. . . Metal layer

124. . . First side wall

126. . . Second side wall

128. . . Lightly doped bungee

130. . . Source/bungee

132. . . Epitaxial layer

134. . . Deuterated metal layer

136. . . Cover layer

138. . . Interlayer dielectric layer

142. . . Metal layer

144. . . P type work function metal layer

150. . . N-type work function metal layer

152. . . Low impedance conductive layer

154. . . First metal gate

156. . . Second metal gate

Claims (25)

A method of fabricating a semiconductor device, comprising: providing a substrate having a first region and a second region; sequentially forming a high-k dielectric layer, a barrier layer, and a first metal layer a surface of the substrate; removing the first metal layer of the second region; forming a polysilicon layer covering the first metal layer and the barrier layer of the first region; patterning the polysilicon layer, The first metal layer, the barrier layer and the high-k dielectric layer respectively form a first gate structure and a second gate structure in the first region and the second region; and respectively form a source The pole/drain is in the base of the first gate structure and the two sides of the second gate structure. The method of claim 1, wherein the first region comprises an NMOS region and the second region comprises a PMOS region. The method of claim 1, wherein the barrier layer comprises TiN. The method of claim 1, wherein the first metal layer comprises TaN. The method of claim 1, wherein the forming the first gate structure and the second gate structure comprises: forming a sidewall between the first gate structure and the second gate structure, respectively a sidewall formed by the source/drain on both sides of the sidewall; forming a dielectric layer covering the first gate structure and the second gate structure; removing a portion by using a first planarization process The dielectric layer is such that the first gate structure and the surface of the second gate structure are flush with the surface of the dielectric layer; respectively, a recess is formed in the first gate structure and the second gate structure; a second metal layer is formed on the first region and the second region; respectively forming a first work function metal layer and a second work function metal layer on the second metal layer; forming a conductive layer on the first work The function metal layer and the second work function metal layer are filled with the grooves; and a second planarization process is performed to form a metal gate in the first region and the second region, respectively. The method of claim 5, wherein the second metal layer comprises TaN. A method of fabricating a semiconductor device, comprising: providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure in the first region and the first a second region; forming a dielectric layer covering the first gate structure and the second gate structure; performing a first planarization process to remove a portion of the dielectric layer, the first gate structure and the second gate The surface of the pole structure is flush with the surface of the dielectric layer; a recess is formed in the first gate structure and the second gate structure respectively; a high-k dielectric layer and a first metal layer are sequentially formed The dielectric layer and the surface of the recess in the first region and the second region; removing the first metal layer of the second region; and forming the first metal of the second metal layer in the first region a layer and a surface of the dielectric layer of the second region. The method of claim 7, wherein the first region comprises an NMOS region and the second region comprises a PMOS region. The method of claim 7, further comprising forming a barrier layer between the high-k dielectric layer and the first metal layer. The method of claim 9, wherein the barrier layer comprises TiN. The method of claim 7, wherein the first metal layer and the second metal layer comprise TaN. The method of claim 7, wherein the first gate structure and the second gate structure each comprise a polysilicon gate. The method of claim 7, wherein the forming the second metal layer further comprises: forming a first work function metal layer and a second work function metal layer on the second metal layer; forming a Conducting a layer on the first work function metal layer and the second work function metal layer and filling the grooves; and performing a second planarization process to form a metal in the first region and the second region, respectively Gate. A method of fabricating a semiconductor device, comprising: providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure in the first region and the first a second region; forming a dielectric layer covering the first gate structure and the second gate structure; performing a first planarization process to remove a portion of the dielectric layer, the first gate structure and the second gate The surface of the pole structure is flush with the surface of the dielectric layer; a recess is formed in the first gate structure and the second gate structure, respectively; a high-k dielectric layer and a metal layer are sequentially formed thereon The dielectric layer of the first region and the second region and the surface of the recess; and removing the first metal layer of the second region. The method of claim 14, wherein the first region comprises an NMOS region and the second region comprises a PMOS region. The method of claim 14, further comprising forming a barrier layer between the high-k dielectric layer and the first metal layer. The method of claim 16, wherein the barrier layer comprises TiN. The method of claim 14, wherein the first metal layer and the second metal layer comprise TaN. The method of claim 14, wherein the first gate structure and the second gate structure each comprise a polysilicon gate. The method of claim 14, wherein the forming the second metal layer further comprises: forming a first work function metal layer and a second work function metal layer on the second metal layer; forming a Conducting a layer on the first work function metal layer and the second work function metal layer and filling the grooves; and performing a second planarization process to form a metal in the first region and the second region, respectively Gate. A semiconductor device comprising: a substrate having a first region and a second region; a first gate structure disposed in the first region, the first gate structure having a first high dielectric constant a dielectric layer, a first work function layer and a first metal layer are disposed between the first high-k dielectric layer and the first work function layer; a second gate structure is disposed in the second region The second gate structure has a second high-k dielectric layer, a second work function layer, and a second metal layer disposed on the second high-k dielectric layer and the second work function layer And the thickness of the second metal layer is lower than the thickness of the first metal layer; a first source/drain is disposed in the substrate on both sides of the first gate structure; and a second source The /pole is disposed in the substrate on both sides of the second gate structure. The semiconductor device of claim 21, wherein the first region comprises an NMOS region and the second region comprises a PMOS region. The semiconductor device of claim 21, further comprising a barrier layer respectively disposed between the first high-k dielectric layer and the first metal layer and the second high-k dielectric Between the layer and the second metal layer. The semiconductor device of claim 23, wherein the barrier layer comprises TiN. The semiconductor device of claim 21, wherein the first metal layer and the second metal layer comprise TaN.