TWI612666B - Method for fabricating finfet transistor - Google Patents

Abstract

The present invention is directed to a method of making a fin field effect transistor. First, a substrate is provided, and then a fin structure is formed on the substrate to form a first gate structure on the fin structure, and a first epitaxial layer is formed in the fin structure and disposed beside the first gate structure. Forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer, forming a contact hole in the interlayer dielectric layer and exposing the first epitaxial layer to form a germanium mask layer on the first epitaxial layer A contact plug is formed in the layer and in the contact hole.

Description

Method for making fin field effect transistor

The present invention relates to a method of fabricating a fin field effect transistor, and more particularly to a method of forming a silicon cap after forming a contact hole and exposing the epitaxial layer.

In recent years, as various consumer electronic products continue to be miniaturized, the size of semiconductor component designs has been shrinking to meet the trend of high integration, high efficiency, low power consumption, and product demand.

As the size of field effect transistors (FETs) components continues to shrink, the development of conventional planar field effect transistor components has faced process limitations. In order to overcome the process limitation, it has become the mainstream trend to replace the planar transistor component with a non-planar field effect transistor component, such as a fin field effect transistor (Fin FET) component. . Since the three-dimensional structure of the fin field effect transistor element can increase the contact area between the gate and the fin structure, the control of the gate to the carrier channel region can be further increased, thereby reducing the buckling initiation band of the small-sized component. The drain induced barrier lowering (DIBL) effect can be suppressed and the short channel effect (SCE) can be suppressed. Furthermore, since the fin field effect transistor element has a wider channel width at the same gate length, a doubled drain drive current can be obtained. Even the criticality of the transistor component The threshold voltage can also be regulated by adjusting the work function of the gate.

In the conventional fin field effect transistor device process, after the epitaxial layer is formed, a mask layer is additionally formed on the epitaxial layer. However, this process sequence typically causes a bump issue to be created by the gate surface of the polysilicon. Secondly, in the process of fabricating the deuterated metal layer, it is easy to cause encroachment of the liner layer between the gate and the sidewall due to the wet cleaning process performed, and cause problems such as nickel silicide piping. . Therefore, how to improve the existing process to solve the bottleneck encountered above is an important issue today.

The present invention is directed to a method of making a fin field effect transistor comprising the following steps. First, a substrate is provided, and then a fin structure is formed on the substrate to form a first gate structure on the fin structure, and a first epitaxial layer is formed in the fin structure and disposed beside the first gate structure. Forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer, forming a contact hole in the interlayer dielectric layer and exposing the first epitaxial layer to form a germanium mask layer on the first epitaxial layer A contact plug is formed in the layer and in the contact hole.

10‧‧‧Base

12‧‧‧First fin structure

14‧‧‧Second fin structure

16‧‧‧Insulation

18‧‧‧ PMOS transistor area

20‧‧‧ NMOS transistor area

22‧‧‧First gate structure

24‧‧‧Second gate structure

26‧‧‧gate electrode

28‧‧‧hard mask

30‧‧‧Virtual gate

32‧‧‧ gate dielectric layer

34‧‧‧First hard mask

36‧‧‧First side wall

38‧‧‧First epitaxial layer

40‧‧‧Second hard mask

42‧‧‧First side wall

44‧‧‧Second epilayer

46‧‧‧Second side wall

48‧‧‧Oxidation cover

50‧‧‧Source/bungee area

52‧‧‧Source/bungee area

54‧‧‧Contact hole etch stop layer

56‧‧‧Interlayer dielectric layer

58‧‧‧Metal gate

60‧‧‧High dielectric constant dielectric layer

62‧‧‧Work function metal layer

64‧‧‧ Covering layer

66‧‧‧Contact hole

68‧‧‧矽 Covering layer

70‧‧‧Deuterated metal layer

72‧‧‧Contact plug

1 to 14 are schematic views showing a method of fabricating a fin field effect transistor according to a preferred embodiment of the present invention.

In order to disclose the technical essence of the present invention in detail, the embodiments will be described in detail below with reference to the accompanying drawings. 1 to 14 are schematic views showing a method of fabricating a semiconductor device according to a preferred embodiment of the present invention. As shown in Figure 1, a substrate 10 is first provided, For example, a substrate or a blanket insulating (SOI) substrate having a first transistor region defined thereon, such as a PMOS transistor region 18 and a second transistor region, such as an NMOS transistor region 20.

The substrate 10 has at least one first fin structure 12, at least one second fin structure 14 and an insulating layer 16. The bottoms of the fin structures 12, 14 are covered by an insulating layer 16, such as yttrium oxide, to form shallow trench isolation, and a portion of the first fin structure 12 and a portion of the second fin structure 14 are respectively provided with a first A gate structure 22 and a second gate structure 24. The first gate structure 22 and the second gate structure 24 respectively include a gate electrode 26 and a hard mask 28 disposed on the gate electrode 26, and the first gate structure 22 and the second gate structure 24 are adjacent to each other. A plurality of dummy gates 30 are selectively provided. In the subsequently produced transistor element, the overlapping regions between the fin structures 12, 14 by the gate electrodes 26 can serve as channels through which the carriers circulate.

The first fin structure 12 and the second fin structure 14 may be formed by first forming a patterned mask (not shown) on the substrate 10, and then transferring the pattern of the patterned mask through an etching process. Into the substrate 10. Then, corresponding to the structural characteristics of the three-gate transistor element and the double-gate fin-shaped transistor element, the patterned mask can be selectively removed or left, and deposition, chemical mechanical polishing (CMP) can be utilized. And an etch back process to form an insulating layer 16 around the bottom of each of the fin structures 12, 14. In addition, the first fin structure 12 and the second fin structure 14 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 10, and using an epitaxial process. A semiconductor layer is grown on the substrate 10 exposed to the patterned hard mask layer, and the semiconductor layer can serve as the corresponding fin structures 12, 14. Similarly, a patterned hard mask layer can be selectively removed or left, and an insulating layer 16 is formed through the deposition, CMP, and etch back processes to cover the bottom of the fin structures 12, 14. In addition, When the substrate 10 is a silicon-on-insulator (SOI) substrate, a patterned mask can be used to etch a semiconductor layer on the substrate, and a bottom oxide layer under the semiconductor layer is stopped to form each fin structure. The above-described step of forming the insulating layer 16 is omitted.

The gate electrode 26 and the fin structures 12, 14 further include a gate dielectric layer 32, respectively. The material of the gate electrode 26 preferably includes doped or undoped polysilicon, but does not exclude materials selected from metal halides or metals, and the material of the gate dielectric layer 32 is preferably included in this embodiment. A telluride layer, such as hafnium oxide (SiO), tantalum nitride (SiN) or hafnium oxynitride (SiON), but does not exclude dielectric materials that may be selected from high dielectric constants.

Then, as shown in FIG. 2, a first hard mask 34 is integrally formed and covers the first gate structure 22 and the second gate structure 24. In accordance with a preferred embodiment of the present invention, the first hard mask 34 is selected from the group consisting of tantalum carbide (SiC), niobium oxynitride (SiON), tantalum nitride (SiN), niobium nitriding (SiCN), and niobium lanthanum hydride ( A group composed of SiBN) or the like, but is not limited thereto.

As shown in FIG. 3, a patterned photoresist layer (not shown) is formed in the NMOS transistor region 20, and the first hard mask of the PMOS transistor region 18 is removed by using the patterned photoresist layer as a mask. The cover 34 defines a first sidewall 36 around the first gate structure 22 and a first recess (not shown) in the first fin structure 12 adjacent to the first gate structure 22. Then, after the patterned photoresist layer of the NMOS transistor region 20 is removed, a selective epitaxial growth process is performed to form a first epitaxial layer 38 composed of germanium germanium in the first recess.

Then, as shown in FIG. 4, a second hard mask 40 is integrally formed and covers the first gate structure 22 and the second gate structure 24, and the portion of the NMOS transistor region 20 A hard mask 34. In accordance with a preferred embodiment of the present invention, the second hard mask 40 is selected from the group consisting of tantalum carbide (SiC), niobium oxynitride (SiON), tantalum nitride (SiN), niobium oxynitride (SiCN), and niobium lanthanum hydride ( A group composed of SiBN) or the like, but is not limited thereto.

Next, as shown in FIG. 5, a patterned photoresist layer (not shown) is formed in the PMOS transistor region 18, and the second hard mask of the NMOS transistor region 20 is removed by using the patterned photoresist layer as a mask. A second recess (not shown) is formed in the second fin structure 14 around the second gate structure 24 and in the second fin structure 14 adjacent to the second gate structure 24 . Then, after the patterned photoresist layer of the PMOS transistor region 18 is removed, a selective epitaxial growth process is performed to form a second epitaxial layer 44 composed of bismuth phosphide (SiP) in the second recess. .

As shown in FIG. 6, a second sidewall 46 is then formed around the first gate structure 22 and the second gate structure 24. The step of forming the second sidewalls 46 may be compared to the steps of forming the first sidewalls 36, 42 as described above, and will not be further described herein. It should be noted that, in this embodiment, the second sidewall 46 is formed directly on the sidewalls of the first sidewalls 36 and 42. However, the second sidewall 46 is not limited thereto, and may be selected from the first gate before forming the second sidewall 46. Structure 22 and second gate structure 24 remove first sidewalls 36, 42 and this embodiment is also within the scope of the present invention.

Then, as shown in FIG. 7, an oxide seal 48 is first applied to the second sidewall 46, the first gate structure 22, and the second gate structure 24, and then as shown in FIG. The PMOS transistor region 18 and the NMOS transistor region 20 are ion implanted to form a source/drain region. For example, a patterned photoresist layer (not shown) may be overlaid on the NMOS transistor region 20 and a P-type ion implantation process is performed on the PMOS transistor region 18 to be first on both sides of the first gate structure 22. Formed in the epitaxial layer 38 A source/drain region 50. Then, the patterned photoresist layer of the NMOS transistor region 20 is removed, another patterned photoresist layer (not shown) is formed in the PMOS transistor region 18, and an N-type ion implantation is performed on the NMOS transistor region 20 to Another source/drain region 52 is formed in the second epitaxial layer 44 on both sides of the second gate structure 24, and then the patterned photoresist layer of the PMOS transistor region 18 is removed.

After the source/drain region 50 and the source/drain region 52 are formed, the first gate structure 22, the second gate structure 24, and the second sidewall portion 46 are removed by using diluted HF (DHF). Oxidation mask 48. In general, after the formation of the source/drain regions 50, 52 and the removal of the patterned photoresist layer, a wet clean of hydrochloric acid (HCl) is usually used to remove the polymer on the surface of the substrate 10. However, the present invention can utilize the arrangement of the oxidized mask layer 48 to protect the first epitaxial layer 38 and the second epitaxial layer 44 from being affected during the wet cleaning process.

Then, as shown in FIG. 9, a contact etch stop layer (CESL) 54 is deposited and covers the first gate structure 22 and the second gate of the PMOS transistor region 18 and the NMOS transistor region 20. Structure 24 and second side wall 46. A fluid chemical vapor deposition (FCVD) process is then performed to form an interlayer dielectric layer 56 and comprehensively cover the contact hole etch stop layer 54. Subsequently, a planarization process, such as a chemical mechanical polishing (CMP) process, removes a portion of the interlayer dielectric layer 56, the contact hole etch stop layer 54 and the hard mask 28, so that the first gate structure 22 and the first The top of the gate electrode 26 composed of polysilicon in the two-gate structure 24 is approximately flush with the surface of the interlayer dielectric layer 56 and exposed. Another method is to remove a portion of the interlayer dielectric layer 56 by CMP, and stop at the contact hole etch stop layer 54, and then remove a portion of the interlayer dielectric layer 56, the contact hole etch stop layer 54 and the hard mask 28 by dry etching. To make the top of the gate electrode 26 Bare out.

As shown in FIG. 10, a metal gate replacement (RMG) process is performed to form a metal gate 58 in each of the PMOS transistor region 18 and the NMOS transistor region 20, wherein the metal gates 58 are each A high-k dielectric layer 60 and a work function metal layer 62 are included.

In accordance with a preferred embodiment of the present invention, the metal gate replacement process can include a selective dry or wet etch process, such as ammonium hydroxide (NH ₄ OH) or tetramethylammonium Hydroxide (Tetramethylammonium Hydroxide). Etching solution such as TMAH) removes the polysilicon layer in the first gate structure 22 and the second gate structure 24 but does not etch the interlayer dielectric layer 56 to form a recess in each of the transistor regions 18, 20 (not shown) ). Then, a high-k dielectric layer 60 and a suitable work function metal layer 62 are formed in the recess, and then the work function metal layer 62 and the high-k dielectric layer 60 are planarized to form a PMOS transistor. The region 18 and the NMOS transistor region 20 form a metal gate 58 respectively.

In accordance with a preferred embodiment of the present invention, the metal gate replacement process includes a gate first process, a gate last process, a high-k first process, and a back gate. After the process, the gate-high dielectric layer (high-k last) process, or the polysilicon gate process. This embodiment is an example of a transistor formed by a gate dielectric process after a gate process. Therefore, the high-k dielectric layer 60 is preferably a high-k dielectric layer having a U-shaped profile. The material comprises a dielectric material having a dielectric constant greater than 4, for example selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride. , HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O _{3 )} Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT), barium strontium titanate (barium strontium titanate, A group consisting of Ba _x Sr _1-x TiO ₃ , BST), or a combination thereof.

In addition, the method of forming the high-k dielectric layer 60 includes an atomic layer deposition (ALD) process or a metal-organic chemical vapor deposition (MOCVD), but is not limited thereto. . In addition, a dielectric layer (not shown) such as a hafnium oxide layer may be selectively disposed between the substrate 10 and the high-k dielectric layer 60. The metal gate 58 may comprise one or more layers of metal material, for example, including a work function metal layer 62, a barrier layer (not shown), and a low resistance metal layer (not shown). Show). The work function metal layer 62 serves to adjust the work function of the formed metal gate 58 to be suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 62 may be selected from a metal material having a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), and tungsten aluminide. (WAl), tantalum aluminide (TaAl), tantalum aluminide (HfAl) or TiAlC (titanium carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 62 may be used for work The function is 4.8 eV~5.2 eV metal materials, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), but not limited to this. The material of the barrier layer may include materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. The low-resistance metal layer may be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof.

As shown in Fig. 11, a mask layer 64 is then formed over the metal gate 58, wherein the mask layer 64 is preferably formed of an oxide, but is not limited thereto. Then, a plurality of contact holes 66 are formed in the cover layer 64 and the interlayer dielectric layer 56 by a lithography and etching (1P1E) or two lithography and etching (2P2E) processes, and the first epitaxial layer 38 and the second are exposed. Epitaxial layer 44.

Subsequently, as shown in FIG. 12, a germanium mask layer 68 is formed on each of the first epitaxial layer 38 and the second epitaxial layer 44. For example, pure germanium or germanium phosphide, and the germanium cap layer 68 is formed only on the first epitaxial layer 38 and the second epitaxial layer 44 in each contact hole 66.

As shown in Fig. 13, a metallization process is followed, for example, a metal material such as cobalt (Co), titanium (Ti), and/or nickel (Ni) or platinum-nickel alloy (NiPt) may be first filled. A metal layer (not shown) is placed in the contact hole 66 and then subjected to a rapid thermal annealing (RTA) process to react the metal layer with the germanium cap layer 68 to form a germanium metal layer 70. In accordance with a preferred embodiment of the present invention, the germanium masking layer 68 is preferably completely consumed during the germanium metallization process, so that the germanium metallization layer 70 is directly grown on the two epitaxial layers, respectively.

Subsequently, as shown in Fig. 14, a contact plug 72 is formed in each contact hole 66. A method of forming the contact plug 72, for example, sequentially forming a barrier/adhesive layer (not shown), a seed layer (not shown), and a conductive layer (not shown) covering the cover layer on the substrate 10. 64 is filled into the contact hole 66, wherein the barrier/adhesive layer is conformally filled into the contact hole 66, and the conductive layer completely fills the contact hole 66. The barrier/adhesive layer can be used to prevent metal atoms of the conductive layer from diffusing into the surrounding cover layer 64 and to increase adhesion between the conductive layer and the cover layer 64. The material of the barrier/adhesive layer is, for example, tantalum (Ta), titanium (Ti), titanium nitride (TiN), titanium telluride (TaN), tungsten nitride (WN) or any combination thereof such as titanium/ Titanium nitride is formed, but not limited thereto. The material of the seed layer is preferably the same as the material of the conductive layer, and the material of the conductive layer comprises various low-resistance metal materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), tantalum. Materials such as (Nb), molybdenum (Mo), copper (Cu), preferably tungsten or copper, preferably tungsten, form appropriate ohms with the deuterated metal layer 70 or the source/drain regions 50, 52 below. Contact (Ohmic contact). Then, a planarization process such as a chemical mechanical polishing (CMP) process, an etching process, or a combination of the two is performed to remove the barrier/adhesion layer, the seed layer and the conductive layer in the region other than the contact hole 66, so that the remaining conductive layer One of the surfaces is coplanar with one of the surfaces of the cover layer 64, thus completing the fabrication of the plurality of contact plugs 72 and the fin field effect transistor of the preferred embodiment of the present invention.

In summary, the present invention mainly focuses on the formation of the germanium cap layer from the original formation of the epitaxial layer and the completion of the fabrication of the sidewalls to the formation of the contact holes and before the completion of the germanium metal layer. By changing the time point at which the germanium mask layer is formed, the present invention can avoid the occurrence of bumps on the surface of the polysilicon gate, and can simultaneously improve the erosion generated during the process of fabricating the germanium metal layer and the conduction of the nickel halide.

10‧‧‧Base

12‧‧‧First fin structure

14‧‧‧Second fin structure

16‧‧‧Insulation

18‧‧‧ PMOS transistor area

20‧‧‧ NMOS transistor area

36‧‧‧First side wall

38‧‧‧First epitaxial layer

42‧‧‧First side wall

44‧‧‧Second epilayer

46‧‧‧Second side wall

50‧‧‧Source/bungee area

52‧‧‧Source/bungee area

54‧‧‧Contact hole etch stop layer

56‧‧‧Interlayer dielectric layer

58‧‧‧Metal gate

60‧‧‧High dielectric constant dielectric layer

62‧‧‧Work function metal layer

64‧‧‧ Covering layer

70‧‧‧Deuterated metal layer

72‧‧‧Contact plug

Claims (13)

A method for fabricating a fin field effect transistor, comprising: providing a substrate; forming a fin structure on the substrate; forming a first gate structure on the fin structure; before forming the first gate structure Forming a shallow trenches on the substrate and surrounding the fin structure; forming a first epitaxial layer in the fin structure and disposed adjacent to the first gate structure; forming an interlayer dielectric layer on the first a gate structure and the first epitaxial layer; forming a contact hole in the interlayer dielectric layer and exposing the first epitaxial layer; forming a silicon cap after forming the contact hole a first epitaxial layer; and a contact plug is formed in the contact hole. The method for fabricating a fin field effect transistor according to claim 1, wherein the first gate structure comprises: a polysilicon layer disposed on the fin structure and the shallow trench isolation; and a hard mask On the polysilicon layer. The method for fabricating a fin field effect transistor according to claim 2, further comprising: forming the first gate structure on the shallow trench isolation and one of the first transistor regions on the substrate, and a first The second gate structure is separated from the shallow trench by a second transistor region of the substrate; a first hard mask is formed on the first gate structure and the second gate structure; Removing a portion of the first hard mask from the first transistor region to form a first sidewall between the first gate structure and a first recess in the fin structure adjacent to the first gate structure Forming the first epitaxial layer in the first recess; forming a second hard mask on the first gate structure and the second gate structure; removing the second transistor region Forming a second recess around the second gate structure and forming a second recess in the fin structure adjacent to the second gate structure; and forming a second epitaxial layer In the second groove. A method of fabricating a fin field effect transistor according to claim 3, wherein the first transistor region comprises a PMOS region and the second transistor region comprises an NMOS region. The method for fabricating a fin field effect transistor according to claim 3, wherein the first hard mask and the second hard mask are selected from the group consisting of niobium carbide (SiC), niobium oxynitride (SiON), and nitrogen. A group consisting of cerium (SiN), niobium nitriding (SiCN), and lanthanum boride (SiBN). A method of fabricating a fin field effect transistor according to claim 3, wherein the first epitaxial layer comprises antimony telluride and the second epitaxial layer comprises germanium phosphide. The method of fabricating a fin field effect transistor according to claim 3, further comprising removing the first sidewall from the first gate structure and the second gate structure. A method for fabricating a fin field effect transistor as described in claim 3, further comprising: Forming a second sidewall around the first gate structure and the second gate structure; forming an oxide seal on the second sidewall, the first gate structure, and the second gate Structurally, forming a source/drain region adjacent to the first gate structure and the second gate structure; removing the oxidized mask layer; performing a metal gate replacement (RMG) process to Forming a metal gate in each of the first transistor region and the second transistor region; forming a mask layer on the metal gate; forming the contact hole in the cover layer and the interlayer dielectric layer, and borrowing The first epitaxial layer and the second epitaxial layer are exposed; the germanium capping layer is formed on the first epitaxial layer and the second epitaxial layer; and the first epitaxial layer and the second epitaxial layer Forming a deuterated metal layer on the crystal layer; and forming the contact plug in the contact hole. A method of fabricating a fin field effect transistor as described in claim 8 of the patent application, further comprising removing the oxidized mask layer by diluted HF (DHF). The method for fabricating a fin field effect transistor according to claim 8 , wherein the metal gate replacement process comprises: removing the hard mask and the polysilicon layer for the first gate structure and the second gate Forming a recess in the structure; forming a high-k dielectric layer in the recess; depositing a work function metal layer in the recess; and planarizing the work function metal layer and the high dielectric constant And an electrical layer, wherein the metal gate is formed in the first transistor region and the second transistor region, respectively. A method of fabricating a fin field effect transistor as described in claim 8 wherein the mask layer comprises an oxide. The method for fabricating a fin field effect transistor according to claim 8 , wherein the forming the contact plug further comprises: forming a barrier layer in the contact hole; filling a conductive layer in the contact hole; And planarizing the conductive layer and the barrier layer to form a contact plug in the contact hole. A method of fabricating a fin field effect transistor as described in claim 12, wherein the conductive layer comprises tungsten.