TWI543370B - Mos transistor process - Google Patents

Description

MOS transistor process

The present invention relates to a MOS transistor process, and more particularly to a MOS transistor process for forming a trench or/and performing a cleaning process after forming a source/drain and before forming an epitaxial structure.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster.

Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used, which utilizes the lattice constant of the epitaxial structure of germanium (SiGe) or germanium carbon (SiC) and single crystal germanium. (single crystal Si) different characteristics, the epitaxial structure is structurally strained to form strain enthalpy. Since the lattice constant of lanthanum or lanthanum carbon (SiC) is smaller than 矽 or larger than 矽, this causes the band structure of 矽 to change, resulting in increased carrier mobility, thus increasing MOS. The speed of the transistor.

However, the general epitaxial structure may be affected by high temperature or ion implantation, resulting in the epitaxial junction. The constituents in the structure, such as helium or carbon, diffuse outward, thereby reducing the concentration of the constituents of the epitaxial structure and degrading the performance of the epitaxial structure. Furthermore, the surface quality of the substrate in forming the epitaxial structure also affects the shape or cross-sectional structure of the epitaxial structure formed thereon, and these factors may affect the quality of the subsequently formed semiconductor device.

The invention provides a MOS transistor process, which forms an epitaxial structure after forming a source/drain, and forms a groove or a cleaning process after the source/drain and before forming the epitaxial structure, so as to form a subsequent process. The epitaxial structure has better quality.

The present invention provides a MOS transistor process comprising the following steps. First, a gate structure is formed on a substrate. Next, a source/drain is formed in the substrate on the side of the gate structure. Continuing, after forming the source/drain, at least one recess is formed in the substrate on the side of the gate structure. Then, an epitaxial structure is formed in the recess.

The present invention provides a MOS transistor process comprising the following steps. First, a gate structure is formed on a substrate. Next, a source/drain is formed in the substrate on the side of the gate structure. Next, after the source/drain is formed, a cleaning process is performed to clean the surface of the substrate on the side of the gate structure. Then, an epitaxial structure is formed in the substrate on the side of the gate structure.

Based on the above, the present invention proposes a MOS transistor process in which a source/drain is formed first, then a recess or/and a cleaning process is performed, and finally an epitaxial structure is formed. In this way, the present invention can avoid the formation of source/drain source/drain ion implantation process and source/ The composition of the epitaxial structure caused by the gate annealing process is outwardly diffused, which reduces the stress applied to the gate channel by the epitaxial structure and causes leakage current in the gate channel. Furthermore, after forming the source/drain, forming a recess or performing a cleaning process, the substrate damaged on the source/drain formation process or the impurities on the substrate can be removed, thereby improving the protrusion formed thereon. The quality of the crystal structure.

The MOS transistor process provided by the invention can be applied to the front gate (Gate-First) process, the front high dielectric constant gate (Gate-Last for High-K First) process, and the post-high dielectric constant. Gate-Last for High-K Last process. Furthermore, the present invention is exemplified by a planar MOS transistor, but the present invention can also be applied to a non-planar MOS transistor, such as a Fin-shaped field effect transistor (FinFET) and a three-gate field effect. Other multi-gate MOSFETs such as tri-gate MOSFETs. An embodiment is described below, which is exemplified by a planar MOS transistor and a Gate-Last for High-K First process, but the invention is not limited thereto.

1-8 are schematic cross-sectional views showing a process of a MOS transistor according to an embodiment of the present invention. As shown in Fig. 1, first, a substrate 110 is provided. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. Next, an insulating structure 10 may be formed in the substrate 110 to electrically insulate the transistors of the respective regions. 10 cases of insulation structure For example, a shallow trench isolation (STI) structure is formed, for example, by a shallow trench isolation process. The detailed formation method is well known in the art and will not be described again, but the invention is not limited thereto. In the present embodiment, the two transistors M1 and M2 of a common source or a common drain are formed in a region A, but the invention is not limited thereto. In other embodiments, a single transistor or other number of transistors, but not a common source or a common drain, may be formed in region A.

Connecting, forming a buffer layer (not shown), a dielectric layer (not shown), a barrier layer (not shown), an electrode layer (not shown), and a cap layer (not shown) On the substrate 110, five are patterned to form two gate structures G1 and G2 including a buffer layer 122, a dielectric layer 124, a barrier layer 126, an electrode layer 128, and a cap layer 129. Then, a main spacer material (not shown) is covered and etched back to form a main spacer 130 on the substrate 110 on the side of each of the gate structures G1 and G2. The width w1 of the main spacer 130 may determine the distance of the source/drain formed in the substrate 110 from the gate channels C1 and C2.

In the foregoing embodiment, the buffer layer 122 may be an oxide layer, which is formed, for example, by a thermal oxidation process or a chemical oxidation process, but the invention is not limited thereto. The buffer layer 122 is located between the dielectric layer 124 and the substrate 110 for buffering the dielectric layer 124 and the substrate 110. The buffer layer 122 can be selectively formed depending on the material of the dielectric layer 124 and the substrate 110 and the electrical quality of the semiconductor component to be formed. For example, the present embodiment is a gate-Last for High-K First process, so the dielectric layer 124 of the present embodiment is a high-k dielectric layer, which is optional. Hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ) , lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), barium titanate (strontium titanate oxide, SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST) Group, but the invention is not limited thereto. Therefore, the material difference between the dielectric layer 124 and the substrate 110 of the present embodiment can be buffered by the buffer layer 122 formed between the two. However, in other embodiments, such as the Gate-Last for High-K Last process, the dielectric layer 124 may be directly formed on the substrate 110, and the dielectric layer 124 may be An oxide layer is removed in a subsequent process, and then, after a subsequent metal gate replacement process, the dielectric layer 124 is removed and a buffer layer 122 is formed on the substrate 110. Alternatively, the buffer layer 122 may be formed on the substrate 110, the dielectric layer 124 may be formed on the buffer layer 122, and then the dielectric layer 124 may be removed during the metal gate replacement process. It is not necessary to remove the buffer layer 122. In addition, if only a polycrystalline germanium transistor is to be formed, the dielectric layer 124 can be an oxide layer, so that the buffer layer 122 and the barrier layer 126 need not be additionally formed.

The barrier layer 126 is located on the dielectric layer 124 for use as an etch when the electrode layer 128 is removed. The stop layer is engraved to protect the dielectric layer 124 and may prevent the subsequent metal components located thereon from diffusing down to contaminate the dielectric layer 124. The barrier layer 126 is, for example, a single layer structure or a composite layer structure of tantalum nitride (TaN), titanium nitride (TiN), or the like. The electrode layer 128 may be, for example, a sacrificial electrode layer formed of polysilicon, which may be replaced by a metal gate in a subsequent process, but the invention is not limited thereto. The cap layer 129 may be, for example, a single layer or a double layer stack structure composed of a nitride layer or an oxide layer. The cap layer 129 can prevent the structure such as the electrode layer 128 underneath from being damaged during the subsequent etching process. Therefore, the material of the cap layer 129 can be determined by various etching parameters such as an etching solution of the etching process. The main spacers 130 may be, for example, a single layer or a multilayer structure formed of a nitride layer, an oxide layer, or a combination of the two, but the invention is not limited thereto.

Next, as shown in FIGS. 2-3, a source/drain 140 is formed in the substrate 110 on the side of each of the gate structures G1 and G2. In detail, as shown in FIG. 2, a source/drain ion implantation process P1 is first performed, and a main spacer 13 is automatically aligned to form a substrate 110 on the side of the gate structures G1 and G2. Planting area 140'. Then, as shown in Fig. 3, a source/drain annealing process P2 is performed to activate the implant region 140', and a source/drain 140 is formed in the substrate 110 on the side of each of the main spacers 130. Of course, as is well known to those skilled in the art, before forming the main spacers 130, a liner sidewall (not shown) may be selectively formed on the substrate 110 on the side of each of the gate structures G1 and G2, and then automatically A lightly doped source/drainage (not shown) is formed quasi-ground.

Subsequently, the main spacers 130 are removed, and as shown in FIG. 4, the sidewalls of the gate structures G1 and G2 are exposed. Since the source/drain 140 is automatically aligned with the topography by the main spacers 130 Therefore, the distance d1 between the source/drain 140 and each of the gate structures G1 and G2 is the width w1 of the main spacer 130 shown in the previous figures. Therefore, the distance d1 can be controlled by adjusting the width w1 of the main spacer 130. In the present embodiment, the main spacers 130 are all removed, but in other embodiments, only a portion of the main spacers 130 may be removed, or the main spacers 130 may not be removed. Then, an epitaxial spacer is formed on the substrate 110 on the side of the remaining main spacer 130 in the subsequent process.

As shown in FIGS. 5-6, an epitaxial spacer 150 is formed on the substrate 110 on the side of each of the gate structures G1 and G2. In detail, as shown in Fig. 5, an epitaxial spacer material 150' is first covered on the gate structures G1 and G2 and the substrate 110. As further shown in FIG. 6, an etching process P3 is performed to etch the epitaxial spacer material 150' to form an epitaxial spacer 150 on the substrate 110 of each of the gate structures G1 and G2. In the present embodiment, the etching process P3 not only etches the epitaxial spacer material 150' to form the epitaxial spacers 150, but the etching process P3 further forms the recesses R in the substrate 110 on the side of the epitaxial spacers 150. As such, the purpose of forming the recesses R is to remove the lattice-damaged substrate 110 in the foregoing process, particularly in the source/drain ion implantation process P1. For example, if the depth of the implanted region 140' formed by the source/drain ion implantation process P1 is 50 angstroms (Å, angstrom), the groove R is preferably controlled to have about 50 to 65 angstroms (Å, angstrom). The depth of the substrate 110 can be removed such that the epitaxial structure subsequently formed in the recess R can be crystallized by the crystallographically intact substrate 110 to have a better cross-sectional structure and shape. In other embodiments, the etching process for forming the recess R and the epitaxial spacer 150 may be formed by different etching processes and segmented, and the depth of the formed recess R may be determined according to actual needs, for example, the subsequent formed Lei The material or characteristics of the crystal structure, depending on. For example, when The epitaxial structure is a carbon-phosphorus (SiCP) epitaxial structure, and the depth of the groove R is preferably about 400 to 500 angstroms (Å, angstrom). Moreover, the width w2 of one of the epitaxial spacers 150 determines the distance of the epitaxial structure formed in the side substrate 110 from the gate structures G1 and G2. In the present embodiment, the width w2 of the epitaxial spacers 150 is smaller than the width w1 of the main spacers 130 of the previous figures. Therefore, the groove R is closer to the gate channels C1 and C2 than the source/drain 140, so that the epitaxial structure formed later in the groove R can be closer to the gate channels C1 and C2. In this way, the stress applied to the gate channels C1 and C2 by the epitaxial structure can be increased, but the source/drain 140 can be prevented from being too close to the gate channels C1 and C2, causing a leakage current due to the electron tunneling effect.

In other embodiments, the distance between the epitaxial structure relative to the gate channels C1 and C2 and the distance between the source/drain 140 and the gate channels C1 and C2 may be adjusted as needed. For the adjustment method, for example, the distance between the source/drain 140 and the gate channels C1 and C2 may be determined by the width w1 of the main spacer 130. Then, the main spacers 130 are removed in whole or in part, or the main spacers 130 are not removed to form the epitaxial spacers 150 at the position of the original main spacers 130 or/and on the substrate 110 on the sides of the main spacers 130. . At this time, the remaining main spacer 130 plus the width W2 of the epitaxial spacer 150 can control the distance of the epitaxial structure from the gate channels C1 and C2.

As shown in FIG. 7, a cleaning process P4 is performed to clean the surface S of the recess R to remove the etching residue and the native oxide thereon, so that the epitaxial structure formed later in the recess R has The shape and cross-sectional structure are better, and the semiconductor element formed thereby has better electrical quality. The cleaning process P4 may comprise a standard cleaning (SC1) process or / and a distillate hydrofluoric acid Cleaning process. In one embodiment, a standard cleaning (SC1) process may be performed to first oxidize a portion of the surface S of the groove R, and then a cleaning process containing dilute hydrofluoric acid. Together, the oxides and other impurities of the surface S are removed, and the surface S of the groove R is repaired, but the invention is not limited thereto. In this embodiment, a first standard cleaning (Standard Clean 1, SC1) process, a dilute hydrofluoric acid cleaning process, and a second standard cleaning (Standard Clean 1, SC1) are sequentially performed. )Process. Specifically, a standard cleaning (SC1) process may be initially performed by cleaning a plurality of wafers at a time, and the process temperature is preferably 70 ° C and the process time is 60 seconds; then, the cleaning is performed once. A single wafer method for performing a cleaning with dilute hydrofluoric acid, the process time is preferably 15 seconds, and the second standard cleaning process is performed by cleaning a single wafer at a time. The temperature is preferably 60 ° C and the process time is 90 seconds.

As shown in FIG. 8, an epitaxial process P5 is performed to form an epitaxial structure 160 in the recess R. The epitaxial structure 160 can be, for example, a germanium-phosphorus (SiP) epitaxial structure, a germanium (SiGe) epitaxial structure, or a germanium carbon-phosphorus (SiCP) epitaxial structure, but the invention is not limited thereto. Depending on the type of crystal. In this embodiment, the epitaxial structure 160 is a germanium-phosphorus (SiP) epitaxial structure of an NMOS transistor. The components of the epitaxial structure 160, especially the phosphorous component, diffuse outward during high temperature processing or ion implantation processes, and are highly sensitive to ion implantation or high temperature. The epitaxial structure 160 of the present invention is formed after the source/drain 140, so that the source/drain ion implantation process P1 and the source/drain annealing process P2 for forming the source/drain 140 are not experienced, thereby avoiding the Lei The components in the crystal structure 160 are expanded outward Dispersing, which reduces the stress applied by the epitaxial structure 160 to the gate channels C1 and C2, and may cause leakage currents in the gate channels C1 and C2. Furthermore, the epitaxial structure 160 is additionally doped therein, and the epitaxial structure 160 can be made conductive, wherein the dopant can be, for example, boron or phosphorous, depending on the electrical properties to be formed. The dopant may be in-situ doped into the epitaxial structure 160 during the epitaxial process P5, or the dopant in the source/drain 140 may enter the epitaxial structure 160 by diffusion or the like. Or, after the epitaxial structure 160 is formed, the epitaxial structure 160 is additionally deposited by, for example, ion implantation.

According to the invention, after the source/drain 140 is formed, the recess R is formed in the substrate 110 on the side of the gate structures G1 and G2, and then the cleaning process P4 is performed to clean the surface S of the recess R, and finally An epitaxial structure 160 is formed. In this way, the epitaxial structure 160 can avoid the formation of the ion implantation process of the source/drain 140 and the high temperature of the annealing process. Moreover, the recess R is formed after the source/drain 140 is formed, and the substrate 110 in the damaged portion in the process of forming the source/drain 140 and the like can be removed, thereby improving the quality of the epitaxial structure 160 formed thereon. . In addition, the cleaning process P4 is performed after the groove R is formed, so that the surface S of the groove R can be cleaned, and the quality of the epitaxial structure 160 formed thereon can be improved.

However, after the source/drain 140 is formed, the recess R is formed and then the cleaning process P4 is performed. Finally, the step of forming the epitaxial structure 160 is only one embodiment of the present invention. The formation of the recess R and the cleaning process P4 can improve the surface of the substrate 110, thereby improving the quality of the epitaxial structure 160. Therefore, the present invention can form only the groove R or only the cleaning process P4 after forming the source/drain 140, and then form the epitaxial structure 160. This also achieves the object of the invention. Of course, the groove R is used for cleaning first. The method of the process P4 can improve the quality of the epitaxial structure 160 more than only one of them.

In summary, the present invention proposes a MOS transistor process in which a source/drain is formed first, then a recess or/and a cleaning process is performed, and finally an epitaxial structure is formed. In this way, the present invention can avoid the outward diffusion of components in the epitaxial structure caused by the source/drain source/drain ion implantation process and the source/drain annealing process, which reduces the epitaxial structure applied to The stress in the gate channel and the leakage current in the gate channel. Furthermore, after the source/drain is formed, a recess is formed to remove the substrate of the damaged portion in the process of forming the source/drain, thereby improving the quality of the epitaxial structure formed thereon. Alternatively, after the source/drain is formed, a cleaning process may be performed, and impurities on the surface of the substrate may be cleaned to improve the quality of the epitaxial structure formed thereon. What is more, the preferred embodiment is that after the source/drain is formed, the groove is formed and then the cleaning process is performed, and finally the epitaxial structure is formed.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Insulation structure

110‧‧‧Base

122‧‧‧buffer layer

124‧‧‧ dielectric layer

126‧‧‧Barrier layer

128‧‧‧electrode layer

129‧‧‧ cover

130‧‧‧Main spacer

140‧‧‧Source/Bungee

140’‧‧·planting area

150‧‧‧Elobite spacer

150'‧‧‧Elevation spacer material

160‧‧‧ epitaxial structure

A‧‧‧ area

C1, C2‧‧‧ gate channel

D1‧‧‧ distance

G1, G2‧‧‧ gate structure

M1, M2‧‧‧ transistor

P1‧‧‧ source/dipper ion implantation process

P2‧‧‧ source/drain annealing process

P3‧‧‧ etching process

P4‧‧‧cleaning process

P5‧‧‧Exploring process

R‧‧‧ groove

S‧‧‧ surface

W1, w2‧‧‧ width

1-8 are schematic cross-sectional views showing a process of a MOS transistor according to an embodiment of the present invention.

10‧‧‧Insulation structure

110‧‧‧Base

122‧‧‧buffer layer

124‧‧‧ dielectric layer

126‧‧‧Barrier layer

128‧‧‧electrode layer

129‧‧‧ cover

140‧‧‧Source/Bungee

150‧‧‧Elobite spacer

160‧‧‧ epitaxial structure

C1, C2‧‧‧ gate channel

G1, G2‧‧‧ gate structure

P5‧‧‧Exploring process

R‧‧‧ groove

S‧‧‧ surface

Claims (20)

An MOS transistor process includes: forming a gate structure on a substrate; forming a source/drain in the substrate on a side of the gate structure; forming at least one recess after forming the source/drain Slotted in the substrate on the side of the gate structure; and forming an epitaxial structure in the recess. The MOS transistor process of claim 1, wherein the step of forming the source/drain includes: performing a source/drain ion implantation process in the substrate on a side of the gate structure to form a planting zone; and performing a source/drain annealing process to activate the implant zone to form the source/drain. The MOS transistor process of claim 1, wherein after forming the recess and before forming the epitaxial structure, further comprising: performing a cleaning process to clean the surface of the recess. The MOS transistor process of claim 3, wherein the cleaning process comprises a standard cleaning (SC1) process or/and a cleaning process containing dilute hydrofluoric acid. For example, the MOS transistor process described in claim 4, wherein the cleaning system The process includes a first standard cleaning (Standard Clean 1, SC1) process, a dilute hydrofluoric acid cleaning process, and a second standard cleaning (SC1) process. The MOS transistor process of claim 5, wherein the process temperature of the first standard cleaning process is 70 ° C and the process time is 60 seconds, and the process time of the cleaning process containing the diluted hydrofluoric acid is 15 seconds. And the process temperature of the second standard cleaning process is 60 ° C and the process time is 90 seconds. The MOS transistor process as described in claim 5, wherein the first standard cleaning process is to clean a plurality of wafer processes at a time, the cleaning process containing the diluted hydrofluoric acid and the second standard cleaning process is Clean a single wafer process at a time. The MOS transistor process of claim 1, wherein after forming the gate structure, further comprising forming a main spacer on the substrate on a side of the gate structure, and the source/drain Formed in the substrate on the side of the main spacer wall. The MOS transistor process of claim 8, wherein the step of forming the recess comprises: removing the main spacer; covering an epitaxial spacer material on the gate structure and the substrate; An etching process is performed to form an epitaxial spacer on the substrate on the side of the gate structure and in the substrate forming the recess on the side of the epitaxial spacer. The MOS transistor process of claim 1, wherein the epitaxial structure comprises a germanium-phosphorus (SiP) epitaxial structure, a germanium (SiGe) epitaxial structure or a germanium carbon-phosphorus (SiCP) epitaxial crystal. structure. A MOS transistor process includes: forming a gate structure on a substrate; forming a source/drain in the substrate on a side of the gate structure; and performing a cleaning process after forming the source/drain Cleaning the surface of the substrate on the side of the gate structure; and forming an epitaxial structure in a recess of the substrate on the side of the gate structure. The MOS transistor process of claim 11, wherein the step of forming the source/drain includes: performing a source/drain ion implantation process on the substrate on a side of the gate structure to Forming an implant region; and performing a source/drain annealing process to activate the implant region to form the source/drain. The MOS transistor process of claim 11, wherein the cleaning process comprises a standard cleaning (SC1) process or/and a cleaning process containing dilute hydrofluoric acid. The MOS transistor process as described in claim 13 wherein the cleaning The process includes a first standard cleaning (Standard Clean 1, SC1) process, a dilute hydrofluoric acid cleaning process, and a second standard cleaning (SC1) process. For example, in the MOS transistor process described in claim 14, wherein the process temperature of the first standard cleaning process is 70 ° C and the process time is 60 seconds, the process of the cleaning process containing dilute hydrofluoric acid The time is 15 seconds, and the process temperature of the second standard cleaning (Standard Clean 1, SC1) process is 60 ° C and the process time is 90 seconds. The MOS transistor process of claim 14, wherein the first standard cleaning process is to clean a plurality of wafer processes at a time, the cleaning process containing dilute hydrofluoric acid and the second standard cleaning process is Clean a single wafer process at a time. The MOS transistor process of claim 11, wherein after forming the source/drain and before performing the cleaning process, further comprising: forming the recess in the substrate on a side of the gate structure. The MOS transistor process of claim 11, wherein after forming the gate structure, further comprising forming a main spacer on the substrate on a side of the gate structure, and the source/drain Formed in the substrate on the side of the main spacer wall. The MOS transistor process as described in claim 18, in forming the source / After the bungee and before the cleaning process, the method further includes: removing the main spacer; covering an epitaxial spacer material on the gate structure and the substrate; and performing an etching process to form an epitaxial spacer On the substrate on the side of the gate structure and in the substrate forming the groove on the side of the epitaxial spacer wall. The MOS transistor process of claim 11, wherein the epitaxial structure comprises a germanium-phosphorus (SiP) epitaxial structure, a germanium (SiGe) epitaxial structure or a germanium carbon-phosphorus (SiCP) epitaxial crystal. structure.