CN104425346A - Manufacturing method for fin on insulator - Google Patents
Manufacturing method for fin on insulator Download PDFInfo
- Publication number
- CN104425346A CN104425346A CN201310407815.7A CN201310407815A CN104425346A CN 104425346 A CN104425346 A CN 104425346A CN 201310407815 A CN201310407815 A CN 201310407815A CN 104425346 A CN104425346 A CN 104425346A
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- Prior art keywords
- fin
- substrate
- oxidation
- insulator
- nitrogenize
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method for a fin on an insulator. The manufacturing method comprises the following steps: forming the fin on a substrate; forming a side wall on the side wall of the fin; carrying out anisotropic etching on the substrate and forming a bottom structure under the fin; carrying out isotropic etching on the substrate so as to reduce the width of the bottom structure; and carrying out an oxidization or nitriding process on the bottom structure so as to convert the bottom structure into the insulator. According to the manufacturing method for the fin on the insulator disclosed by the invention, a refined fin line is formed by a special sub-step etching process, and good insulated isolation between the substrate and the fin is formed by oxidizing or nitriding the lower part of the fin, so that the device performance and reliability are improved.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to a kind of method manufacturing FinFET fin in semiconductor on insulator.
Background technology
Along with device size equal proportion is reduced to 22nm technology and following, such as the three-dimensional multi-gate device of FinFET (FinFET) and three grid (tri-gate) device becomes one of the most promising new unit technology, and these structures enhance grid control ability, inhibit electric leakage and short-channel effect.
For traditional handicraft, carry out gate patterns and formed contacting to the cmos device comprising FinFET, tri-gate device, to realize the function element of isolation by following step:
1, adopt wiring-cutting (line-and-cut) two photolithography patterning technology and subsequently etching grid stacking come to gate patterns;
2, uniform characteristics size and pitch is adopted to be used for along a direction printing parallel lines of gate patterns;
3, only grid line end (tip) is arranged at predetermined grid node place;
4, by forming the electroconductive contact holes that between device, after insulating blanket, photoetching and etching are formed for device grids electrode and source/drain.
Said method has some advantages:
1, the photoetching being applicable to special lighting pattern is simplified;
2, the many proximity effects making photoetching, etching and OPC complicated are eliminated.
FinFET is different from planar CMOS device with tri-gate devices, is three-dimension device.Usually, on body substrate or SOI substrate, form semiconductor fin by selectivity dry method or wet etching, then form gate stack across fin.Three-dimensional tri-gate transistors all defines conducting channel on three sides of vertical fin structure, thus provides " fully-depleted " operational mode.Tri-gate transistors also can have multiple fins of coupling together to increase for more high performance total driving force.
But enter 22nm technology node along with FinFET and reduce further, the size of fin becomes more and more less, such as only about 10 ~ 30nm.Even if now adopt the epitaxial growth had good uniformity, the fin size for device source/drain regions is still very little, and this makes to be difficult to form effective contact on these areas.On the other hand, these very undersized fins are also fragile, are very easy to break, particularly for the fin formed on the soi wafer.Therefore, be very difficult to control fin height and on body silicon wafer, form FinFET shallow trench isolation used from (STI).
Summary of the invention
From the above mentioned, the object of the invention is to overcome above-mentioned technical difficulty, improve the state modulator fineness of fin, and improve fin lamination insulation isolation effect.
For this reason, the invention provides a kind of manufacture method adopting body substrate to form fin on insulator, comprising: on substrate, form fin; Fin sidewall forms side wall; Anisotropic etching substrate, leaves polycrystalline substance below fin; Isotropic etching substrate, reduces polycrystalline substance width; Oxidation or nitriding process are performed to polycrystalline substance, makes it change insulator into.
Wherein, substrate material is selected from the arbitrary and combination of Si, Ge, SOI, GeOI, strained silicon, SiGe, GaN, GaAs, InP, InSb, Graphene, SiC, carbon nanotube.
Wherein, the step forming side wall comprises further: on substrate and fin, form protective layer; Anisotropic etching protective layer, removes the protective layer at substrate and fin top, only in fin sidewall, leaves side wall.
Wherein, side wall material is selected from the arbitrary and combination of silica, silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon.
Wherein, after isotropic etching, polycrystalline substance width is 2/3 ~ 1/2 of fin width.
Wherein, oxidation technology comprises thermal oxidation, chemical oxidation or nitrogenize, plasma oxidation or nitrogenize, gaseous oxidation or nitrogenize, or the after annealing tilting to inject oxygen or nitrogen makes it be oxidized or nitrogenize.
Wherein, controlled oxidization or nitriding process parameter, make polycrystalline substance complete oxidation and change insulator into.
Wherein, increase oxidation or nitriding process time, make substrate top by selective oxidation or nitrogenize to connect with insulator.
Wherein, isotropism and/or anisotropic etch process are plasma dry etch or RIE.
Wherein, etching gas is selected from NF
3, SF
6, CF
4, CH
2f
2, CH
3f, CHF
3, Cl
2arbitrary and combination.
According to the manufacture method of fin on insulator of the present invention, defined the fin lines become more meticulous by special step etching technique, formed by oxidation fin bottom and isolate with the good insulation of substrate, which thereby enhance device performance and reliability.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 is the top view of three-dimensional gate device;
Fig. 2 to Fig. 6 is the generalized section of each step of manufacture method according to fin on insulator of the present invention; And
Fig. 7 is the indicative flowchart according to the manufacture method of fin on insulator of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose the manufacture method of fin on the fineness that effectively can improve fin and the insulator improving fin lamination insulation isolation effect.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process.These modify the space of not hint institute's modification device architecture or manufacturing process unless stated otherwise, order or hierarchical relationship.
Figure 1 shows that the top view of FinFET, tri-gate devices in prior art and the present invention, comprising the fin 1F that substrate 1 and etched substrate 1 are formed.In Fig. 1, A-A ' line is that vertical fin 1F extends the hatching of distribution arrangement, and B-B ' line is be parallel to and extended the hatching of distribution arrangement by fin 1F.Especially, in following Fig. 2 to Fig. 6, figure left part is depicted as the cutaway view that device obtains along the A-A ' hatching of Fig. 1, and figure right part is depicted as the cutaway view that device obtains along the B-B ' hatching of Fig. 1.
As shown in Figure 2, fin 1F is formed on substrate 1.Substrate 1 is provided, substrate 1 needs and choose reasonable according to device application, monocrystalline silicon (Si), monocrystal germanium (Ge), SOI, GeOI, strained silicon (Strained Si), germanium silicon (SiGe) can be comprised, or compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc.For the consideration with CMOS technology compatibility, substrate 1 is preferably body Si or SOI.Photoetching/etched substrate 1, forms the fin 1F that between multiple groove 1G along first direction (being also B-B ' hatching direction) parallel distribution and groove 1G, remaining substrate 1 material is formed in substrate 1.The depth-to-width ratio of groove 1G is preferably more than 5:1.For the semiconductor-on-insulator substrate such as SOI, GeOI, the stop position that etching forms groove 1G (is such as equal to or less than the bottom surface of oxygen buried layer for being equal to or less than oxygen buried layer, even enter in thick body substrate), make thus to leave very thin semiconductor material layer on whole wafer, this contributes to the enough fin intensity of maintenance to bear the clean of subsequent erosion.In an embodiment of the invention, relevant to the selection of etch process parameters, the fin 1F that etching is formed has the profile morphology of sloped sidewall (cross section is up-narrow and down-wide) slightly, and this section also can be have vertical sidewall in addition.Fin 1F such as has the mean breadth of 10 ~ 30nm.
Namely as shown in Figure 3, also substrate 1 and fin 1F and groove 1G form protective layer 2 at whole device.The formation process of protective layer 2 can comprise LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxidation, chemical oxidation etc., and its material can be selected from silica, silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon etc. and combination thereof.Preferably, Controlling Technology parameter, makes protective layer 2 all have uniform thickness on fin 1F and groove 1G, such as 1 ~ 10nm also preferred 5nm.
As shown in Figure 4; anisotropic etching is carried out to wafer; such as vertical direction etch rate is obviously greater than horizontal cross erosion rate (such as vertical etch rate: horizontal etch rate >=5:1), the protective layer 2 of horizontal component is etched completely and removes and only on fin 1F sidewall, leave side wall 2S.Etching technics is such as dry plasma etch, reactive ion etching (RIE), and etching gas such as comprises fluorine-based or chlorine-based gas, such as NF
3, SF
6, CF
4, CH
2f
2, CH
3f, CHF
3, Cl
2deng and combination.Preferably, increase etch period, increase the etch amount of vertical direction, the groove 1G degree of depth between fin 1F is increased, below the 1F of fin shown in Fig. 2, leave the fin polycrystalline substance 1Fb that substrate 1 is formed thus.As shown in Figure 2,1Fb width is greater than 1F width, such as, have the width of 15 ~ 50nm.In addition, the protective layer 2 at fin 1F top is also correspondingly removed, and exposes its top so that source and drain is afterwards adulterated.
As shown in Figure 5, carry out isotropic etching to wafer, such as vertical direction etch rate equals or is slightly less than horizontal direction etch rate, fin polycrystalline substance 1Fb is etched and recessed, reduce width.The preferred dry plasma etch of isotropic etching or RIE, gas shown in etching gas and Fig. 4 seemingly, also can comprise fluorine-based or chlorine-based gas, such as NF
3, SF
6, CF
4, CH
2f
2, CH
3f, CHF
3, Cl
2deng and combination; just by adjusting the technological parameter such as flow, air pressure, temperature of the flow of etching gas, proportioning and other protectiveness inert gases or oxidizing gas, vertical direction etch rate being equaled or is slightly less than horizontal direction etch rate.Due to the protection of the side wall 2S that protective layer 2 is formed; fin 1F is not now subject to the erosion of isotropic etching; final fin 1F width is made to be greater than the width of polycrystalline substance 1Fb; this contributes to increasing the following space forming bottom insulation structure or fill STI, effectively can improve the isolation effect of device further.In an embodiment of the invention, by adjusting process parameter, make fin polycrystalline substance 1Fb remain width and be only 2/3 ~ 1/2, such as 5 ~ 20nm of fin 1F width.
As shown in Figure 6, oxidation or nitriding process are performed to fin polycrystalline substance 1Fb, makes it change insulator 3 into.Oxidation technology comprises thermal oxidation, chemical oxidation or nitrogenize, plasma oxidation or nitrogenize, gaseous oxidation or nitrogenize, or the after annealing tilting to inject oxygen or nitrogen makes its oxygen or nitrogenize.Controlled oxidization or nitriding process speed and time, make the completely oxidized or nitride conversion of fin polycrystalline substance 1Fb be insulator 3, thus achieve and the insulation completely between fin 1F and substrate 1 is isolated, be conducive to the performance and the reliability that improve device.According to substrate 1, self material of fin 1F difference, insulator 3 material can be silica, germanium oxide, germanium oxide silicon, nitrogen gallium oxide, silicon nitride etc., can adulterate in addition and have other elements such as F, N, C, S.The side wall 2S due to fin 1F sidewall with insulating barrier 2 formation protects; for the oxidation of fin 1F self or nitrogenize be enough slowly; make to be oxidized or nitridation process mainly concentrates on oxidation for polycrystalline substance 1Fb or nitrogenize; also namely fin 1F top is not oxidized (even if there is slight oxidation, also can be removed by the cleaning of HF base corrosive liquid in subsequent process) substantially.Further preferably, suitably can increase oxidation or nitridation time, to make the also oxidized or nitrogenize of part thus connect with fin dielectric isolation layer 3 of substrate 1 surface, to improve the support strength for fin, and also can increase insulation isolation effect simultaneously.
So far, the flow chart of reference Fig. 2 to Fig. 6 and Fig. 7 describes the manufacture method of fin on insulator of the present invention.After this, can deposit in A-A ' direction and etch formation gate stack, in the fin 1F of gate stack along the both sides in B-B ' direction, doping forms source-drain area and also makes contact, completes device architecture.
According to the manufacture method of fin on insulator of the present invention, defined the fin lines become more meticulous by special step etching technique, formed by oxidation fin bottom and isolate with the good insulation of substrate, which thereby enhance device performance and reliability.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (10)
1. the manufacture method of fin on insulator, comprising:
Substrate forms fin;
Fin sidewall forms side wall;
Anisotropic etching substrate, leaves polycrystalline substance below fin;
Isotropic etching substrate, reduces polycrystalline substance width;
Oxidation or nitriding process are performed to polycrystalline substance, makes it change oxide or nitride insulator into.
2. the method for claim 1, wherein substrate material is selected from the arbitrary and combination of Si, Ge, SOI, GeOI, strained silicon, SiGe, GaN, GaAs, InP, InSb, Graphene, SiC, carbon nanotube.
3. the step the method for claim 1, wherein forming side wall comprises further:
Substrate and fin form protective layer;
Anisotropic etching protective layer, removes the protective layer at substrate and fin top, only in fin sidewall, leaves side wall.
4. the method for claim 1, wherein side wall material is selected from the arbitrary and combination of silica, silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon.
5., the method for claim 1, wherein after isotropic etching, polycrystalline substance width is 2/3 ~ 1/2 of fin width.
6. the method for claim 1, wherein oxidation or nitriding process comprise thermal oxidation, chemical oxidation or nitrogenize, plasma oxidation or nitrogenize, gaseous oxidation or nitrogenize, or the after annealing tilting to inject oxygen or nitrogen makes it be oxidized or nitrogenize.
7. the method for claim 1, wherein controlled oxidization or nitriding process parameter, makes polycrystalline substance complete oxidation or nitrogenize and changes insulator into.
8. the method for claim 1, wherein increase oxidation or nitriding process time, make substrate top by selective oxidation or nitrogenize to connect with insulator.
9. the method for claim 1, wherein isotropism and/or anisotropic etch process are plasma dry etch or RIE.
10. method as claimed in claim 9, wherein, etching gas is selected from NF
3, SF
6, CF
4, CH
2f
2, CH
3f, CHF
3, Cl
2arbitrary and combination.
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| CN201310407815.7A CN104425346A (en) | 2013-09-10 | 2013-09-10 | Manufacturing method for fin on insulator |
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| CN201310407815.7A CN104425346A (en) | 2013-09-10 | 2013-09-10 | Manufacturing method for fin on insulator |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106298919A (en) * | 2015-05-29 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, fin formula field effect transistor and forming method thereof |
| CN107591331A (en) * | 2016-07-08 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108109919A (en) * | 2017-12-14 | 2018-06-01 | 深圳市金誉半导体有限公司 | Three-dimensional field-effect transistor and preparation method thereof |
| CN108630523A (en) * | 2017-03-22 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN106298919A (en) * | 2015-05-29 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, fin formula field effect transistor and forming method thereof |
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| CN108630523B (en) * | 2017-03-22 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108109919A (en) * | 2017-12-14 | 2018-06-01 | 深圳市金誉半导体有限公司 | Three-dimensional field-effect transistor and preparation method thereof |
| CN108109919B (en) * | 2017-12-14 | 2020-05-22 | 深圳市金誉半导体有限公司 | Three-dimensional field effect transistor and manufacturing method thereof |
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