CN104779285A - FINFET (Fin Field Effect Transistor) semiconductor device and manufacturing method thereof - Google Patents

FINFET (Fin Field Effect Transistor) semiconductor device and manufacturing method thereof Download PDF

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CN104779285A
CN104779285A CN 201410011019 CN201410011019A CN104779285A CN 104779285 A CN104779285 A CN 104779285A CN 201410011019 CN201410011019 CN 201410011019 CN 201410011019 A CN201410011019 A CN 201410011019A CN 104779285 A CN104779285 A CN 104779285A
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fin
finfet
stacked
fins
device
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CN 201410011019
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Chinese (zh)
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赵猛
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中芯国际集成电路制造(上海)有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Abstract

The invention mainly relates to a FINFET (Fin Field Effect Transistor) device, and particularly relates to a FINFET semiconductor device with stacked-type fins and a manufacturing method thereof, so as to enhance gate control and current driving abilities. The FINFET semiconductor device comprises a substrate, the stacked fins located on the substrate and gate structures surrounding two sides and above the stacked-type fins, wherein the stacked fins comprise a hourglass lower fin and a trapezoidal or square upper fin located above the lower fin.

Description

FINFET半导体器件及其制备方法 Semiconductor device and method of preparation FINFET

技术领域 FIELD

[0001] 本发明主要涉及FINFET半导体器件,更确切地说,涉及一种带有堆叠式鳍片的FINFET半导体器件及其制备方法,以便增强栅极控制和电流驱动能力。 [0001] The present invention generally relates to a FINFET semiconductor devices, and more particularly, to a semiconductor device and a FINFET preparation method having stacked fins, and control gate in order to enhance the current driving capability.

背景技术 Background technique

[0002] 随着半导体器件维持低成本和具有较高竞争力性能的需求,器件中晶体管单元的密度一直在增加并且器件的整体尺寸却是在降低的,对金属氧化物半导体场效应晶体管(MOSFET)而言,随着器件整体尺寸的缩小,一些不期望的负面影响亦随之而来,譬如当沟道缩小到一定值时(例如低于lOOnm),源极区和漏极区之间的距离也相应缩短,极易带来短沟道效应,栅极对沟道的控制能力被消减,栅极夹断沟道的难度增大,负面的亚阈值漏电现象也更容易产生。 [0002] As semiconductor devices have higher demand to maintain a low cost and performance competitive forces, the density of transistor cells of the device has been increased and the overall size of the device is reduced, the metal oxide semiconductor field effect transistor (MOSFET ), the overall size of the device is reduced as the number of undesirable attendant negative effects also, for example, when the channel is reduced to a certain value (e.g., less than lOOnm), between the source region and the drain region distance is shortened, the short channel effect can easily bring the gate control of the channel is subtracted, the difficulty of gate pinch off the channel is increased, the negative subthreshold leakage phenomenon is more likely to occur. 基于传统平面型的晶体管固有的缺陷,鳍形场效应晶体管(Fin FieldEffect Transistor,FinFET)被业界广泛采用来克服前述难题。 Based on the inherent weaknesses of traditional planar type transistor, fin-shaped field effect transistor (Fin FieldEffect Transistor, FinFET) are widely used in the industry to overcome the aforementioned problems. 通常是在鳍片的顶部和两侧都形成栅极结构,来提高栅极控制能力。 They are usually formed on the top and sides of the gate structure of the fins, to improve gate control.

[0003] 当半导体产业想22nm或以下的技术节点发挺进时,一个挑战是FinFET器件如何具有更小的尺寸和更高的驱动电流,尤其是希望提供具有受到应力因素影响的FinFET,譬如适当的采用应力材料以诱引沟道中的应力来强化载流子的迁移率。 [0003] When the semiconductor industry or the like 22nm technology node send advance, a challenge is how FinFET device having a smaller size and a higher drive current, particularly desirable to provide a FinFET subjected to stress factors, such appropriate to lure stress using stress material to reinforce the channel mobility of the carriers. 但现有的FinFET制造能力显然无法满足这样的技术要求。 However, the existing FinFET manufacturing capacity so clearly unable to meet the technical requirements. 由本发明后续的详细说明和所附的权利要求,结合本发明伴随的图式和先前技术,本发明揭示的特征和方案将变得清晰。 By the subsequent detailed description of the invention and the appended claims, the present invention in conjunction with the accompanying drawings and the prior art, the present invention is disclosed features and aspects will become apparent.

发明内容 SUMMARY

[0004] 在一种实施例中,FinFET半导体器件,包括:一衬底和位于衬底之上的堆叠式鳍片;围绕在堆叠式鳍片两侧及上方的栅极结构;其中所述堆叠式鳍片包括一沙漏状的下部鳍片和位于下部鳍片之上的一梯形状的上部鳍片。 [0004] In one embodiment, a FinFET semiconductor device, comprising: a substrate and stacked fins positioned above the substrate; around both sides of the fin and the gate stacked structure above; wherein said stack fin hourglass comprising a lower portion and an upper fin fins positioned on a lower portion of trapezoidal fins.

[0005] 上述的FinFET半导体器件,所述上部和下部鳍片两者中之一为Si材质,另一者为SiGe材质。 [0005] FinFET semiconductor device described above, one of the upper and lower fins of both Si material, the other material is SiGe.

[0006] 上述的FinFET半导体器件,所述衬底包含一底部衬底和位于底部衬底之上的掩埋绝缘层,所述堆叠式鳍片设置在掩埋绝缘层上方。 [0006] FinFET semiconductor device described above, the substrate comprises a base substrate and the buried insulating layer is disposed on the base substrate, the stacked fins disposed over the buried insulating layer.

[0007] 上述的FinFET半导体器件,位于栅极结构两侧的堆叠式鳍片,其两侧及上方设置有源极/漏极外延区。 [0007] FinFET semiconductor device described above, the fins located on both sides of the gate stacked structure disposed on both sides thereof and over the active source / drain epitaxial region.

[0008] 上述的FinFET半导体器件,N型FinFET的源极/漏极外延区包括拉伸应变的SiC外延区,P型FinFET的源极/漏极外延区包括压缩应变的SiGe外延区。 [0008] FinFET semiconductor device described above, the N-type FinFET source / drain region comprises an epitaxial SiC epitaxial tensile strained region, the P-type FinFET source / drain region comprises epitaxial SiGe compressive strained epitaxial region.

[0009] 在本发明的另一种实施例中,FinFET半导体器件,包括:一衬底和位于衬底之上的堆叠式鳍片;围绕在堆叠式鳍片两侧及上方的栅极结构;其中所述堆叠式鳍片包括一沙漏状的下部鳍片和位于下部鳍片之上的一方形状的上部鳍片。 [0009] In another embodiment of the present invention, a FinFET semiconductor device, comprising: a substrate and stacked fins positioned above the substrate; a gate structure surrounds the fin and the top sides of the stacked; wherein the stacked fins comprises a hourglass-shaped lower fins and upper fins positioned one above the lower portion of the fin shape.

[0010] 在本发明的一种FinFET半导体器件的制备方法中,包括以下步骤:提供一包含第一、第二半导体层的衬底;刻蚀第一半导体层形成上部鳍片;刻蚀第二半导体层未被上部鳍片覆盖住的区域以形成上部鳍片下方的呈沙漏状的下部鳍片;形成围绕在包含上部、下部鳍片的堆叠式鳍片两侧及上方的栅极结构。 [0010] In the method for producing a FinFET semiconductor device according to the present invention, comprising the steps of: providing a substrate comprising a first, a second semiconductor layer; and etching the first semiconductor layer is formed in an upper portion of the fin; etching the second the semiconductor layer is not covered with an upper fin to form a lower region of the fin stay hourglass shape below the upper fin; formed around the sides of the stacked gate structure including an upper fin, the lower fin and above.

[0011] 上述的方法,形成上部鳍片的步骤中,在第一半导体层上方形成一硬掩膜层并图案化该硬掩膜层;利用带有开口图形的硬掩膜层干法刻蚀第一半导体层暴露的区域,形成第一半导体层中深度小于第一半导体层原始厚度的沟槽;利用硬掩膜层沿着所述沟槽以各向异性湿法刻蚀第一半导体层,从而形成上窄下宽的梯形状上部鳍片。 Step [0011] The method of forming the upper portion of the fin, forming a hard mask layer and patterning the hard mask layer over the first semiconductor layer; using a dry etching the hard mask layer with an opening pattern the exposed region of the first semiconductor layer, forming a trench depth less than the original thickness of the first semiconductor layer of a first semiconductor layer; layer using the hard mask along the trench anisotropic wet etching of the first semiconductor layer, thereby forming a trapezoidal shape of the upper fin of the narrow width.

[0012] 上述的方法,形成下部鳍片的步骤中,对第二半导体层暴露的区域进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 Step [0012] The method of forming the lower fins, the second semiconductor layer exposed region anisotropic wet etching, is formed larger than the width of the top and bottom of the hourglass-shaped lower portion of the intermediate portion of the width of the fin.

[0013] 上述的方法,形成下部鳍片的步骤中,先利用硬掩膜层干法刻蚀第二半导体层,形成带有垂直侧壁形貌的下部鳍片;然后对下部鳍片暴露的侧壁进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 Step [0013] The method of forming the lower fins, the first hard mask layer using a dry-etching the second semiconductor layer, forming a lower portion having vertical side walls of the fin morphology; then exposed to the lower fins width of the sidewall is anisotropically wet etched to form the top and bottom of the lower portion of the fin is greater than the intermediate portion hourglass width.

[0014] 上述方法,形成上部鳍片的步骤中,利用硬掩膜层干法刻蚀第一半导体层,从而形成带有垂直侧壁形貌的上部鳍片;然后在硬掩膜层中的开口的内壁、上部鳍片的侧壁和在硬掩膜层的顶面上覆盖一牺牲侧墙层;回蚀牺牲侧墙层形成覆盖在开口内壁和上部鳍片的侧壁上的牺牲侧墙;利用牺牲侧墙和硬掩膜层刻蚀第二半导体层暴露的区域形成下部鳍片。 [0014] The above-described method, the step of forming the upper fin, the hard mask layer using a dry-etching the first semiconductor layer to form an upper fin with vertical sidewalls topography; then the hard mask layer the inner wall of the opening, side walls and an upper top surface of the fin of the hard mask layer covering a sacrificial spacer layer; etching back the sacrificial spacer layer is formed overlying the sidewalls and the upper opening of the inner wall of the sacrificial sidewall spacer fin ; using sacrificial spacers and the hard mask layer etching the exposed region of the second semiconductor layer to form a lower fin.

[0015] 上述的方法,形成下部鳍片的步骤中,对第二半导体层暴露的区域进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 Step [0015] The method of forming the lower fins, the second semiconductor layer exposed region anisotropic wet etching, is formed larger than the width of the top and bottom of the hourglass-shaped lower portion of the intermediate portion of the width of the fin.

[0016] 上述的方法,形成下部鳍片的步骤中,先利用硬掩膜层和牺牲侧墙干法刻蚀第二半导体层,形成带有垂直侧壁形貌的下部鳍片;然后对下部鳍片暴露的侧壁进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 Step [0016] The method of forming the lower fins, the first hard mask layer using a dry etching the sacrificial sidewall spacer and the second semiconductor layer, forming a lower portion having vertical side walls of the fin morphology; then the lower the width of the exposed sidewalls of the fin anisotropically wet etched to form the top and bottom of the lower portion of the fin is greater than the intermediate portion hourglass width.

[0017] 上述的方法,形成栅极结构之后,以栅极结构为自对准掩膜在上部鳍片的上表面注入轻掺杂源/漏区;以及然后在栅极结构的侧壁上形成侧墙,并在栅极结构两侧的堆叠式鳍片中植入源极/漏极掺杂区。 After the [0017] above method, forming a gate structure, the gate structure as a mask a self-aligned implantation lightly doped source / drain regions on the upper surface of the fin; and then formed on the sidewalls of the gate structure spacer, and implanted source / drain doped regions in a stacked gate structure on both sides of the fin.

[0018] 上述的方法,形成栅极结构之后,在栅极结构两侧的堆叠式鳍片的两侧及上方选择性的外延生长源极/漏极外延区。 After the [0018] above method, forming a gate structure, the epitaxial growth of source / drain regions on both sides and selective epitaxial stacked above the gate structure on both sides of the fin. 上述的方法,N型FinFET所外延生长的源极/漏极外延区包括拉伸应变的SiC外延区,P型FinFET所外延生长的源极/漏极外延区包括压缩应变的SiGe外延区。 The above-described method, the source of the N-type FinFET epitaxially grown source / drain region comprises an epitaxial SiC epitaxial tensile strained region, the source of the P-type FinFET epitaxially grown source / drain region comprises epitaxial SiGe compressive strained epitaxial region.

附图说明 BRIEF DESCRIPTION

[0019] 阅读以下详细说明并参照以下附图之后,本发明的特征和优势将显而易见: [0019] reading of the following detailed description with reference to the following drawings and following, features and advantages of the present invention will become apparent:

[0020] 图1显示了在底部衬底上设置的顶部外延层和底部外延层。 [0020] Figure 1 shows the top of the epitaxial layer and a bottom epitaxial layer disposed on the bottom substrate.

[0021] 图2〜5显示了刻蚀顶部外延层形成倒梯形的上部鳍片的流程图。 [0021] 2 ~ 5 shows a flowchart of FIG etching the epitaxial layer is formed on top of the upper portion of an inverted trapezoidal fin.

[0022] 图6A〜6B是刻蚀底部外延层来制备沙漏状的下部鳍片的示意图。 [0022] FIG 6A~6B is a schematic view of an hourglass-shaped lower bottom fin etch the epitaxial layer is prepared.

[0023] 图7是包含上部、下部鳍片的堆叠式鳍片的鸟瞰图。 [0023] FIG. 7 comprising upper and lower fins stacked fin aerial view.

[0024] 图8是在堆叠式鳍片和掩埋绝缘层上制备栅极绝缘层和栅极材料的流程图。 [0024] FIG 8 is a flowchart of a gate insulating layer and a gate electrode material prepared in the stacked fins and the buried insulating layer.

[0025] 图9是图案化栅极绝缘层和栅极材料制备栅极结构的流程示意图。 [0025] FIG. 9 is a schematic flow diagram of the patterned gate insulating layer and the gate material prepared gate structure.

[0026] 图10是在栅极结构的两侧形成侧墙的示意图。 [0026] FIG. 10 is a schematic view of a spacer formed at both sides of the gate structure.

[0027] 图11是选择性外延生长源极/漏极外延区的示意图。 [0027] FIG. 11 is a schematic view of selective epitaxial growth of source / drain epitaxial region.

[0028] 图12A显示了刻蚀顶部外延层形成具有垂直侧壁的上部鳍片的方法。 [0028] FIG 12A shows a method of etching the epitaxial layer forming the top of the upper portion having vertical sidewalls of the fin.

[0029] 图12B〜12C是制备牺牲侧墙的方法。 [0029] FIG 12B~12C is a method for preparing the sacrificial sidewall spacer.

[0030] 图12D〜12F是以牺牲侧墙和硬掩膜层作为掩膜来刻蚀底部外延层形成下部鳍片。 [0030] FIG 12D~12F is a sacrificial sidewall spacer as a mask and a hard mask layer is etched to form the lower bottom of the epitaxial layer fin.

[0031] 图12G是图案化栅极绝缘层和栅极材料制备栅极结构的流程示意图。 [0031] FIG. 12G is a schematic flow diagram of patterning the gate insulating layer and a gate material prepared gate structure.

[0032] 图12H是选择性外延生长源极/漏极外延区的示意图。 [0032] FIG 12H is a schematic view of selective epitaxial growth of source / drain epitaxial region.

具体实施方式 detailed description

[0033] 图1展示了一个典型的绝缘体上娃(Silicon-0n_Insulator,S0I)的晶圆,在一个底部衬底101上方设有掩埋绝缘层102,例如一个掩埋氧化物层,以及还在掩埋绝缘层102上方由下至上依次具有形成的一层底部外延层103和一层顶部外延层104,外延层104、103分别对应作为掩埋绝缘层102上的一个第一半导体层和一个第二半导体层。 [0033] Figure 1 shows a typical baby insulator (Silicon-0n_Insulator, S0I) wafer, over a base substrate 101 provided with the buried insulating layer 102, for example a buried oxide layer, and also in the buried insulating oriented layer above the bottom layer 102 epitaxial layer 103 and one top epitaxial layer 104 having formed by the lower order, as the epitaxial layer 104, 103 respectively correspond to a buried insulating layer 102 on the first semiconductor layer and a second semiconductor layer. 作为示范,在一些可选的实施方式中,例如,底部外延层103是Si材质外延层,而顶部外延层104可以是GeSi材质,或底部外延层103是GeSi材质外延层,而顶部外延层104可以是Si材质等。 Exemplary, in some alternative embodiments, e.g., the bottom of the epitaxial layer 103 is a Si epitaxial layer material, while the top epitaxial layer 104 may be a GeSi material, or the bottom of epitaxial layer 103 is an epitaxial layer GeSi material, while the top epitaxial layer 104 the material can be Si and the like. 在图2中,先行制备一个硬掩膜层105,覆盖在顶部外延层104上方,其中硬掩膜层105可以是单层结构,例如典型的SiN等,也可以是含有多层的复合层结构。 In FIG. 2, the preparation of a first hard mask layer 105 covers over the top of epitaxial layer 104, wherein the hard mask layer 105 may be a single layer structure, such as a typical SiN or the like, or may be a composite layer structure comprising a plurality of layers . 须强调的是,这里的晶圆并非一定是SOI晶圆,在另一些实施方式中,SOI晶圆还可以被不含任何掩埋绝缘层的纯硅衬底所替代。 It should be emphasized that this is not necessarily the wafer is an SOI wafer, in some other embodiments, SOI wafers can also be free of any pure silicon substrate, a buried insulating layer is replaced.

[0034] 如图3〜4所示,利用常规的光刻工艺,图案化硬掩膜层105形成其中的开口图形,例如在硬掩膜层105中刻蚀出的开口105a。 [0034] As shown in FIG. 3 to 4, using a conventional photolithographic process, the patterned hard mask layer 105 is an opening pattern formed therein, for example etched in the hard mask layer 105 in the opening 105a. 然后再利用硬掩膜层105作为一个刻蚀掩膜,对其下方的顶部外延层104暴露的区域进行干法刻蚀,形成沟槽104a,注意此刻蚀终止在顶部外延层104内而没有刻蚀贯穿其整个厚度,所以沟槽104a的深度小于顶部外延层104的原始厚度。 And then using the hard mask layer 105 as an etching mask, dry etching of the epitaxial layer 104 below the top of its exposed region, forming a trench 104a, note that this etch stop within the top epitaxial layer 104 without engraved erosion throughout its thickness, the depth of the groove 104a is smaller than the original thickness of the top of the epitaxial layer 104. 然后继续利用硬掩膜层105作为刻蚀掩膜,沿着沟槽104a实施各向异性湿法刻蚀工艺,刻蚀顶部外延层104暴露在沟槽104a内的区域,由于沟槽104a的存在和后续执行的各向异性腐蚀,在沿着沟槽104a将顶部外延层104刻蚀贯穿之后,便可形成了多个条状的上部鳍片104',其大体呈现为上窄下宽的梯形状结构。 Then continue using the hard mask layer 105 as an etching mask, trenches 104a along embodiment anisotropic wet etching process, the region 104a within the trench etching the exposed top epitaxial layer 104, due to the presence of the trenches 104a and the subsequent anisotropic etching is performed, after the top 104a through epitaxial layer 104 along the trench etching, it can be formed a plurality of stripe-shaped upper fin 104 ', which is generally presented as the narrow width of the ladder shaped structure. 多个上部鳍片104'彼此间平行排列,上部鳍片104'之间的贯穿顶部外延层104厚度的刻蚀沟槽将相邻上部鳍片104'分离断开,注意此时的上部鳍片104'的侧壁具有倾斜面的形貌,上部鳍片104'的竖截面为上窄下宽是因为刻蚀步骤在硬掩膜层105下方形成了底切,将上部鳍片104'两侧的较上部的拐角部各自的一部分区域给移除掉了。 A plurality of upper fins 104 'are arranged in parallel to each other, an upper fin 104' throughout the thickness of the epitaxial layer 104 on top of the etched trench between the adjacent upper portion of the fins 104 'separating off the upper part of the fin at this time note 104 'having a sidewall inclined surface topography, an upper fin 104' is on the vertical cross section of the narrow width is formed because the undercut etch step under the hard mask layer 105, the upper portion of the fin 104 'on both sides a portion of the respective upper corner regions than to the portion removed off. 一般要求,在刻蚀顶部外延层104时,底部外延层103的材质能够抵抗对顶部外延层104执行的刻蚀工艺,而不受该刻蚀步骤的影响。 General requirements, when etching the top of the epitaxial layer 104, epitaxial material of the bottom layer 103 against the etching process can be performed on top of the epitaxial layer 104, without being affected by the etching step.

[0035] 图6A〜6B是进一步刻蚀底部外延层103的示意图,此时硬掩膜层105和上部鳍片104' 一起作为刻蚀掩膜,使底部外延层103暴露的区域被刻蚀掉,而形成最终的竖直截面为沙漏状的下部鳍片103'。 [0035] FIG 6A~6B is a schematic view of a further etching the bottom of the epitaxial layer 103, in which case the hard mask layer 105 and the upper fin 104 'as an etching mask with the exposed bottom of the epitaxial layer 103 are etched away region a lower portion of the fin-like an hourglass, and a final vertical section 103 '. 在图6A中,先经由各向同性刻蚀底部外延层103先形成下部鳍片103'的垂直侧壁,例如干法刻蚀,然后采用各向异性刻蚀,如利用湿法刻蚀在下部鳍片103'的垂直侧壁上刻蚀形成向内侧凹进的凹槽,凹槽的存在导致下部鳍片103'的侧壁具有相对竖直方向而呈现为倾斜面的上侧壁103'a和倾斜面的下侧壁103'b。 In FIG. 6A, the isotropic etch through the bottom of the first epitaxial layer 103 is formed to a lower portion of the vertical sidewall of the fin 103 ', for example, dry etching, and anisotropic etching, such as by wet etching at a lower on the sidewalls of the fin 103 'is etched to form vertical sidewalls of the recess inwardly recessed, resulting in the presence of a lower portion of the fin grooves 103' opposite vertical side walls having inclined surfaces presented 103'a and the inclined surface of the lower side wall 103'b. 设定沙漏状的下部鳍片103'的较中间部最窄,则在竖直方向上,中间部向上和向下分别以逐步增加宽度的方式与顶部和底部连续。 Setting the intermediate portion than the lower portion of the hourglass-shaped fin 103 'narrowest, in the vertical direction, the intermediate portion up and down, respectively, in a stepwise manner to increase the width of the top and bottom continuous. 上侧壁103' a、下侧壁103' b是〈110〉晶面或者〈111〉晶面,可依底部外延层103顶面的晶向〈100〉晶面而定,上侧壁103'a、下侧壁103'b的〈100〉晶面,可依底部外延层103顶面的晶向〈110〉晶面而定。 On the side wall 103 'A, the sidewall 103' B is a <110> crystallographic plane or <111> crystal plane, to follow the bottom surface of the epitaxial layer 103 crystal orientation of <100> crystal plane may be, on the side wall 103 ' a, <100> crystal plane of the lower side wall 103'b, 103 to follow the crystal of the epitaxial layer to the bottom surface of the <110> crystal plane dependent. 在此步骤中,掩埋绝缘层102不受刻蚀的影响,并且在形成梯形状的上部鳍片104'和沙漏状的下部鳍片103'之后,还需要将硬掩膜层105腐蚀剥离掉。 In this step, the buried insulating layer 102 is not etched impact, and after formation of the upper trapezoidal fins 104 'and a lower portion of the hourglass-shaped fins 103', also need to etching the hard mask layer 105 peeled off.

[0036] 在另一些可选实施例中,以硬掩膜层105和上部鳍片104'作为掩膜,不采用干法刻蚀而直接采用各向异性的湿法刻蚀对底部外延层103暴露的区域进行刻蚀,不形成下部鳍片103'的过渡的垂直侧壁,而是直接形成侧壁上的倾斜面即上侧壁103'a和下侧壁103'b,这样的侧壁又可称之为Σ形侧壁,即由图5之步骤直接执行图6B之步骤。 [0036] In other alternative embodiments, hard mask layer 105 and the upper fin 104 'as a mask, dry etching is not directly an anisotropic wet etching of the epitaxial layer 103 on the bottom etching the exposed area, the transition does not form a lower vertical sidewalls of the fin 103 ', but is directly formed on the surface of the side wall that is inclined upper side wall and a lower side wall 103'a 103'b, so that the side wall but also known as Σ-shaped side wall, i.e., the step of FIG. 6B directly from step 5 of FIG. 从而底部外延层103籍由刻蚀而形成了多个条状的下部鳍片103',相邻下部鳍片103'间的贯穿整个底部外延层103厚度的刻蚀沟槽将它们分离断开,这些下部鳍片103'彼此间大体平行排列设置。 So that the bottom of the epitaxial layer 103 is etched to form a membership from a plurality of stripe-shaped lower portion of the fins 103 ', 103 adjacent the lower portion of the fin' trench 103 etched through the epitaxial layer thickness of the entire bottom between the disconnect to separate them, the lower portion of the fins 103 'are arranged substantially parallel to each other. 在刻蚀底部外延层103时,顶部外延层104的材质能够抵抗对底部外延层103执行的刻蚀工艺,而不受该刻蚀步骤的影响。 Etching the epitaxial layer at the bottom 103, a top epitaxial layer 104 is a material capable of resisting etching process performed on the bottom of the epitaxial layer 103, without being affected by the etching step.

[0037] 图6B的竖剖面图和图7的鸟瞰图很好的展示了多条相互平行排列设置的堆叠式鳍片150。 Vertical cross-sectional view [0037] FIG. 6B and FIG. 7 of the bird's-eye view showing a good stacked fins are arranged parallel to each other a plurality of 150. 堆叠式鳍片150包括下部鳍片103'和堆叠在下部鳍片103'正上方的上部鳍片104',鳍片104'、103'分别对应作为一个第一鳍片和一个第二鳍片,这些堆叠式鳍片150都位于掩埋绝缘层102上方。 The stacked fin 150 includes a lower fin 103 'stacked on a lower fin 103 and' just above the top of the fin 104 ', the fin 104', 103 'respectively as a first fin and a second fin, these stacked fins 150 are located above the buried insulating layer 102. 在已知技术的FinFET中鳍条一般都是单材质的,而且常见于竖直剖面为矩形的结构中,而本发明图7之堆叠式鳍片150为复合层,不同层的材质亦可以不同,这对考虑沟道的有益应力工程相对已知技术而显现出来的效果是毫无疑虑的,后续内容将继续予以详细介绍。 Rays are generally known in the FinFET art single material, but common in vertical section of a rectangular configuration, and FIG. 7 of the present invention stacked fin 150 is a composite layer of material of the different layers may differ also , which manifest themselves useful to consider the channel strain engineering techniques known effect is relatively unsuspecting, subsequent content will continue to be described in detail.

[0038] 在图8中,继续在每个堆叠式鳍片150的顶部和两侧覆盖一层栅极绝缘层106,例如在氧化环境下热氧化堆叠式鳍片150而生成的氧化物,氧化物的类别取决于顶部外延层104和底部外延层103的材质,如二氧化硅或二氧化锗等。 [0038] In FIG. 8, each of the stacked fins continue top and sides covered with a layer 150 of the gate insulating layer 106, for example, thermal oxidation in an oxidizing environment fin 150 stacked generated oxide, category depends on the material composition of the top and bottom of the epitaxial layer 104 of epitaxial layer 103, such as silicon dioxide or germanium dioxide and the like. 栅极绝缘层106还可以是直接沉积的氧化硅、氮化硅等,或譬如HfS1等高介电常数绝缘物,栅极绝缘层106同时还覆盖在掩埋绝缘层102未被堆叠式鳍片150覆盖住的区域上。 The gate insulating layer 106 may also be directly deposited silicon oxide, silicon nitride, or a high-dielectric insulating material such HfS1, the gate insulating layer 106 also covers the buried insulating layer 102 is not stacked fins 150 live coverage area. 在图8中,其后还需要再在栅极绝缘层106上方沉积一层栅极材料层107,栅极材料层107为导电材料,典型的包含譬如多晶硅、一层或多层金属材料、或它们的组合等,考虑到相邻堆叠式鳍片150间的间隙宽度随着器件的尺寸减小亦是趋于缩小,所以栅极材料层107要无缺陷的填充在相邻堆叠式鳍片150间的间隙中,例如没有空洞,就必须设法降低间隙的高深宽比,本发明中可以调整下部鳍片103'和上部鳍片104'的高度即可,我们一般设定底部外延层103和顶部外延层104的厚度在6nm〜20nm间。 In FIG. 8, still need to subsequently deposited over the gate insulating layer 106 is a layer of gate material layer 107, the gate material layer 107 is a conductive material, such as polysilicon typically include one or more layers of metal material, or combinations thereof and the like, taking into account the adjacent stacked fin gap width 150 decreases as the size of the device also tends to be reduced, so that the gate material layer 107 to fill a defect-free stacked adjacent fins 150 the gap between, for example, free of voids, it is necessary to try to reduce the high aspect ratio gaps, the present invention can be adjusted in a lower portion of fin 103 'and the upper fin 104' can height, we usually set a bottom 103 and a top epitaxial layer the thickness of the epitaxial layer 104 between 6nm~20nm.

[0039] 在图9中,以未示意出的栅极掩膜刻蚀栅极材料层107和栅极绝缘层106,形成围绕在每个堆叠式鳍片150两侧及上方的栅极结构160,栅极结构160包括经由栅极绝缘层106图案化而来的栅绝缘层106',和包括经由栅极材料层107图案化而来的栅极107',栅极107'叠加在栅绝缘层106'上方。 [0039] In FIG. 9, not to illustrate the gate mask 107 is etched layer of gate material and the gate insulating layer 106, a gate structure 160 is formed around the sides 150 and the top of each of the fins stacked , via a gate structure 160 comprising a gate insulating layer 106 from the patterned gate insulating layer 106 ', and through the gate comprises a patterned gate material layer 107 from 107', gate electrode 107 'is superimposed on the gate insulating layer 106 'above. 在一些实施例中,长条状的栅极结构160的长度延伸方向正交于每个堆叠式鳍片150的长度方向。 In some embodiments, the gate structure 160 extending elongated in the length direction orthogonal to the longitudinal direction of each fin 150 is stacked. 此时FinFET的沟道区包括每条堆叠式鳍片150内被栅极结构160包覆和围绕住的部分,相对平面型MOSFET,FinFET的沟道区的三个侧面受到栅极结构160的控制,无疑增强了驱动电流的能力。 At this time, the channel region of the FinFET 160 comprises a coated and partially surrounds the fin of each stacked gate structure 150, relative to the plane of the MOSFET type, three sides of the channel region of the FinFET structure of the control gate 160 by undoubtedly enhances the ability of the drive current. 尤其是,依本申请的发明精神,一方面,在下部鳍片103'的侧壁上所刻蚀出的向内凹进的凹槽,相当于可以使该鳍片两侧侧壁的面积得以增加,另一方面,在上部鳍片104'的梯形结构中,虽然使得上部鳍片104'的顶面面积略有减少,但是其两侧侧壁所增加的面积远远超过顶面缩减的面积。 In particular, the spirit of the invention under this application, on the one hand, on the sidewalls of the lower portion of fin 103 'is etched inwardly recessed groove, corresponding to the area can be made on both sides of the fin to the side walls increase, on the other hand, in the upper portion of the fin 104 'ladder structure, although such an upper portion of the fin 104' top surface area decreased slightly, but the side walls on both sides thereof increased area far exceeds the area of ​​the reduced top surface . 籍此来增加堆叠式鳍片150中被栅极结构160所包覆住的沟道区的有效沟道宽度,在不增加晶体管单元尺寸条件下,涉及电流控制的沟道宽长比这个因素得到明显改善,这是本领域技术人员所乐见其成的。 Thereby to increase the effective channel width of the fins 150 are stacked gate structure 160 covered live channel region, without increasing the unit size of the transistor condition, to the current control channel width to length ratio of this factor obtained improved significantly, which is skilled in the art it is happy to see.

[0040] 在一些实施方式中,可在形成栅极机构160之后,实施轻掺杂源/漏区(Lightlydoped drain, LDD)工序,无需提供额外的离子注入掩膜,可以直接利用栅极结构160为自对准掩膜而在上部鳍片104'的上表面注入轻掺杂源/漏区(未示意出),为了形成轻掺杂源/漏区而掺杂浓度相对较轻的掺杂物被植入到位于栅极机构160两侧的上部鳍片104'的上表面中,N沟道FinFET较佳植入砷离子,P沟道FinFET较佳植入硼离子。 [0040] In some embodiments, the mechanism may be after forming the gate 160, the implementation of lightly doped source / drain regions (Lightlydoped drain, LDD) step, no additional mask ion implantation, using the gate structure 160 may be directly injected lightly doped source / drain regions (not illustrated) is formed on the upper surface of the fin 104 'is self-aligned mask, to form lightly doped source / drain regions and the doping concentration of the relatively light dopant are implanted into the upper portion of fin 104 on both sides of the gate mechanism 160 'of the upper surface, N-channel FinFET implanted arsenic ions are preferred, P-channel FinFET preferred implanted boron ions. 之后,再在栅极结构160两侧的侧壁上形成侧墙108,如图10所示,形成侧墙108的步骤可以先沉积侧墙覆盖层来覆盖在栅极结构160、堆叠式鳍片150及掩埋绝缘层102裸露的区域上,再回蚀侧墙覆盖层以便将不需要的区域刻蚀掉而仅仅保留栅极结构160侧壁上的侧墙108。 Thereafter, the side wall 160 is further formed on the sides of the gate sidewall spacer structure 108, shown in Figure 10, the step of forming the sidewall spacers 108 may be deposited to cover the sidewall spacer layer overlying the gate structure 160, the stacked fins 150 and 102 on the buried insulating layer exposed region, return to etch spacer layer so as to cover the etching away unwanted areas of the sidewall and retain only the sidewalls 108 of the gate structure 160. 最后,还需要在位于栅极结构160 —侧的裸露出来的堆叠式鳍片150a中注入重掺杂的源极掺杂区,和在栅极结构160另一侧裸露出来的堆叠式鳍片150b中注入重掺杂的漏极掺杂区,它们的掺杂浓度比LDD区要大得多。 Finally, the gate structure also need 160-- implanted highly doped source bared stacked side fin 150a doping region, and expose the other side of the gate structure 160 stacked fins 150b implanting heavily doped drain doped regions, doping concentration thereof is much greater than the LDD region.

[0041] 在图10的实施方式中,还在栅极结构160两侧选择性的外延生长了譬如源极外延区109a和漏极外延区109b,注意此外延步骤并非是掩埋绝缘层102上方的任意区域都生长了外延区,仅仅是在栅极结构160两侧的堆叠式鳍片150a、150b上选择性的开始生长外延区109a、109b。 [0041] In the embodiment of FIG. 10, also on both sides of the gate structure 160 is selectively epitaxially grown epitaxial regions such as the source and drain extension regions 109a 109b, Note Additionally casting step is not over the buried insulating layer 102 any regions of the epitaxial growth region, only stacked fin 150a on both sides of the gate structure 160, the selective epitaxial growth starting area 109a, 109b on 150b. 参见图10〜11,位于栅极结构160 —侧的生长出的源极外延区109a围绕在位于栅极结构160该同侧的堆叠式鳍片150a的两侧及上方,而位于栅极结构160相对的另一侧的生长出的漏极外延区109b则围绕在位于栅极结构160另一侧的每个堆叠式鳍片150b的两侧及上方。 Referring to FIG. 10~11, the gate structure 160-- growth side out of the epitaxial source region 109a located above and around the sides of the gate structure 160 is stacked on the same side of the fins 150a, and the gate structure 160 the opposite side of the drain epitaxial region grown around the sides and 109b are stacked above each fin 150b located on the other side of the gate structure 160. 在一些可选但不作限制的实施方式中,N型沟道的FinFET所外延生长的源极/漏极外延区109a、109b包括具拉伸应变能力的SiC外延区,P型沟道的FinFET所外延生长的源极/漏极外延区109a、109b包括具压缩应变的SiGe外延区,来改变载流子的迁移率。 In some embodiments, but is not limited alternative embodiment, the source of N-channel FinFET the epitaxially grown source / drain extension regions 109a, 109b having a tensile strain capacity including SiC epitaxial region, P-type channel of the FinFET epitaxially grown source / drain extension regions 109a, 109b includes a region having a strained SiGe epitaxial compression, to change the mobility of carriers.

[0042] 图12A〜12H的方法流程是以矩形的上部鳍片代替梯形的上部鳍片的一种实施例。 The method of flow [0042] FIG 12A~12H made on one rectangular instead of trapezoidal upper portion of the upper fin fin embodiments. 在图12A中,利用常规的光刻工艺,图案化硬掩膜层105形成其中的开口图形,例如刻蚀出硬掩膜层105中的开口105a,然后再利用硬掩膜层105作为一个刻蚀掩膜,对其下方的顶部外延层104进行刻蚀。 In Figure 12A, using conventional photolithographic process, the patterned hard mask layer 105 is an opening pattern formed therein, for example, an opening 105a is etched hard mask layer 105, and then using the hard mask layer 105 as a carved etching mask, its top epitaxial layer 104 is etched below. 干法刻蚀顶部外延层104,从而顶部外延层104暴露在开口105a中的区域将被刻蚀掉,顶部外延层104形成了多个条状的上部鳍片104',它们彼此间大体平行排列,相邻上部鳍片104'间的贯穿顶部外延层104的刻蚀沟槽将它们分离断开,注意此时的上部鳍片104'具有大体垂直的侧壁形貌。 Dry etching the top epitaxial layer 104, so that the top of the epitaxial layer 104 exposed in the opening 105a in a region to be etched away, top of the epitaxial layer 104 is formed of a plurality of strip-shaped upper fin 104 ', are arranged substantially parallel to one another between , adjacent the upper fin 104 'etching grooves through the top epitaxial layer 104 between the disconnect to separate them. Note that the upper portion of the fin 104' having substantially vertical sidewalls morphology. 在刻蚀顶部外延层104时,底部外延层103的材质能够抵抗对顶部外延层104执行的刻蚀工艺,而不受该刻蚀步骤的影响。 When etching the top of the epitaxial layer 104, epitaxial material of the bottom layer 103 against the etching process can be performed on top of the epitaxial layer 104, without being affected by the etching step. 然后沉积一层牺牲侧墙层110,如图2B所示,侧墙层110典型的如二氧化硅或氮化硅等,此时牺牲侧墙层110覆盖在硬掩膜层105的顶面上,和附着在开口105a的内壁上,还附着在上部鳍片104'的侧壁上和覆盖在底部外延层103未被上部鳍片104'覆盖住而裸露的上表面上,之后各向同性回刻蚀牺牲侧墙层110,将硬掩膜层105的顶面上和底部外延层103的顶面上所覆盖的牺牲侧墙层110刻蚀移除掉,如图12C所示。 Then depositing a sacrificial spacer layer 110, as shown, a typical spacer layer 110 such as silicon dioxide or silicon nitride, etc. 2B, at this time the sacrificial spacer layer 110 covers the top surface 105 of hard mask layer , and adhered to the inner wall of the opening 105a, it is also attached to 'on the side wall 103 and covering the upper portion of the fin is not the bottom of the epitaxial layer 104' covering an upper portion of the fin 104 and the exposed upper surface, then back isotropically etching the sacrificial spacer layer 110, the top surface of the hard mask layer 105 on the top surface and the bottom 103 of the epitaxial layer covered by the sacrificial spacer layer 110 is etched away removal, shown in Figure 12C. 牺牲侧墙层110经刻蚀后仅仅保留下所形成的牺牲侧墙110',其附着在开口105a的内壁上和上部鳍片104'的侧壁上。 After the sacrificial spacer layer 110 is etched to retain only the sacrificial sidewall spacer formed at 110 ', which is attached to the inner wall of the opening 105a and an upper fin 104' on the side wall. 如图12D〜12E所示,利用牺牲侧墙110'、上部鳍片104'和硬掩膜层105作为掩膜,刻蚀底部外延层103未被上部鳍片104'或牺牲侧墙110'覆盖住而暴露的区域,形成下部鳍片103,。 As shown in FIG 12D~12E, using sacrificial spacers 110 ', an upper fin 104' and the hard mask layer 105 as a mask, etching the upper portion of the fin 103 is not the bottom of the epitaxial layer 104 'or the sacrificial sidewall spacer 110' covered live exposed region, form a lower fin 103 ,.

[0043] 在一种实施方式中,下部鳍片103'可以经由各向同性刻蚀底部外延层103先形成其垂直侧壁,如图12D,然后采用各向异性刻蚀,在下部鳍片103'的垂直侧壁上刻蚀形成向内侧凹进的凹槽,如图12E,凹槽的存在导致下部鳍片103'的侧壁具有相对竖直方向而呈现为倾斜面的上侧壁103' a和倾斜面的下侧壁103' b。 [0043] In one embodiment, the lower fin 103 'may be formed by isotropic etching to the bottom of the vertical sidewalls of the epitaxial layer 103, as shown in FIG 12D, and then anisotropic etching, at the lower fin 103 'formed on the vertical sidewalls etched recess inwardly recessed, as shown in FIG 12E, the presence of grooves results in a lower portion of fin 103' having relatively vertical side walls on the side wall presenting an inclined surface 103 ' a lower side wall and an inclined surface 103 'b. 在此步骤中,掩埋绝缘层102不受刻蚀的影响,并且在形成矩形状的上部鳍片104'和沙漏状的下部鳍片103'之后,需要将硬掩膜层105和牺牲侧墙110'剥离移除掉,如图12F所示。 After this step, the buried insulating layer 102 not affect etching, is formed in a rectangular shape and an upper fin 104 'and the hourglass-shaped lower fin 103' needs to be sacrificial hard mask layer 105 and spacers 110 'peeled off is removed, as shown in FIG 12F. 在另一些可选实施例中,以硬掩膜层105、上部鳍片104'和牺牲侧墙110'作为掩膜,不采用干法刻蚀而直接采用各向异性的湿法刻蚀对底部外延层103暴露的区域进行刻蚀,不形成下部鳍片103'的过渡的垂直侧壁,而是直接形成侧壁上的倾斜面即上侧壁103' a和下侧壁103' b,这样的侧壁又可称之为Σ形侧壁。 In other alternative embodiments, hard mask layer 105, an upper fin 104 'and the sacrificial spacer 110' as a mask, dry etching is not used directly in an anisotropic wet etching bottom the exposed area of ​​the epitaxial layer 103 is etched to form the lower fin 103 is not 'vertical sidewalls of the transition, but directly on an inclined surface, i.e., the side wall on the side wall 103' and the lower sidewall 103 a 'B, so sidewall in turn called Σ-shaped side wall. 从而底部外延层103籍由刻蚀而形成了多个条状的下部鳍片103',相邻下部鳍片103'间的贯穿整个底部外延层103厚度的刻蚀沟槽将它们分离断开,这些下部鳍片103'彼此间大体平行排列设置。 So that the bottom of the epitaxial layer 103 is etched to form a membership from a plurality of stripe-shaped lower portion of the fins 103 ', 103 adjacent the lower portion of the fin' trench 103 etched through the epitaxial layer thickness of the entire bottom between the disconnect to separate them, the lower portion of the fins 103 'are arranged substantially parallel to each other. 在刻蚀底部外延层103时,顶部外延层104的材质是否能够抵抗对底部外延层103执行的刻蚀工艺变得不再重要,因为它一直受到硬掩膜层105和牺牲侧墙110'的保护。 When etching the bottom of the epitaxial layer 103, epitaxial layer 104 on top of the material is able to resist to the bottom of the epitaxial layer 103 etching process is performed is no longer important, since it has been hard mask layer 105 and the sacrificial spacer 110 ' protection.

[0044] 图12G〜12H的方法步骤与图8〜11的步骤基本大体相同,因此不再赘述。 Step [0044] FIG 12G~12H FIG 8~11 method steps substantially the same as the basic, and therefore omitted. 但值得注意的是,与图8〜11最大的区别是,在图12G〜12H的FinFET器件中,上部鳍片104'的竖剖面已经不再是上窄下宽的梯形,其剖面却是一个上下宽度相等的方形,而此时的堆叠式鳍片150包括一沙漏状的下部鳍片103'和位于下部鳍片103'之上的一方形状的上部鳍片104'。 It is noteworthy that, with the biggest difference is that in FIG. 8~11 in FIG 12G~12H FinFET device, the upper fin 104 'is no longer a vertical cross-sectional view on the narrow width of the trapezoid, which is a sectional vertical width equal to the square, but this time the stacked fin 150 comprises a fin hourglass-shaped lower portion 103 'and a lower fin 103 is located "above the upper one of the shape of the fin 104'. 很容易从图12A〜12F的步骤中获悉,上部鳍片104'具有大体垂直的侧壁形貌在后续步骤中一直受到牺牲侧墙110'的保护,其侧壁上并不会被腐蚀出Σ形凹槽,所以上部鳍片104'的方形结构得以保持。 Easily learned from FIG 12A~12F step, the upper fin 104 'having substantially vertical sidewalls morphology sacrificial sidewall spacer 110 has been in a subsequent step' protection, which will not be etched sidewalls Σ shaped groove, so that the upper portion of the fin 104 'of a square configuration is maintained.

[0045] 在一些实施方式中,碱性的腐蚀液被用来刻蚀形成带有凹槽的Σ形的侧壁,例如本发明中制备下部鳍片103'和上部鳍片104'各自的Σ形侧壁,典型的可采用如含四甲基氢氧化铵(TMAH),或NH4OH,或NaOH,或Κ0Η,或乙二胺邻苯二酹(Ethylenediaminepyrocatechol, EDP)的腐蚀液等。 [0045] In some embodiments, the alkaline etchant is used to etch a recess formed in the sidewall of the Σ-shaped with, for example, a lower fin 103 'and the upper fins 104' of the present invention prepared in the respective Σ side wall, typically employed such as those containing tetramethylammonium hydroxide (of TMAH), or NH40H, or NaOH, or Κ0Η, phthalimido or ethylenediamine sprinkle (Ethylenediaminepyrocatechol, EDP) etching solution and the like.

[0046] 以上,通过说明和附图,给出了具体实施方式的特定结构的典型实施例,上述发明提出了现有的较佳实施例,但这些内容并不作为局限。 Typical [0046] The above description and drawings, particular embodiments are given the particular structure of the embodiments of the invention proposes a presently preferred embodiment, but the content is not by way of limitation. 对于本领域的技术人员而言,阅读上述说明后,各种变化和修正无疑将显而易见。 Those skilled in the art, upon reading the foregoing description, various changes and modifications will no doubt become apparent. 因此,所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。 Accordingly, the appended claims should be considered all alterations and modifications to cover the true spirit and scope of the present invention. 在权利要求书范围内任何和所有等价的范围与内容,都应认为仍属本发明的意图和范围内。 Within the scope of the appended claims and any and all equivalents ranges content, to be considered within the spirit and scope of the present invention still.

Claims (16)

  1. 1.一种FinFET半导体器件,其特征在于,包括: 一衬底和位于衬底之上的堆叠式鳍片; 围绕在堆叠式鳍片两侧及上方的栅极结构; 其中所述堆叠式鳍片包括一沙漏状的下部鳍片和位于下部鳍片之上的一梯形状的上部鳍片。 A FinFET semiconductor device comprising: a substrate and stacked fins positioned above the substrate; around both sides of the fin and the gate stacked structure above; wherein the stacked fins a sheet comprising an hourglass-shaped lower fins and upper fins positioned on a lower portion of trapezoidal fins.
  2. 2.如权利要求1所述的FinFET半导体器件,其特征在于,所述上部和下部鳍片两者中之一为Si材质,另一者为SiGe材质。 2. The FinFET semiconductor device according to claim 1, wherein one of said upper and lower fins of both Si material, the other material is SiGe.
  3. 3.如权利要求1所述的FinFET半导体器件,其特征在于,所述衬底包含一底部衬底和位于底部衬底之上的掩埋绝缘层,所述堆叠式鳍片设置在掩埋绝缘层上方。 3. The FinFET semiconductor device according to claim 1, wherein the substrate comprises a base substrate and the buried insulating layer is disposed on the base substrate, the stacked fins disposed over the buried insulating layer .
  4. 4.如权利要求1所述的FinFET半导体器件,其特征在于,位于栅极结构两侧的堆叠式鳍片,其两侧及上方设置有源极/漏极外延区。 4. The FinFET semiconductor device according to claim 1, wherein the fins located on both sides of the gate stacked structure disposed on both sides thereof and over the active source / drain epitaxial region.
  5. 5.如权利要求4所述的FinFET半导体器件,其特征在于,N型FinFET的源极/漏极外延区包括拉伸应变的SiC外延区,P型FinFET的源极/漏极外延区包括压缩应变的SiGe外延区。 5. The FinFET semiconductor device according to claim 4, characterized in that the source of the N-type FinFET source / drain region comprises an epitaxial SiC epitaxial tensile strained region, the P-type FinFET source / drain regions comprising epitaxially compression strained SiGe epitaxial region.
  6. 6.一种FinFET半导体器件,其特征在于,包括: 一衬底和位于衬底之上的堆叠式鳍片; 围绕在堆叠式鳍片两侧及上方的栅极结构; 其中所述堆叠式鳍片包括一沙漏状的下部鳍片和位于下部鳍片之上的一方形状的上部鳍片。 A FinFET semiconductor device, characterized by comprising: a substrate and stacked fins positioned above the substrate; around both sides of the fin and the gate stacked structure above; wherein the stacked fins a sheet comprising an hourglass-shaped lower fins and upper fins positioned one above the lower portion of the fin shape.
  7. 7.—种FinFET半导体器件的制备方法,其特征在于,包括以下步骤: 提供一包含第一、第二半导体层的衬底; 刻蚀第一半导体层形成上部鳍片; 刻蚀第二半导体层未被上部鳍片覆盖住的区域以形成上部鳍片下方的呈沙漏状的下部鳍片; 形成围绕在包含上部、下部鳍片的堆叠式鳍片两侧及上方的栅极结构。 7.- preparation methods FinFET semiconductor device, characterized by comprising the steps of: providing a substrate comprising a first, a second semiconductor layer; and etching the first semiconductor layer is formed in an upper portion of the fin; etching the second semiconductor layer, not live coverage area of ​​the upper fin to form a lower hourglass-shaped fins below the upper portion of the fin; forming a stacked gate structure on both sides and over the fin comprising an upper portion, a lower portion of the fin around.
  8. 8.如权利要求7所述的方法,其特征在于,形成上部鳍片的步骤中,在第一半导体层上方形成一硬掩膜层并图案化该硬掩膜层; 利用带有开口图形的硬掩膜层干法刻蚀第一半导体层暴露的区域,形成第一半导体层中深度小于第一半导体层原始厚度的沟槽; 利用硬掩膜层沿着所述沟槽以各向异性湿法刻蚀第一半导体层,从而形成上窄下宽的梯形状上部鳍片。 8. The method according to claim 7, wherein the step of forming an upper portion of the fin, forming a hard mask layer and patterning the hard mask layer over the first semiconductor layer; using a pattern with an opening dry etching the hard mask layer a first exposed region of the semiconductor layer, forming a trench depth less than the original thickness of the first semiconductor layer of a first semiconductor layer; layer using the hard mask along the trench to anisotropic wet etching the first semiconductor layer, thereby forming a trapezoidal shape of the upper fin of the narrow width.
  9. 9.如权利要求8所述的方法,其特征在于,形成下部鳍片的步骤中,对第二半导体层暴露的区域进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 9. The method according to claim 8, wherein the step of forming the lower portion of the fin, a second semiconductor layer on the exposed region of the anisotropic wet etching, a width larger than the intermediate top and bottom portions a lower portion of the fin width hourglass.
  10. 10.如权利要求8所述的方法,其特征在于,形成下部鳍片的步骤中,先利用硬掩膜层干法刻蚀第二半导体层,形成带有垂直侧壁形貌的下部鳍片; 然后对下部鳍片暴露的侧壁进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 10. The method according to claim 8, wherein forming the lower fins, the first hard mask layer using a dry-etching the second semiconductor layer, the fin is formed with a lower vertical sidewalls morphology ; then exposed sidewalls of the lower fins anisotropic wet etching, is formed larger than the width of the top and bottom of the hourglass-shaped lower portion of the intermediate portion of the width of the fin.
  11. 11.如权利要求7所述的方法,其特征在于,形成上部鳍片的步骤中,利用硬掩膜层干法刻蚀第一半导体层,从而形成带有垂直侧壁形貌的上部鳍片; 然后在硬掩膜层中的开口的内壁、上部鳍片的侧壁和在硬掩膜层的顶面上覆盖一牺牲侧墙层; 回蚀牺牲侧墙层形成覆盖在开口内壁和上部鳍片的侧壁上的牺牲侧墙; 利用牺牲侧墙和硬掩膜层刻蚀第二半导体层暴露的区域,形成下部鳍片。 11. The method according to claim 7, wherein the step of forming an upper portion of the fin, the hard mask layer using a dry-etching the first semiconductor layer to form an upper fin with vertical sidewalls Morphology ; and the inner wall of the opening in the hard mask layer, covering the sidewalls and upper fins sacrificial spacer layer on a top surface of the hard mask layer; etching back the sacrificial spacer layer is formed to cover the inner wall of the opening and an upper fin sacrificial sidewall spacer on the sidewalls of the sheet; a sacrificial spacers and the hard mask layer etching the exposed region of the second semiconductor layer, forming a lower portion of the fin.
  12. 12.如权利要求11所述的方法,其特征在于,形成下部鳍片的步骤中,对第二半导体层暴露的区域进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 Width 12. The method according to claim 11, characterized in that the lower portion of the fin is formed in the second semiconductor layer on the exposed region of anisotropically wet etched to form the top and bottom larger than the intermediate portion a lower portion of the fin width hourglass.
  13. 13.如权利要求11所述的方法,其特征在于,形成下部鳍片的步骤中,先利用硬掩膜层和牺牲侧墙干法刻蚀第二半导体层,形成带有垂直侧壁形貌的下部鳍片; 然后对下部鳍片暴露的侧壁进行各向异性的湿法刻蚀,形成顶部和底部的宽度大于中间部宽度的沙漏状下部鳍片。 13. The method according to claim 11, wherein, in the formation of the lower fins, and the first sacrificial hard mask layer using a dry etching the second spacer semiconductor layer formed with the vertical sidewall morphology the lower portion of the fin; fins and the lower sidewall of the exposed anisotropically wet etched to form the top and bottom of the hourglass a lower width greater than the width of the intermediate fins.
  14. 14.如权利要求7所述的方法,其特征在于,形成栅极结构之后,以栅极结构为自对准掩膜在上部鳍片的上表面注入轻掺杂源/漏区;以及然后在栅极结构的侧壁上形成侧墙,并在栅极结构两侧的堆叠式鳍片中植入源极/漏极掺杂区。 14. The method according to claim 7, wherein, after forming the gate structure, the gate structure as a mask a self-aligned implantation lightly doped source / drain regions on the upper surface of the fin; and then forming sidewall spacers on the gate structure, and implanting source / drain doped regions in a stacked gate structure on both sides of the fin.
  15. 15.如权利要求7所述的方法,其特征在于,形成栅极结构之后,在栅极结构两侧的堆叠式鳍片的两侧及上方选择性的外延生长源极/漏极外延区。 After 15. The method according to claim 7, wherein the gate structure is formed, the epitaxial growth of source / drain regions on both sides and selective epitaxial stacked above the gate structure on both sides of the fin.
  16. 16.如权利要求15所述的方法,其特征在于,N型FinFET所外延生长的源极/漏极外延区包括拉伸应变的SiC外延区,P型FinFET所外延生长的源极/漏极外延区包括压缩应变的SiGe外延区。 16. The method according to claim 15, wherein the source of the N-type FinFET epitaxially grown source / drain regions include source and tensile strained epitaxial SiC epitaxial region, P-type FinFET is epitaxially grown source / drain epitaxial region comprises a compression strained SiGe epitaxial region.
CN 201410011019 2014-01-09 2014-01-09 FINFET (Fin Field Effect Transistor) semiconductor device and manufacturing method thereof CN104779285A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6972461B1 (en) * 2004-06-30 2005-12-06 International Business Machines Corporation Channel MOSFET with strained silicon channel on strained SiGe
WO2007002426A2 (en) * 2005-06-21 2007-01-04 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
US20090072279A1 (en) * 2007-08-29 2009-03-19 Ecole Polytechnique Federale De Lausanne (Epfl) Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (PI-MOS)
CN103022100A (en) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 Structure for finned field effect transistor and forming method of finned field effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6972461B1 (en) * 2004-06-30 2005-12-06 International Business Machines Corporation Channel MOSFET with strained silicon channel on strained SiGe
WO2007002426A2 (en) * 2005-06-21 2007-01-04 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
US20090072279A1 (en) * 2007-08-29 2009-03-19 Ecole Polytechnique Federale De Lausanne (Epfl) Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (PI-MOS)
CN103022100A (en) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 Structure for finned field effect transistor and forming method of finned field effect transistor

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