CN103915316A - Stacked nanowire fabrication method - Google Patents

Stacked nanowire fabrication method Download PDF

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CN103915316A
CN103915316A CN201310007063.5A CN201310007063A CN103915316A CN 103915316 A CN103915316 A CN 103915316A CN 201310007063 A CN201310007063 A CN 201310007063A CN 103915316 A CN103915316 A CN 103915316A
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nano wire
groove
substrate
fin
etching
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CN103915316B (en
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马小龙
殷华湘
秦长亮
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a stacked nanowire manufacturing method, which comprises the following steps: step a, forming a hard mask on a substrate; step b, anisotropically etching the substrate to form a first groove and a fin; step c, corroding the fins and the lower substrate by a wet method, and forming a second groove on the side surface of the first groove; repeating the steps b to c for multiple times to form a plurality of fins stacked up and down; and d, rounding the fins to form stacked nanowires. According to the manufacturing method of the stacked nanowire, the dry etching and the wet etching are combined, the high-precision stacked nanowire is formed by utilizing double internal cutting corrosion, the miniaturization of a device is facilitated, and the cost is reduced.

Description

Stacking nano wire manufacture method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to a kind of manufacture method of stacking nano wire.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, this structural reinforcing grid control ability, suppressed electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, can suppress short-channel effect (SCE) and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, can realize raceway groove light dope, can carry out adjusting threshold voltage by the work function that metal gates is set, can obtain the drive current of approximately 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid has surrounded channel region end face and two sides, and grid control ability is stronger.Further, loopful has more advantage around nano wire multiple-grid device.
At loopful, in the manufacture process of nano wire multiple-grid device, a kind of known method is as follows: on Si substrate, form hard mask, adopt SF 6the isotropic plasma of etching gas is dry-etched in the substrate of hard mask below and forms the first groove of indent slightly, leaves backing material and form fin structure between the first relative groove; Adopt high density C xthe plasma etching of F (carbon fluorine is higher) etching gas, on substrate and the first trenched side-wall form passivation layer; SF again 6anisotropic etching, removes passivation layer on substrate, leaves the passivation layer of the first groove madial wall; SF 6isotropic etching, continues etched substrate, forms the second groove in the first beneath trenches; The like, form multiple grooves and fin structure; Fin structure between oxidation groove, removes oxide, leaves nano-wire array.The method technology controlling and process difficulty, nanowire density is less, and consistency is poor.
Another kind of known method comprises: on SOI substrate, extension forms the overlapping epitaxial loayer of Si and Ge/SiGe successively, forms hard mask layer at top layer, and etching forms grid lines, and the Ge/SiGe layer between selective etch removal adjacent S i layer, leaves Si nano wire.The method is limited to Ge/SiGe bed boundary poor performance, and process costs is high, is difficult to popularize.
In view of the trench fabrication methods simple process comparatively speaking of Σ shape section, as long as the relatively good control anisotropic etching of energy is expected to form even, highdensity stacking nano wire.
Summary of the invention
From the above mentioned, the object of the present invention is to provide a kind of energy low cost, efficient stacking nano wire manufacture method.
For this reason, the invention provides a kind of stacking nano wire manufacture method, comprising: step a forms hard mask on substrate; Step b, anisotropic etching substrate forms the first groove and fin; Step c, wet etching fin and below substrate, form the second groove in the first groove side surface; Wherein, repeatedly repeating step b, to step c, forms multiple fins of stacked on top of one another; Steps d, mellow and fullization fin, forms stacking nano wire.
Wherein, substrate is body Si or SOI.
Wherein, substrate is (100) crystal face.
Wherein, the anisotropic etching of step b is dry etching.Wherein, dry etching is RIE.Wherein, etching gas comprises fluorine base gas.
Wherein, after step c, before steps d, also comprise: step c1, anisotropic etching substrate forms another and organizes the first groove and fin; Step c2, isotropic etching fin and below substrate, form the 3rd groove in the first groove side surface; Wherein, repeatedly repeating step b, step c, step c1, step c2, multiple fins of formation stacked on top of one another.
Wherein, the first groove of formation has vertical sidewall.
Wherein, the first trenched side-wall is (110) face, and substrate is (100) face.
Wherein, wet etching liquid comprises TMAH.
Wherein, steps d further comprises: form oxide layer on fin surface; Remove oxide layer, expose fin; Under atmosphere of hydrogen, anneal, make mellow and fullization of fin, form stacking nano wire.
Wherein, the first trenched side-wall is (110) face, and substrate is (100) face.
Wherein, the second trenched side-wall is (111) face.
Wherein, the 3rd trenched side-wall is (110) face.
According to stacking nano wire manufacture method of the present invention, combine dry etching and wet etching, utilize dual inscribe corrosion to form the stacking nano wire of high accuracy, be conducive to device miniaturization, reduce cost.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 8 is the cut-away view according to the each step of manufacture method of first embodiment of the invention;
Fig. 9 to Figure 15 is the cutaway view according to the each step of manufacture method of second embodiment of the invention;
Figure 16 is the indicative flowchart according to first embodiment of the present invention manufacture method; And
Figure 17 is the indicative flowchart according to second embodiment of the present invention manufacture method.
Embodiment
The feature and the technique effect thereof that also describe technical solution of the present invention referring to accompanying drawing in conjunction with schematic embodiment in detail, disclose energy low cost, efficient stacking nano wire manufacture method.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
First, describe the each step of method, semi-conductor device manufacturing method according to first embodiment of the invention in detail below with reference to the flow chart of Figure 16 and referring to figs. 1 through the generalized section of Fig. 8.
As shown in Figure 1, provide substrate 1.Substrate 1 needs and choose reasonable according to device purposes, can comprise monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.Preferably, substrate 1 for body Si so that with CMOS process compatible for making large scale integrated circuit.More preferably, substrate 1 is (100) crystal face.
As shown in Figure 2, on substrate 1, form hard mask 2.By conventional methods such as LPCVD, PECVD, UHVCVD, HDPCVD, thermal oxidation, chemical oxidation, MBE, ALD, evaporation, sputters, on substrate 1, form hard mask layer, and utilize already known processes photoetching/etching to form hard mask graph 2.The material of hard mask 2 can be silica, silicon nitride, silicon oxynitride and combination thereof.
As shown in Figure 3, etched substrate 1 forms the first groove 1G, and substrate 1 remainder that hard mask 2 belows stay forms the first fin 1F.Etching is preferably anisotropic etching, taking the sidewall that makes the first groove 1G as (substantially) vertical.Anisotropic etching is fluorine base gas (for example carbon fluorine base gas C preferably xh yf z, wherein x is that 1～4, y is that 0～8, z is that 1～8, xyz three quantitative relation meets and makes above-mentioned chemical formula form fluoro (saturated or unsaturated) alkene or alkane; In addition can be also SF 6, NF 3) plasma dry etching, so that accurately control etching depth d by controlling etching condition e, and then control final nanowire height/thickness.It is (110) face that etching makes the sidewall of the first groove 1G, and substrate 1 surface is still (100) face.
As shown in Figure 4, carry out wet etching, etching fin 1F and substrate 1, form the second groove 1G ' in the first groove 1G side.The corrosive liquid of wet etching is Tetramethylammonium hydroxide (TMAH), the first fin 1F between etching the first groove 1G, and in fin 1F, (the first groove 1G side) forms the second groove 1G '.In wet etching course, (111) face corrosion rate of Si material is significantly lower than (100) face and (110) face, and therefore etching finally terminates on (111) face.In addition can be by controlling speed and the time of wet etching, the profile morphology that makes the second groove 1G ' is triangle substantially.As shown in Figure 4, in first embodiment of the invention, the second groove 1G ' does not make fin 1F break-through, but between the second relative groove, leaves a small amount of part that is connected.Certainly, alternatively, the second groove 1G ' also can break-through, and fin 1F is separated with below substrate (or follow-up fin).It should be noted that, in this process, because sidewall is (110) face, and substrate is (100) face, therefore TMAH for the corrosion rate of sidewall slightly lower than substrate, thereby making the second groove 1G ' bottom width be greater than top width, is also that groove end points is not on vertical line.Follow-uply to carry out further technique the second groove end points is distributed on vertical line.
As shown in Figure 5, carry out anisotropic etching, etched substrate 1, is etched the substrate part of fin 1F below sloped sidewall and forms another group fin 1F ' with vertical sidewall, and the groove between fin 1F ' has the first groove 1G of vertical sidewall for another group.Anisotropic etching can be above-mentioned dry etching, for example plasma etching or reactive ion etching (RIE), and the sidewall of the fin 1F ' that etching forms is (110) crystal face, substrate is still (100) crystal face.V-groove that it should be noted that substrate 1 surface in Fig. 4 is still conformally formed in Fig. 5, and the sloped sidewall of fin 1F below part is etched and is modified to vertical sidewall, and therefore the upper and lower end points of the second groove 1G ' is finally distributed on a vertical line.So, by the blocked operation of isotropic etching and anisotropic etching, can make Σ type profile groove also can be used to form evenly neat nano wire stacking.
As shown in Figure 6, similar with technique shown in Fig. 4, carry out wet etching, continue another group fin of etching 1F ', form therein another and organize the second groove 1G '.Correspondingly, the second groove 11G ' now upper and lower end points not on a vertical line.
As shown in Figure 7, similar with technique shown in Fig. 5, carry out anisotropic etching, eliminate the second outstanding part in groove 1G ' below, make another group fin 1F ' there is vertical sidewall.
As shown in Figure 8, similar with technique shown in Fig. 4 or Fig. 6, carry out TMAH wet etching, form another group of fin 1F " and the second groove 1G ".
After this, can carry out subsequent technique processing with attenuate fin structure.Conventional method comprises the method that adopts thermal oxidation, chemical oxidation, at fin structure 1F/1F '/1F " surface formation oxide layer (not shown, for example silica), and make remaining fin structure 1F/1F '/1F " formation nano wire 1NW.Preferably, can further in atmosphere of hydrogen, anneal, make residue ground fin structure 1F/1F '/1F " surperficial mellow and fullization, the conglobate nano wire 1NW of shape.Subsequently, remove surperficial oxide layer, leave nano wire 1NW.Removal method is for example that whole device wafer immerses HF base corrosive liquid (dHF or dBOE (slowly-releasing etching agent)), and the oxide layer of erosion removal silica material only leaves the gate line strip array of the stacking formation of multiple nano wire 1NW.
Fig. 9 is to the each step cutaway view of process Figure 15 shows that according to second embodiment of the invention, and Figure 17 is its indicative flowchart.
As shown in Fig. 9～Figure 13, similar or identical with Fig. 1 to Fig. 5 of embodiment 1, on substrate 1, form hard mask 2, anisotropic etching substrate 1 forms the first groove 1G of fin 1F and vertical sidewall, TMAH wet etching fin 1F and substrate 1 form the second groove 1G ' of indent, anisotropic etching fin 1F below substrate makes the upper and lower end points of the second groove 1G ' on vertical line, also makes fin 1F below another group fin 1F ' have vertical sidewall.Wherein, etching shown in Figure 13 can be reactive ion etching (RIE), etching gas can be above-mentioned carbon fluorine base gas, for example, by adjusting gas mixing ratio (fall low fluorine content, improve hydrocarbon content and can improve isotropism, improve fluorine content and can improve anisotropy), to make RIE be anisotropy.All the other processing steps are similar or identical, therefore repeat no more.
As different from Example 1, embodiment 2 formed first group of fin 1F, the first groove 1G and repaired the second groove 1G ' make its upper and lower side on vertical line after, it not the circulation step of the next TMAH wet etching of continuation as shown in Figure 6, but as shown in figure 14, adopt isotropic RIE to form the 3rd groove 1G ".Can for example, by adjusting gas mixing ratio (fall low fluorine content, improve hydrocarbon content and can improve isotropism, improve fluorine content and can improve anisotropy), to make this RIE be isotropism.It should be noted that, although the 3rd groove 1G " be circular arc shown in profile morphology figure; in fact can not be all various rational shapes according to etching condition, such as semicircle (D type), large semicircle (C type), ellipse, parabola, hyperbola etc. and combination thereof.The 3rd groove 1G herein " lower width still may be more than or equal to upper width, but can make finally to make the 3rd groove 1G by adjusting RIE technological parameter " wide up and down.
As shown in figure 15, repeat processing step shown in Fig. 9 to Figure 14, adopt isotropism RIE etching to form multiple the second groove 1G ' and multiple the 3rd groove 1G ".
Finally, can, with reference to embodiment 1, continue subsequent technique, complete nano wire stacking.
According to stacking nano wire manufacture method of the present invention, combine dry etching and wet etching, utilize dual inscribe corrosion to form the stacking nano wire of high accuracy, be conducive to device miniaturization, reduce cost.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (11)

1. a stacking nano wire manufacture method, comprising:
Step a forms hard mask on substrate;
Step b, anisotropic etching substrate forms the first groove and fin;
Step c, wet etching fin and below substrate, form the second groove in the first groove side surface;
Wherein, repeatedly repeating step b, to step c, forms multiple fins of stacked on top of one another;
Steps d, mellow and fullization fin, forms stacking nano wire.
2. stacking nano wire manufacture method as claimed in claim 1, wherein, substrate is body Si or SOI.
3. stacking nano wire manufacture method as claimed in claim 1, wherein, substrate is (100) crystal face.
4. stacking nano wire manufacture method as claimed in claim 1, wherein, the anisotropic etching of step b is dry etching.
5. stacking nano wire manufacture method as claimed in claim 4, wherein, dry etching is RIE.
6. stacking nano wire manufacture method as claimed in claim 5, wherein, etching gas comprises fluorine base gas.
7. stacking nano wire manufacture method as claimed in claim 1, wherein, also comprises after step c, before steps d: step c1, and anisotropic etching substrate forms another and organizes the first groove and fin; Step c2, isotropic etching fin and below substrate, form the 3rd groove in the first groove side surface; Wherein, repeatedly repeating step b, step c, step c1, step c2, multiple fins of formation stacked on top of one another.
8. stacking nano wire manufacture method as claimed in claim 1, wherein, the first groove of formation has vertical sidewall.
9. stacking nano wire manufacture method as claimed in claim 6, wherein, the first trenched side-wall is (110) face, substrate is (100) face.
10. stacking nano wire manufacture method as claimed in claim 1, wherein, wet etching liquid comprises TMAH.
11. stacking nano wire manufacture methods as claimed in claim 1, wherein, steps d further comprises: form oxide layer on fin surface; Remove oxide layer, expose fin; Under atmosphere of hydrogen, anneal, make mellow and fullization of fin, form stacking nano wire.
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CN105590845A (en) * 2015-12-25 2016-05-18 中国科学院微电子研究所 Method for manufacturing stacked fence nanowire
CN105719961A (en) * 2016-02-04 2016-06-29 中国科学院微电子研究所 Stacked nanowire fabrication method
CN105742175A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105742231A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105742239A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
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CN107437556A (en) * 2016-05-27 2017-12-05 中芯国际集成电路制造(上海)有限公司 GAA structures MOSFET forming method
CN107871666A (en) * 2017-09-25 2018-04-03 中国科学院上海微系统与信息技术研究所 The method for making the integrated semiconductor nanowires of vertical stacking and its field-effect transistor
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CN105742232B (en) * 2014-12-11 2019-01-18 中国科学院微电子研究所 Method for forming nanowire array
CN105742239A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105742231B (en) * 2014-12-11 2020-04-24 中国科学院微电子研究所 Method for forming nanowire array
CN105742231A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105742153B (en) * 2014-12-11 2019-09-24 中国科学院微电子研究所 Method of forming cascaded nanowires
CN105742153A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method of forming cascaded nanowires
CN105742232A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105742239B (en) * 2014-12-11 2018-12-11 中国科学院微电子研究所 Method for forming nanowire array
CN105742175A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN106298540A (en) * 2015-06-29 2017-01-04 台湾积体电路制造股份有限公司 There is the multiple gate field effect transistor of deoxidation gate stack
CN105590845A (en) * 2015-12-25 2016-05-18 中国科学院微电子研究所 Method for manufacturing stacked fence nanowire
CN105719961A (en) * 2016-02-04 2016-06-29 中国科学院微电子研究所 Stacked nanowire fabrication method
CN105719961B (en) * 2016-02-04 2018-08-10 中国科学院微电子研究所 Stacked nanowire fabrication method
CN107437556A (en) * 2016-05-27 2017-12-05 中芯国际集成电路制造(上海)有限公司 GAA structures MOSFET forming method
CN107871666A (en) * 2017-09-25 2018-04-03 中国科学院上海微系统与信息技术研究所 The method for making the integrated semiconductor nanowires of vertical stacking and its field-effect transistor
CN109888014A (en) * 2017-12-06 2019-06-14 中芯国际集成电路制造(上海)有限公司 Nano-wire devices and forming method thereof
CN109888014B (en) * 2017-12-06 2022-03-22 中芯国际集成电路制造(上海)有限公司 Nanowire device and method of forming the same

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