CN103311123B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
- Publication number
- CN103311123B CN103311123B CN201210067438.2A CN201210067438A CN103311123B CN 103311123 B CN103311123 B CN 103311123B CN 201210067438 A CN201210067438 A CN 201210067438A CN 103311123 B CN103311123 B CN 103311123B
- Authority
- CN
- China
- Prior art keywords
- hard mask
- mask layer
- group
- lines
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention discloses a kind of method, semi-conductor device manufacturing method, comprising: form the 2nd group of hard mask layer on substrate; 2nd group of hard mask layer forms first group of hard mask layer; Photoetching/etch first group of hard mask layer, forms first group of lines; Taking first group of lines as mask, photoetching/etching the 2nd group of hard mask layer, forms the 2nd group of lines, and wherein the 2nd group of line thickness is less than first group of line thickness; Taking the 2nd group of lines as mask, etched substrate, forms fin sheet. According to the method, semi-conductor device manufacturing method of the present invention, adopt multiplet structure mask, shelter with twice side wall and etch graphically, thus obtain the Nano-structure being less than photolithography limitation size. Technique is simple, precision height, and compatible high.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to a kind of employing twice side wall masking graphics to prepare the method for Nano-structure.
Background technology
Along with the development of time, the public is more and more higher for the performance requriements of the semiconducter device taking CMOS as representative, impels device architecture in mainstream CMOS processes to there occurs change with rapid changepl. never-ending changes and improvements. such as, just metal silicide is have employed to reduce source-drain contact resistance during more than 130nm technique, for ultra-shallow junctions (USJ) and stressor layers is then introduced to improve channel region carrier mobility during 90nm to 45nm technique, introduce high-k during 45nm to 28nm technique further (high k) to do gate insulator and adopt first grid technique or rear grid technique to make metal gates, then have employed many grid structures of such as FinFET to strengthen the control of grid for raceway groove when 22nm to 15nm, WeiLai Technology at below 15nm then comprises application III-V to improve driving force, channel fet is to reduce gate control voltage, nano wire (NW) structure is to realize device subminiaturization etc.
Such as, conventional MOSFET is taking body silicon as substrate, and depletion region is thicker, it is easy to form parasitic transistors influence device property. For this reason, developed SOIMOSFET, there is not latch-up, have more high operation speed, there is low-power consumption, Flouride-resistani acid phesphatase and the advantages such as 3 D stereo is integrated can be realized. Further, propose double gate SOI MOSFET, by setting up bottom grid in oxygen buried layer (BOX), reduce short-channel effect, leak induced barrier reduction effect thus enhance the ability of scaled down, there is lower junction capacitance, raceway groove light dope can be realized, threshold voltage can be adjusted by the work function of metal gate electrode, improve the driving electric current of nearly a times compared with SOIMOSFET, processing requirement for equivalent oxide thickness (EOT) is also lower in addition. Therefore, development multi-gate device, to improve device performance, is trend of the times.
Existing multi-gate device is generally divided into: a) double-gated devices, and such as GAA, SON etc. are double-deck gated device up and down, the double-deck gated device in the left and right such as MIGFET, and FinFET etc.;B) tri-gate devices, such as Tri-gate MOSFET, �� type grid device, �� type grid device etc.; C) grid device is surrounded, such as the nano-wire fet of quadruple ring grid device, annulus grid device and many bridges/stacking. These different device architectures often need different substrate materials, such as body silicon, SOI etc., therefore cause complex process, not compatible.
In addition, in order to control short-channel effect, it usually needs the thickness of grid is less than gate length, such as, in FinFET, fin grid is generally strip thin slice shape. Along with size constantly reduces, the requirement of equal proportion reduction is more and more higher, and the photoetching for the small size device grid taking FinFET as representative requires also more and more higher with etching imaging technique. Although utilizing side wall shelter etching technology that characteristic dimension can be accomplished below photolithography limitation size, but the super little ultra thin device for below 15nm, and prior art still faces significant challenge.
Summary of the invention
Described in upper, it is an object of the invention to provide a kind of efficient accurately, Nano-structure making method that technique is simple and compatible high.
For this reason, the present invention provides a kind of method, semi-conductor device manufacturing method, comprising: form the 2nd group of hard mask layer on substrate; 2nd group of hard mask layer forms first group of hard mask layer; Photoetching/etch first group of hard mask layer, forms first group of lines; Taking first group of lines as mask, photoetching/etching the 2nd group of hard mask layer, forms the 2nd group of lines, and wherein the 2nd group of line thickness is less than first group of line thickness; Taking the 2nd group of lines as mask, etched substrate, forms fin sheet.
Wherein, first group of hard mask layer comprises the first hard mask layer and the 2nd hard mask layer, and the 2nd group of hard mask layer comprises the 3rd hard mask layer and the 4th hard mask layer.
Wherein, the step forming first group of lines specifically comprises: photoetching/etching the 4th hard mask layer, forms the 4th hard mask pattern on the 3rd hard mask layer; The first side wall is formed in the 4th hard mask pattern both sides; Remove the 4th hard mask pattern; Taking the first side wall as mask, etching the 3rd hard mask layer also removes the first side wall, leaves the hard mask pattern of independent the 3rd on the 2nd hard mask layer, form first group of lines, wherein, the width of first group of lines equals the width of the first side wall, and is less than the width of the 4th hard mask pattern.
Wherein, the step forming the 2nd group of lines specifically comprises: form the 2nd side wall first group of lines both sides; Remove first group of lines; Taking the 2nd side wall as mask, etching the 2nd hard mask layer also removes the 2nd side wall, leaves the hard mask pattern of independent the 2nd on the first hard mask layer, form the 2nd group of lines, wherein, the width of the 2nd group of lines equals the width of the 2nd side wall, and is less than the width of first group of lines.
Wherein, the material of substrate, the first hard mask layer, the 2nd hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, the first side wall and the 2nd side wall is selected according to following principle: any two layers of adjacent material difference.
Wherein, the material of substrate, the first hard mask layer, the 2nd hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, the first side wall and the 2nd side wall is selected from following scope: silica-base material, silicon oxide, silicon nitride, silicon oxynitride.
Wherein, silica-base material comprises silicon single crystal, non-crystalline silicon, microcrystal silicon, low temperature polycrystalline silicon, high temperature polysilicon.
Wherein, the forming method of first group of hard mask layer and/or the 2nd group of hard mask layer comprises LPCVD, PECVD, HDPCVD, ALD, cryochemistry thing thermolysis deposition, sputtering, evaporation.
According to the method, semi-conductor device manufacturing method of the present invention, adopt multiplet structure mask, shelter with twice side wall and etch graphically, thus obtain the Nano-structure being less than photolithography limitation size. Technique is simple, precision height, and compatible high.
Accompanying drawing explanation
The technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 18 is the diagrammatic cross-section of each step of the manufacture method according to the present invention; And
Figure 19 is the manufacture method schema according to the present invention.
Embodiment
Referring to accompanying drawing and feature and the technique effect thereof of technical solution of the present invention are described in detail in conjunction with schematic embodiment, disclose efficient accurately, Nano-structure making method that technique is simple and compatible high. It is noted that similar Reference numeral represents similar structure, term " first " used in the application, " the 2nd ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process. These modify the space, order or the level relation that not imply institute's modification device architecture or manufacturing process unless stated otherwise.
Diagrammatic cross-section hereinafter with reference to Fig. 1 to Figure 18 illustrates each step of the manufacture method according to the present invention in detail.
First, with reference to Fig. 1, substrate forms multiple hard mask layer. Substrate 1 is provided, material is such as monocrystalline silicon, silicon-on-insulator (SOI), single crystal germanium (Ge), germanium on insulator (GeOI), strained silicon (StrainedSi), germanium silicon (SiGe), or compound semiconductor materials, such as gan (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc. Preferably, substrate 1 is body silicon or SOI, to improve the compatibility with other CMOS technology. Then, adopting the ordinary methods such as LPCVD, PECVD, HDPCVD, ALD, cryochemistry thing thermolysis deposition, sputtering, evaporation, deposit the first hard mask layer 2 on substrate 1, its material is such as silicon nitride (SiNx, x can be 1��2, is not limited to integer) or silicon oxynitride (SiOxNy, x, y can according to needs Reasonable adjustment). Depositing the 2nd hard mask layer 3 on the first hard mask layer 2, its material is such as the etching characteristics such as non-crystalline silicon, microcrystal silicon, high temperature polysilicon or low temperature polycrystalline silicon (p-Si) are different from the material of the first hard mask layer 2, its thickness such as 10��100nm. Such as adopt LPCVD formation of deposits non-crystalline silicon below 580 DEG C, selection of land laser illumination can be adopted to make non-crystalline silicon local-crystalized and form low temperature polycrystalline silicon or microcrystal silicon afterwards, or LPCVD formation of deposits high temperature polysilicon more than 580 DEG C. 2nd hard mask layer 3 deposits the 3rd hard mask layer 4, its material is such as different from the first hard mask layer 2 and the material of the 2nd hard mask layer 3 for etching characteristics such as silicon oxide, and deposition method is LPCVD, PECVD, HDPCVD, cryochemistry thing thermolysis deposition, sputtering, evaporation etc. such as. In addition, the 3rd hard mask layer 4 can also form doped-glass by the impurity such as in-situ doped B, P, C, N, O, As, to change etching characteristic. Depositing the 4th hard mask layer 5 on the 3rd hard mask layer 4, its material can be identical with the 2nd hard mask layer 3, such as, be p-Si. Preferably its thickness is greater than and equals the 2nd hard mask layer 3 to improve homogeneity when top layer etches and to obtain better conformality, and such as, when the 2nd hard mask layer 3 thickness is 10��50nm, the 4th hard mask layer 5 thickness is 50��100nm.Above four layers of hard mask layer 2,3,4,5 form four layer stackup structures from the bottom to top, therefore its layer 5 at the middle and upper levels and layer 4 can be called first group of hard mask layer for first time side wall forming process, and therefore the layer 3 of lower floor and layer 2 can be called the 2nd group of hard mask layer for second time side wall forming process. Can selection of land, layer 5/4/3/2 is not limited to above-mentioned concrete material and limits, as long as adjacent each layer material is different because having bigger etching selection ratio, it is possible to form meticulous etching figure. Such as, layer 5/4/3/2 can be p-Si/SiNx/p-Si/SiO2, or SiNx/p-Si/SiNx/SiO2, or p-Si/SiO2/p-Si/SiO2, or p-Si/SiNx/p-Si/SiNxEtc., and wherein p-Si can replace as non-crystalline silicon, microcrystal silicon or high temperature polysilicon. Resist coating PR is revolved subsequently above first group of hard mask layer 5/4, and preferably, the top of photoresist material PR can be revolved and is coated with reflection coating provided (TAR, belong to the one of antireflecting coating ARC), and/or above first group of hard mask layer 5/4, first deposit the bottom antireflective coating (BARC does not illustrate) of such as TiN and then revolve resist coating PR.
Secondly, with reference to Fig. 2, needing according to device architectures such as MOSFET and arrange the first mask plate, exposed by photoresist material PR and ARC, develop, a series of lithography step such as heavily fortified point film, define multiple photoresist material figure PRP, each PRP all has the first width. It is noted that clear in order to draw in accompanying drawing, depict only the minority figures such as, two or four, but technical solution of the present invention substantially can be applied to more figure structure, as long as MOSFET element structure needs.
Again, with reference to Fig. 3, taking photoresist material figure PRP as mask, etching the 4th hard mask layer 5, until exposing the 3rd hard mask layer 4, forms the multiple 4th hard mask graph 5P. When the 4th hard mask layer 5 material is the silicon substrate matter such as non-crystalline silicon, microcrystal silicon, low temperature polycrystalline silicon, it is possible to select the alkalescence wet etching liquid such as KOH, TMAH to remove; When the 4th hard mask layer 5 material is silicon oxide, it is possible to adopt the acid wet method corrosive fluid such as HF, BOE to remove; When the 4th hard mask layer 5 material is silicon nitride or during silicon oxynitride, adopts the strong oxidizers such as hot phosphoric acid, the vitriol oil, hydrogen peroxide to carry out wet etching and remove. Or adopt dry etching to remove the 4th hard mask layer 5 of above various material, such as, adopt fluoro-gas (carbon fluorine base gas, SF6��NF3Deng) plasma etching. Burn into about similar layers of material etches, hereinafter repeat no more, but according to material characteristic and etching accuracy requirement, the choose reasonable processing parameter with reference to foregoing description, the temperature of such as wet etching, proportioning, time, the etching gas of dry etching, flow velocity, power, carrier gas, additive, time, temperature etc. Therefore, hereinafter every relating to the technique removing a certain hard mask layer, its concrete grammar all can refer to above description.
Then, with reference to Fig. 4, remove remaining photoresist material figure PRP, the 3rd hard mask layer 4 stays the hard mask pattern 5P of independent the multiple 4th. Minimizing technology such as adopts acetone and aromatic organic solvent, or the inorganic solvent of sulfuric acid/hydrogen peroxide, or plasma etching removal etc. The width of the 4th hard mask pattern 5P is identical with photoresist material figure PRP, all has the first width.
Then, with reference to Fig. 5, on whole device, also namely on the 4th hard mask pattern 5P and the 3rd hard mask layer 4, by common process formation of deposits first spacer material layers 6 such as LPCVD, PECVD, HDPCVD, ALD, cryochemistry thing thermolysis deposition, sputtering, evaporations.The material of the first spacer material layer 6 is all different from the 4th hard mask layer 5 and the 3rd hard mask layer 4, and to obtain good Etch selectivity, such as 6/5/4 is respectively SiNx/p-Si/SiO2, or p-Si/SiNx/SiO2��SiNx/SiO2/p-Si��p-Si/SiO2/SiNxEtc., and wherein p-Si can replace as non-crystalline silicon, microcrystal silicon or high temperature polysilicon.
Hereafter, with reference to Fig. 6, photoetching/etch the first spacer material layer 6, forms multiple first side wall 6S in the 4th hard mask pattern 5P both sides. Wherein, the spacing of the first side wall 6S is first width of the 4th hard mask pattern 5P, and the width of the first side wall 6S self is the 2nd width, and the 2nd width is less than the first width.
Then, with reference to Fig. 7, remove the 4th hard mask pattern 5P, the 3rd hard mask layer 4 stays independent multiple first side wall 6S.
Then, with reference to Fig. 8, taking the first side wall 6S as mask, photoetching/etching the 3rd hard mask layer 4, until exposing the 2nd hard mask layer 3, defines the multiple 3rd hard mask pattern 4P. Wherein, the width of the 3rd hard mask pattern 4P self is the 2nd width of the first side wall 6S, and spacing is first width of the 4th hard mask pattern 5P.
Subsequently, with reference to Fig. 9, remove the first side wall 6S, the 2nd hard mask layer 3 leaves multiple the 3rd independent hard mask pattern 4P. More than by first group of hard mask layer photoetching/etching, the width of the hard mask pattern 4P of first group of lines the 3rd obtained can be less than the precision of original PR photoetching/etching, tentatively improves lines precision therefrom.
Then, with reference to Figure 10, on whole device, also namely on the hard mask pattern 4P of the 2nd hard mask layer 3 and the 3rd, by LPCVD, PECVD, HDPCVD, ALD, cryochemistry thing thermolysis deposition. Common process formation of deposits the 2nd spacer material layers 7 such as sputtering, evaporation. The material of the 2nd spacer material layer 7 is all different from the material of the 3rd hard mask layer 4 and the 2nd hard mask layer 2, to obtain good Etch selectivity. Such as, 7/4/2 it is respectively SiNx/SiO2/ p-Si, or SiNx/p-Si/SiO2��p-Si/SiNx/SiO2��p-Si/SiO2/SiNxEtc., and wherein p-Si can replace as non-crystalline silicon, microcrystal silicon or high temperature polysilicon.
Hereafter, with reference to Figure 11, photoetching/etching the 2nd spacer material layer 7, forms multiple 2nd side wall 7S in the 3rd hard mask pattern 4P both sides. Wherein, the spacing of the first side wall 7S is the 2nd width of the 3rd hard mask pattern 4P, and the width of the 2nd side wall 7S self is the 3rd width, and the 3rd width is less than the 2nd width.
Then, with reference to Figure 12, remove the 3rd hard mask pattern 4P, the 2nd hard mask layer 3 stays independent multiple 2nd side wall 7S.
Then, with reference to Figure 13, taking the 2nd side wall 7S as mask, photoetching/etching the 2nd hard mask layer 3, until exposing the first hard mask layer 2, defines the multiple 2nd hard mask pattern 3P. Wherein, the width of the 2nd hard mask pattern 3P self is the 3rd width of the 2nd side wall 7S, and spacing is the 2nd width of the 3rd hard mask pattern 4P.
Subsequently, with reference to Figure 14, remove the 2nd side wall 7S, the first hard mask layer 2 leaves multiple the 2nd independent hard mask pattern 3P.
Hereafter, with reference to Figure 15, taking the 2nd hard mask pattern 3P as mask, etching the first hard mask layer 2, until exposing substrate 1, forming the multiple first hard mask pattern 2P. Wherein, the first hard mask pattern 2P local width equals the 3rd width of the 2nd hard mask pattern 3P, and spacing equals the 2nd width of the 3rd hard mask pattern 4P.
Then, with reference to Figure 16, remove the 2nd hard mask pattern 3P, leave multiple the first independent hard mask pattern 2P on substrate 1.More than by the 2nd group of hard mask layer photoetching/etching, the width of the hard mask pattern 2P of the 2nd group of lines first obtained is less than the precision of original PR photoetching/etching further, again improves lines precision therefrom.
Then, with reference to Figure 17, taking the first hard mask pattern 2P as mask, etched substrate 1 forms multiple substrate figure 1P, forms the fin sheet of device.
Finally, with reference to Figure 18, remove the first hard mask pattern 2P, leave multiple independent substrate figure 1P. The lines local width of substrate figure 1P is the 3rd width of the first hard mask pattern 2P, the 2nd hard mask pattern 3P, and spacing is the 2nd width of the 3rd hard mask pattern 4P. By Figure 18 it can be seen that the thickness that fin sheet is also substrate figure 1P is far smaller than its length, therefore form the multiple vertical strip thin slice being perpendicular to substrate horizontal plane. The basis that these fin sheets will be formed as the gate stack structure such as gate insulator, grid conducting layer in follow-up MOSFET manufacturing process, so that the fine structure of good control grid. Such as, by the above-mentioned two step side wall techniques of the present invention, it is possible to control make fin thickness also namely the width of substrate figure 1P be less than 15nm, be particularly less than 10nm, thus form nano thread structure.
In sum, with reference to Figure 19, the schema of the method for the present invention at least comprises the following steps:
Substrate is formed the 2nd group of hard mask layer;
2nd group of hard mask layer forms first group of hard mask layer;
Etch first group of hard mask layer, form first group of lines;
Taking first group of lines as mask, etch the 2nd group of hard mask layer, form the 2nd group of lines;
Taking the 2nd group of lines as mask, etched substrate, forms fin sheet.
Especially, although the present invention only show two step side wall techniques, in fact can implement more times side wall formed and remove technique, to utilize in depositing operation for the accurate selection of thickness to make up the precise decreasing of width in photoetching/etching technics, meticulousr nano thread structure thus can be obtained.
In addition, it should be appreciated that although embodiment of the present invention part lists limited several hardmask material, but actual manufacture can also select other different materials, as long as any two layers of adjacent material are different to ensure higher etching selection ratio. In the embodiment of the present invention, preferred p-Si is as the hard mask layer material except silicon nitride, these two kinds of conventional hard mask materials of silicon oxide, just in order to example object, what should know is the material with higher etching selection ratio that can use other, such as, and the thickness of each layer requires and select, 10��100nm according to etching pattern precision.
According to the method, semi-conductor device manufacturing method of the present invention, adopt multiplet structure mask, shelter with twice side wall and etch graphically, thus obtain the Nano-structure being less than photolithography limitation size. Technique is simple, precision height, and compatible high.
Although the present invention being described with reference to one or more exemplary embodiment, those skilled in the art can know, without the need to departing from the scope of the invention, device architecture made various suitable change and equivalents. In addition, can make by disclosed instruction and many may be suitable for the amendment of particular condition or material and do not depart from the scope of the invention. Therefore, the object of the present invention is not to be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments falling in the scope of the invention.
Claims (6)
1. a method, semi-conductor device manufacturing method, comprising:
Forming the 2nd group of hard mask layer on substrate, the 2nd group of hard mask layer comprises the first hard mask layer and the 2nd hard mask layer;
Forming first group of hard mask layer on the 2nd group of hard mask layer, first group of hard mask layer comprises the 3rd hard mask layer and the 4th hard mask layer, and wherein the 4th hard mask layer thickness is more than or equal to the 2nd hard mask layer thickness;
Photoetching/etch first group of hard mask layer, forms first group of lines;
Taking first group of lines as mask, photoetching/etching the 2nd group of hard mask layer, forms the 2nd group of lines, and wherein the 2nd group of line thickness is less than first group of line thickness;
Taking the 2nd group of lines as mask, etched substrate, forms fin sheet,
Wherein, the step forming the 2nd group of lines specifically comprises: form the 2nd side wall first group of lines both sides; Remove first group of lines; Taking the 2nd side wall as mask, etching the 2nd hard mask layer also removes the 2nd side wall, leaves the hard mask pattern of independent the 2nd on the first hard mask layer, form the 2nd group of lines, wherein, the width of the 2nd group of lines equals the width of the 2nd side wall, and is less than the width of first group of lines.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step forming first group of lines specifically comprises:
Photoetching/etching the 4th hard mask layer, forms the 4th hard mask pattern on the 3rd hard mask layer;
The first side wall is formed in the 4th hard mask pattern both sides;
Remove the 4th hard mask pattern;
Taking the first side wall as mask, etching the 3rd hard mask layer also removes the first side wall, leaves the hard mask pattern of independent the 3rd, form first group of lines on the 2nd hard mask layer,
Wherein, the width of first group of lines equals the width of the first side wall, and is less than the width of the 4th hard mask pattern.
3. such as the method, semi-conductor device manufacturing method of claim 1 to 2 arbitrary, wherein, the material of substrate, the first hard mask layer, the 2nd hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, the first side wall and the 2nd side wall is selected according to following principle: any two layers of adjacent material difference.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, the material of substrate, the first hard mask layer, the 2nd hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, the first side wall and the 2nd side wall is selected from following scope: silica-base material, silicon oxide, silicon nitride, silicon oxynitride.
5. method, semi-conductor device manufacturing method as claimed in claim 4, wherein, silica-base material comprises silicon single crystal, non-crystalline silicon, microcrystal silicon, low temperature polycrystalline silicon, high temperature polysilicon.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the forming method of first group of hard mask layer and/or the 2nd group of hard mask layer comprises LPCVD, PECVD, HDPCVD, ALD, cryochemistry thing thermolysis deposition, sputtering, evaporation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210067438.2A CN103311123B (en) | 2012-03-14 | 2012-03-14 | Method, semi-conductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210067438.2A CN103311123B (en) | 2012-03-14 | 2012-03-14 | Method, semi-conductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103311123A CN103311123A (en) | 2013-09-18 |
| CN103311123B true CN103311123B (en) | 2016-06-08 |
Family
ID=49136203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210067438.2A Active CN103311123B (en) | 2012-03-14 | 2012-03-14 | Method, semi-conductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103311123B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157574B (en) * | 2014-07-31 | 2018-06-05 | 上海集成电路研发中心有限公司 | The fin structure line top cutting-off method of Dual graphing fin transistor |
| CN105428317B (en) * | 2014-09-12 | 2018-09-18 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN105470137A (en) * | 2014-09-12 | 2016-04-06 | 中国科学院微电子研究所 | Fin etching method |
| CN104528634B (en) * | 2014-12-16 | 2017-01-18 | 南京工业大学 | Side wall forming and manufacturing method for nanometer structure |
| CN105762186A (en) * | 2014-12-17 | 2016-07-13 | 中国科学院微电子研究所 | Fin field-effect transistor, fin structure and manufacturing method thereof |
| CN105762071B (en) * | 2014-12-17 | 2019-06-21 | 中国科学院微电子研究所 | The manufacturing method of fin formula field effect transistor and its fin |
| CN105097449B (en) * | 2015-06-09 | 2018-07-31 | 华为技术有限公司 | A method of making nano wire |
| CN108807170B (en) * | 2018-06-11 | 2021-10-22 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
| CN112967986B (en) * | 2020-10-19 | 2022-06-21 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
| EP1764827A1 (en) * | 2005-09-16 | 2007-03-21 | Interuniversitair Microelektronica Centrum ( Imec) | Recursive spacer defined patterning |
| KR101057191B1 (en) * | 2008-12-30 | 2011-08-16 | 주식회사 하이닉스반도체 | Method of forming fine pattern of semiconductor device |
| US8222140B2 (en) * | 2009-12-23 | 2012-07-17 | Intel Corporation | Pitch division patterning techniques |
-
2012
- 2012-03-14 CN CN201210067438.2A patent/CN103311123B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103311123A (en) | 2013-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103311123B (en) | Method, semi-conductor device manufacturing method | |
| US10510853B2 (en) | FinFET with two fins on STI | |
| US8053299B2 (en) | Method of fabrication of a FinFET element | |
| CN103915486B (en) | High efficiency finfet diode | |
| US8716156B1 (en) | Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process | |
| US7829466B2 (en) | Methods for fabricating FinFET structures having different channel lengths | |
| US10566330B2 (en) | Dielectric separation of partial GAA FETs | |
| TWI688044B (en) | Semiconductor device, fin field-effect transistor device and method for fabricating the same | |
| US20130082329A1 (en) | Multi-gate field-effect transistors with variable fin heights | |
| JP2010530623A (en) | Fin-type field effect transistor device having self-aligned source / drain regions and method of forming the same | |
| US9202919B1 (en) | FinFETs and techniques for controlling source and drain junction profiles in finFETs | |
| KR20130129867A (en) | Method of forming finfet devices with alternative channel materials | |
| US9620589B2 (en) | Integrated circuits and methods of fabrication thereof | |
| CN109473398B (en) | Semiconductor device and method for manufacturing the same | |
| US9166025B1 (en) | Methods of forming a nanowire device with a gate-all-around-channel configuration and the resulting nanowire device | |
| CN102832135A (en) | Method for preparing FinFET on germanium and III-V semiconductor material substrate | |
| US20230037719A1 (en) | Methods of forming bottom dielectric isolation layers | |
| CN107452680B (en) | Semiconductor device and method for manufacturing the same | |
| US11201246B2 (en) | Field-effect transistor structure and fabrication method | |
| CN107424994A (en) | Ring grid III-V quantum well transistors and germanium nodeless mesh body pipe and its manufacture method | |
| CN104517839A (en) | Fin-shaped field effect transistor structure and preparation method thereof | |
| JP2022552417A (en) | Horizontal gate all-around (hGAA) nanowire and nanoslab transistors | |
| CN106981422B (en) | Vertical TFET and manufacturing method thereof | |
| CN205789953U (en) | A kind of fin formula field effect transistor device test structure | |
| Chen et al. | A Si–based bulk FinFET by novel etching process with mask–less and photoresist–free lithography technique |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |