CN107871666B - Method for manufacturing vertical stacking integrated semiconductor nano-wire and field effect transistor thereof - Google Patents

Method for manufacturing vertical stacking integrated semiconductor nano-wire and field effect transistor thereof Download PDF

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CN107871666B
CN107871666B CN201710872129.5A CN201710872129A CN107871666B CN 107871666 B CN107871666 B CN 107871666B CN 201710872129 A CN201710872129 A CN 201710872129A CN 107871666 B CN107871666 B CN 107871666B
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CN107871666A (en
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李铁
何云乾
王跃林
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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Abstract

The invention provides a method for manufacturing a vertical stacking integrated semiconductor nanowire and a field effect transistor thereof, which comprises the following steps: providing a {100} semiconductor substrate, and preparing a pair of grooves on the substrate; etching the lining bottom materials of the paired grooves by adopting an anisotropic etching method, wherein the side walls of the grooves form a sawtooth-like structure; manufacturing a new groove aligned with the center of the window at the bottom of the groove, and performing anisotropic etching to obtain a new sawtooth-like structure; forming vertically stacked integrated semiconductor nanowires encased in oxidized semiconductor walls on walls between pairs of trenches using high temperature oxidation techniques; and finally, manufacturing a source, a drain and a grid at two ends and the middle of the semiconductor nanowire to form the field effect transistor. The method has simple process, only needs the conventional MEMS process such as the common photoetching technology and the like, has generality in equipment parameter design and low cost, only needs to control the etching time according to the target etching depth, has high controllability and is easy to realize.

Description

Method for manufacturing vertical stacking integrated semiconductor nano-wire and field effect transistor thereof
Technical Field
The invention relates to the field of nano device manufacturing, in particular to a method for manufacturing a vertical stacking integrated semiconductor nanowire and a field effect transistor thereof.
Background
The semiconductor nano-wire is a novel one-dimensional nano-material, and is widely applied to the research of silicon nano-sensors and silicon nano-electronic devices due to the specific nanoscale characteristics of optics, electricity, thermology, mechanics and the like. The preparation of semiconductor nano-wires is divided into two methods of 'bottom-up' and 'top-down', wherein the 'bottom-up' method is that the required nano-materials and structures grow by self-assembly starting from atomic molecules, and the structures, components, sizes, positions and the like of the nano-materials are required to be controlled in the growth process of the materials. The 'top-down' method is that the required nano structure is directly prepared on the bulk material by using the technologies of film deposition, photoetching, etching and the like. The method of 'bottom-up' using self-assembly technology is difficult to control the positioning of semiconductor nano-wire, and the method of 'top-down' using photoetching, masking and etching etc. can realize the accurate positioning of semiconductor nano-wire position, providing reliable method for manufacturing silicon nano-device accurately in large scale.
In the application of the semiconductor nano-wire, the silicon nano-sensor detects the conductivity parameters of the semiconductor nano-wire by utilizing the modulation effect of the measured object on the electron hole concentration of the semiconductor nano-wire so as to quantify the characteristics of the measured object, such as dosage and the like. The silicon nano electronic device utilizes the modulation effect of external potential on the electron hole concentration of a semiconductor nano wire to realize the switching characteristic of a microelectronic device and the like. Regardless of the silicon nano sensor or the silicon nano electronic device, the driving current of the semiconductor nanowire is strongly dependent, and the performance of the device can be improved by increasing the driving current, so that the increase of the driving current of the semiconductor nanowire becomes a hot point of research. Existing technologies are stressed silicon technology, new channel materials and multi-channel integration technology. On one hand, the multi-channel integration technology is the simplest technology with proper cost and good compatibility with a silicon process, on the other hand, the technology is in integral multiple relation to the improvement of the driving current of the device, and the improvement of the driving current and the performance of the nanometer device can be improved by N times by N-number of nanometer line integration, so that the development of the multi-channel integration technology has important value on the improvement of the driving current and the performance of the nanometer device.
Methods of fabricating multi-channel integrated silicon nano-devices include planar multi-nanowire integration methods and vertically stacked nanowire integration methods. The planar multi-nanowire integration method is a method for integrating a plurality of nanowires in a plane into one device in parallel, and the vertically stacked nanowire integration method is a method for manufacturing a plurality of nanowires in a vertical direction of a channel region in a stacked manner and integrating the nanowires into one device. The planar multi-nanowire integration method can increase the surface area of a device, greatly reduces the yield of the device on a single wafer of the device, and the vertically stacked nanowire integration can not increase the surface area of the device, so that the dual effects of keeping the surface area of the device unchanged and increasing the driving current of the device in multiples are realized, and therefore, the development of the vertically stacked nanowire integration has important significance and value for improving the performance of the nano device.
The existing methods for preparing the vertical stacked semiconductor nanowire are two, one is realized by utilizing an epitaxial Si/SiGe/Ge technology and a sacrificial layer technology; the other method is realized by utilizing a BOSCH technology to obtain a sawtooth structure in the deep reaction sample etching (ICP) etching process and then reducing the size of a silicon wall through high-temperature thermal oxidation. The former method uses special epitaxial equipment, requires a multi-material stack, such as a Si/SiGe/Ge/SiGe stack, requires careful consideration of stress distribution and stress matching between films for epitaxial materials, and is costly and complicated to control. The latter method strongly depends on various parameters of deep reactive ion etching (ICP), such as gas pressure, gas flow, plasma power, chassis temperature, passivation and etching time, etc., to form a suitable saw-tooth like structure. The method of making the structure strongly depends on a good fit of these parameters, and the desired structure will not be obtained if there is a mismatch. In the conventional process, the parameters of the equipment are not allowed to be adjusted randomly, so that the method is not conventional parameter setting and has specificity, and the same parameters are not suitable for other ICP equipment due to the difference among the equipment, and the parameters need to be specially and massively adjusted according to the requirements of nanowires with different sizes and densities and different equipment, so that the workload is huge; in addition, expensive electron beam lithography needs to be used, and process control is difficult. The invention provides a new manufacturing method, the process is simple, only conventional MEMS (micro-electromechanical systems) processes such as a common photoetching technology and the like are needed, the equipment parameter design is general, the cost is low, the etching time is controlled only according to the target etching depth, the controllability is high, and the realization is easy.
Disclosure of Invention
The invention aims to provide a method for manufacturing a vertical stack integrated semiconductor nanowire field effect transistor, which aims to solve the problems that the existing process for preparing a vertical stack semiconductor nanowire is complex in control, is controlled by multiple parameters of equipment, needs expensive electron beam lithography, is difficult in process control and the like.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a method for manufacturing a vertically stacked and integrated semiconductor nanowire, which is characterized by comprising the following steps of: s1: providing a {100} semiconductor material substrate, and preparing an array of grooves arranged in pairs on the substrate; the low-index crystal faces on the bottom face of the groove are {100} faces, and the low-index crystal faces on the four side faces are {110} crystal faces; s2: carrying out anisotropic etching on the semiconductor material in the grooves, and symmetrically forming sawtooth-like structures on the side walls of the grooves and the semiconductor material walls between the paired grooves; s3: manufacturing a new groove aligned with the center of a window of the groove at the bottom of the groove; s4: repeating step S2; s5: obtaining a plurality of zigzag-like structures which are vertically stacked and arranged; s6: and for the sawtooth-like structure in the S5, oxidizing for a preset time by adopting a method of reducing the size of the semiconductor by adopting a high-temperature oxidation technology to form a vertically stacked single crystal semiconductor nanowire core wrapped in the oxidized semiconductor wall on the wall between the paired grooves.
The step S1 and the step S4 are both prepared by adopting a photoetching technology, and comprise the following steps: selecting a chemical vapor deposition layer of hard mask on the surface of the substrate, then preparing a uniform photoresist layer on the surface of the hard mask, and defining an array of rectangular windows arranged in pairs on the photoresist layer by the traditional photoetching technology, wherein the edges of the rectangular windows are aligned along a <110> crystal direction; and taking the photoresist layer with the rectangular window array as a mask, and sequentially etching the hard mask in the rectangular window and the substrate with a certain depth by adopting a dry etching technology to form a groove.
The hard mask is silicon oxide or silicon nitride, the deposition of the hard mask adopts a chemical vapor deposition technology, and the dry etching technology comprises reactive ion etching and deep reactive ion etching.
The etchant used in the anisotropic etching of step S2 is KOH or TMAH.
The side surfaces of the sawtooth-like structure described in the step S5 are all surrounded by {111} crystal planes, and the following conditions are satisfied: d ═ W ═ tan (θ), T ═ 0.5W ÷ ρ110And Wsca0.5W ÷ cos (θ), or D < W × tan (θ), T ═ 0.5(W-W1) ÷ ρ110And Wsca0.5(W-W1) ÷ cos (θ), wherein D is a silicon etching depth, W is a gap between grooves arranged in pairs, and W1 is a reserved space between two intersecting lines of the {111} planes; theta is the angle between the {100} and the {111} planes, T is the etching time, rho110Is {110} plane etch rate, WscaThe width of the inclined plane of the sawtooth-like structure.
The sawtooth-like structure described in step S5 has sides consisting of {111} and {110}The crystal face is enclosed to meet the following conditions: d is more than or equal to W tan (theta); t-0.5 (W-W2) ÷ ρ110；Wsca0.5(W-W2) ÷ cos (θ); d is the silicon etching depth, W is the gap of the grooves arranged in pairs, and W2 is the reserved width of the {110} plane; theta is the angle between the {100} and the {111} planes, T is the etching time, rho110Is {110} plane etch rate, WscaThe width of the inclined plane of the sawtooth-like structure.
The gap W of the grooves arranged in pairs is 2-3 mu m, the corrosion time is preferably 9min, 30 s-10 min, and the silicon etching depth D is 2.8-3 mu m.
The substrate is N or P type semiconductor material silicon, germanium and SOI.
The invention also provides a method for manufacturing the vertical stacking integrated semiconductor nanowire field effect transistor, which comprises the following steps: s1: fabricating vertically stacked integrated semiconductor nanowires using the method of claims 1-8; s2: and taking the semiconductor nanowire structure S1 as a channel, manufacturing a source electrode and a drain electrode at two ends of the semiconductor nanowire structure, manufacturing a grid in the middle of the semiconductor nanowire structure, and etching an isolation groove to realize physical isolation of the source electrode and the drain electrode except for channel connection.
The grid electrode can be an omega-shaped grid, a pi-shaped grid, a GAA surrounding grid and a three-dimensional grid, and the material is metal or polycrystalline silicon.
The method for manufacturing the vertical stack integrated semiconductor nanowire field effect transistor has the advantages that the technical process is simple, only standard MEMS (micro-electromechanical systems) processes such as conventional photoetching, dry etching and wet etching processes are utilized, the equipment parameter design is general and standardized, only the etching time needs to be controlled according to the required etching depth, the setting and debugging of special parameters are not needed as the sawtooth structure obtained by utilizing the BOSCH technology is not needed, the controllability is high, and the realization is easy; the required photoetching technology is a common photoetching technology, is not other expensive photoetching technologies with ultra-high precision and ultra-small line width, such as deep ultraviolet photoetching, electron beam photoetching and the like, and has low cost. The field effect transistor manufactured by the method can vertically integrate a plurality of semiconductor nanowires, increases the contact area with the peripheral environment, enhances the response strength, improves the sensitivity, and simultaneously obviously increases the driving current of the device, improves the signal-to-noise ratio and obviously enhances the performance of the device on the premise of keeping the chip area unchanged.
Drawings
Fig. 1 and 2 show a schematic top view and a schematic cross-sectional structure of a single pair of windows of an array of pairs of windows formed on a hard mask by an etching technique according to the present invention.
Fig. 3 is a schematic cross-sectional structure of a trench structure formed on a semiconductor substrate by an etching technique under the window structure of fig. 2.
Fig. 4 is a schematic cross-sectional view of a trench having saw-tooth-like sidewalls formed by anisotropic etching under the trench structure of fig. 3.
Fig. 5 is a schematic cross-sectional view of the trench structure of fig. 3 formed on a semiconductor substrate by an etching technique under the trench structure of fig. 4.
FIG. 6 is a schematic cross-sectional view of a trench formed by anisotropic etching to form the sidewall of the saw-tooth like structure of FIG. 4 under the trench structure of FIG. 5.
Fig. 7 is a schematic cross-sectional view of a nanowire stack structure having an inverted triangular (top) + diamond (middle) + triangular (bottom) profile formed by a high temperature thermal oxidation technique under the trench structure of fig. 6.
Fig. 8 shows a top view of a semiconductor nanowire vertical stack integrated field effect transistor structure formed by depositing and etching source and drain gate electrodes under the structure shown in fig. 7.
Fig. 9 shows a cross-sectional view of the channel a-a' position of the semiconductor nanowire vertical stack integrated field effect transistor as shown in fig. 8.
1/2/3-top silicon/middle oxide layer/bottom silicon of an SOI substrate, 4-hard mask, 5-photoresist layer, 6-rectangular window, 7-first etching groove, 8-first etching groove side wall, 9-second etching rectangular window, 10-second etching groove, 11-second etching groove side wall, 12/13/14-inverted triangle/diamond/regular triangle section semiconductor nanowire, 15-oxide layer, 16-source electrode, 17-drain electrode, 18-omega type gate and 21-source drain electrode physical isolation groove.
Detailed Description
The following description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will provide a better understanding of the function and features of the invention.
The invention provides a method for manufacturing a vertically stacked and integrated semiconductor nanowire, which comprises the following steps:
s1: there is provided a 100 SOI substrate on which an array of recesses 7 arranged in pairs is prepared, wherein 100, 110, 111 represent indices of three crystal plane groups of semiconductor material, each group having several equivalent crystal planes, and 100 refers to the collective term for the group of several equivalent crystal plane substrates. The method specifically comprises the following steps:
s11: a100 type SOI silicon wafer is provided. The specific structure of the SOI Silicon wafer (Silicon-On-Insulator, i.e., Silicon On an insulating substrate) is shown in fig. 3, and includes a bottom layer Silicon 1, a middle oxide layer 2, and a top layer Silicon 3 from bottom to top; alternatively, the substrate may be selected to be silicon or germanium, which is an N or P type semiconductor material.
S12: a silicon nitride hard mask 4 is selectively deposited by chemical vapor deposition on the surface of the top silicon 1 of the SOI material in step S11, and then a uniform photoresist layer 5 is prepared on the surface of the silicon nitride hard mask 4, and an array of rectangular windows 6 arranged in pairs is defined on the photoresist layer 5 by conventional photolithography. Wherein the photoresist layer is shaped as shown in fig. 1, four edges of the rectangular window 6 are aligned along a <110> crystal direction, wherein <110> represents a crystal orientation index; the dimensions of the rectangular window 6 are: the length is 5-100 mu m, and the gradient change is 5 mu m; the width is 5-100 μm, and the gradient is 5 μm. The gap between the two rectangular windows in pairs is 2-3 μm.
S13: as shown in fig. 3, the photoresist layer 5 with the rectangular window array described in S12 is used as a mask, and the silicon nitride hard mask 4 (using a reactive ion etching technique) and the top silicon (using a deep reactive ion etching technique) with a certain depth in the rectangular window 6 are sequentially etched by using a dry etching technique to form the grooves 7 arranged in pairs, so that the gap between the grooves 7 arranged in pairs is 2 μm to 3 μm, the low-index crystal plane of the bottom surface is a {100} plane, and the low-index crystal planes of the four side surfaces are {110} crystal planes. Preferably, the silicon etching depth D is 2.8 μm to 3 μm.
S2: by anisotropically etching the silicon in the grooves 7 through the grooves 7 described in S13, saw-tooth like structures 8 are formed symmetrically on the side walls of the grooves 7 and the silicon wall between the pair of grooves 7. As shown in fig. 4, according to the crystal plane distribution of the rectangular window 6 aligned with the <110> crystal direction and the five surfaces of the groove 7, in the wet anisotropic etching process of the groove 7, the five surfaces of the groove 7 are all etched, since the four side surfaces of the groove 7 are all {110} surfaces, the etching respectively stops at two inclined {111} surfaces with an included angle of 54.74 degrees with the {100} surfaces of the surfaces, a V-shaped groove with a bevel width of 1.5-2 μm is formed, the {100} surfaces at the bottom of the groove 6 are also etched, and a fully saturated state forms an inverted pyramid or inverted V-shaped structure from the four inclined {111} surfaces. However, since the etch rate of the 111 planes is much lower than that of the 100 and 110 planes, the wet etch process only requires four sidewalls to reach a saturated etch state, so as to form a saw-tooth-like structure symmetrically on the silicon wall between the pair of trenches. The anisotropic etching uses KOH, TMAH, and other etching agents, in the embodiment shown in fig. 4, KOH is preferable, and the etching time is preferably 9min30 s-10 min.
S3: making a new groove 10 at the bottom of said groove 6, aligned with the centre of its window, comprising:
s31: a silicon nitride mask is prepared in the groove 6, then a uniform photoresist layer is prepared on the surface of the silicon nitride mask, a new array of rectangular windows 9 at the positions shown in fig. 4 is exposed on the photoresist layer by the conventional photolithography technique, the size of the rectangular windows 9 is smaller than the original rectangular windows 9 and is aligned with the center of the original rectangular windows 9, the windows are positioned at the bottom of the groove 6, and the edges of the windows are aligned along the <110> crystal direction. Because the new rectangular window 9 is to be exposed in the groove for lithography, the rectangular window must be reduced to expose the groove 6 without damaging the existing sidewall structure of the groove 6 in consideration of the error of the lithography machine and the diffraction and scattering of light during exposure.
S32: as shown in fig. 5, using the photoresist layer 5 with the new array of rectangular windows 9 as a mask in S31, sequentially using the reactive ion etching technique to first etch away the exposed dielectric mask layer in the rectangular windows and using deep reactive ions to etch the silicon substrate with a predetermined depth, so as to form new grooves 10 arranged in pairs. Thus, the low-index crystal plane of the bottom surface of the recess 10 is a {100} plane, and the low-index crystal planes of the four side surfaces are {110} planes. Preferably, the silicon etching depth D is 2.8 μm to 3 μm.
S4: as shown in fig. 6, the step S2 is repeated, and the silicon in the grooves 10 is anisotropically etched through the grooves 10 described in S3, to form saw-tooth like structures 11 symmetrically on the side walls of the grooves 10 and the silicon wall between the pair of grooves 10.
S5: the above steps S3 and S4 are repeated until the material of the {100} plane at the bottom of the groove 6 is silicon oxide, and by iterating the steps S3 and S4, a plurality of symmetrical saw-tooth-like structures arranged in a vertical stack can be formed on the silicon wall between the paired grooves.
The size of the sawtooth-like structure is controlled by the gap of the grooves arranged in pairs, the silicon etching depth D and the wet etching time T. The sawtooth-like structure is formed by the crystal faces of silicon, and can be divided into two cases, according to the arrangement of the gap of the grooves arranged in pairs, the etching depth D of the silicon and the wet etching time T, the first kind is that the side faces are all formed by the {111} crystal faces, and the second kind is that the side faces are formed by the {111} crystal faces and the {110} crystal faces.
To obtain a saw-tooth like structure with sides all surrounded by the 111 crystal planes, the following conditions must be satisfied:
corrosion self-stop method 1: d ═ W × tan (θ); T0.5W ÷ ρ110；Wsca＝0.5W÷cos(θ)。
Corrosion self-stop method 2: d < W tan (theta); t-0.5 (W-W1) ÷ ρ110；Wsca＝0.5(W-W1)÷cos(θ)。
To obtain a sawtooth-like structure with sides surrounded by {111} and {110} crystal planes, the following conditions must be satisfied:
the time control method comprises the following steps: d is more than or equal to W tan (theta); t-0.5 (W-W2) ÷ ρ110；Wsca＝0.5(W-W2)÷cos(θ)。
Wherein D is the silicon etching depthW is the gap of the grooves arranged in pairs, W1 is the reserved space of the two intersecting lines of the {111} surfaces, and W2 is the reserved width of the {110} surfaces; theta is the angle between the {100} and the {111} planes, T is the etching time, rho110Is {110) plane etch rate, WscaThe width of the inclined plane of the sawtooth-like structure. All three methods firstly determine D and T to have WscaA saw-tooth like structure of size.
As described above, in the present embodiment, the gap W between the grooves arranged in pairs is 2 μm to 3 μm, the etching time is preferably 9min30s to 10min, and the silicon etching depth D is 2.8 μm to 3 μm, so that the side surfaces of the resulting saw-tooth like structure are entirely surrounded by the {111} crystal plane. Under the condition, the cross-sectional profiles of the plurality of zigzag-like structures arranged in a vertical stack comprise inverted triangle, rhombus and regular triangle profiles, the angles of the inverted triangle and the regular triangle are 54.7 °, 70.6 °, and the angles of the rhombus are 109.4 °, 70.6 ° and 70.6 °.
And S6, for the sawtooth-shaped structure in S5, oxidizing for a preset time by adopting a method of reducing the size of silicon by adopting a high-temperature oxidation technology, and forming vertically stacked monocrystalline silicon nanowire cores wrapped in the walls of silicon oxide on the walls between the paired grooves. As shown in fig. 7, which is an example of three nanowires, the top of the nanowire 12 with an inverted triangle-shaped cross section, the middle of the nanowire 13 with a diamond-shaped cross section, and the bottom of the nanowire 14 with a regular triangle-shaped cross section are all wrapped in an oxide layer 15 to form a vertically stacked silicon nanowire structure, which can be used as a channel. Preferably, the high temperature oxidation technique in step S6 is to perform high temperature wet oxidation to a certain thickness, remove the oxide layer by HF dry method, and then perform high temperature thermal oxidation.
The present invention also provides a method of fabricating a vertical stack integrated semiconductor nanowire field effect transistor, the method fabricating a vertical stack integrated semiconductor nanowire according to the steps S1 to S6 described above, and further comprising the steps of:
s7: as shown in fig. 8, with the silicon nanowire structure described in S6 as a channel, exposing the positions of the source electrode 16 and the drain electrode 17 and the positions of the source-drain physical isolation trenches 21 at the two ends of the silicon nanowire structure by using a conventional photolithography technique, and removing the mask layer at the positions of the source electrode 16 and the drain electrode 17, the mask layer of the isolation trenches 21, and the top silicon by dry etching; and respectively forming a source electrode 16 and a drain electrode 17 at two ends of the channel by adopting a metal deposition technology, and forming an omega-shaped gate 18 in the middle of the silicon nanowire structure to form the vertically-stacked integrated silicon nanowire field effect transistor. Therefore, the source electrode 16 and the drain electrode 17 of the vertically stacked integrated silicon nanowire field effect transistor are only connected through a channel, the other positions are etched with an isolation groove through an etching technology to realize physical isolation, and the bottoms are isolated through an oxide layer to ensure that current can only flow through the channel. The grid 18 can be an omega-shaped grid, a pi-shaped grid, a GAA surrounding grid or a three-dimensional grid, and the material is metal or polysilicon. As shown in fig. 9, the gate electrode 18 is preferably an omega-shaped gate electrode.
The above embodiments are merely preferred embodiments of the present invention, which are not intended to limit the scope of the present invention, and various changes may be made in the above embodiments of the present invention. All simple and equivalent changes and modifications made according to the claims and the content of the specification of the present application fall within the scope of the claims of the present patent application. The invention has not been described in detail in order to avoid obscuring the invention.

Claims (8)

1. A method of fabricating a vertically stacked integrated semiconductor nanowire, comprising:
s1: providing a {100} semiconductor material substrate, and preparing an array of grooves arranged in pairs on the substrate; the low-index crystal faces on the bottom face of the groove are {100} faces, and the low-index crystal faces on the four side faces are {110} crystal faces;
s2: carrying out anisotropic etching on the semiconductor material in the grooves, and symmetrically forming sawtooth-like structures on the side walls of the grooves and the semiconductor material walls between the paired grooves;
s3: manufacturing a new groove aligned with the center of the original rectangular window at the bottom of the groove;
s4: repeating step S2;
s5: obtaining a plurality of zigzag-like structures which are vertically stacked and arranged;
s6: forming vertically stacked single crystal semiconductor nanowires wrapped in the oxidized semiconductor material walls on the walls between the pair of trenches by using a high temperature oxidation technique for the zigzag structure described in S5;
the S3 includes:
s31: preparing a layer of silicon nitride mask in the groove, then preparing a uniform photoresist layer on the surface of the silicon nitride mask, and exposing an array of new rectangular windows on the photoresist layer by using a conventional photoetching technology, wherein the size of the new rectangular windows is smaller than the original rectangular windows of the groove and is aligned with the center of the original rectangular windows, the new rectangular windows are positioned at the bottom of the groove, and the edges of the new rectangular windows are aligned along a <110> crystal direction;
s32: and taking the photoresist layer with the new rectangular window array as a photoresist layer mask, sequentially adopting a reactive ion etching technology to firstly etch the silicon nitride mask exposed in the rectangular window and adopting deep reactive ions to etch the semiconductor material substrate with a preset depth to form new grooves arranged in pairs.
2. The method of fabricating vertically stacked integrated semiconductor nanowires of claim 1, wherein the recess preparation of S1 employs a photolithography technique comprising:
selecting a chemical vapor deposition layer of hard mask on the surface of the substrate, then preparing a uniform photoresist layer on the surface of the hard mask, and defining an array of rectangular windows arranged in pairs on the photoresist layer by the traditional photoetching technology, wherein the edges of the rectangular windows are aligned along a <110> crystal direction;
and taking the photoresist layer with the rectangular window array as a photoresist layer mask, and sequentially etching the hard mask in the rectangular window and the substrate with a certain depth by adopting a dry etching technology to form a groove.
3. The method of claim 2, wherein the hard mask is silicon oxide or silicon nitride, and wherein the hard mask is deposited using a chemical vapor deposition technique, and wherein the dry etching technique comprises reactive ion etching and deep reactive ion etching.
4. The method of fabricating vertically stacked integrated semiconductor nanowires of claim 1, wherein the anisotropic etching of S2 uses KOH or TMAH as an etchant.
5. The method of claim 1, wherein the gap W between the pair of aligned grooves is 2 μm to 3 μm, the etching time is 9min30s to 10min, and the etching depth D of the semiconductor material substrate is 2.8 μm to 3 μm.
6. The method of fabricating vertically stacked integrated semiconductor nanowires of claim 1, wherein the substrate is a semiconductor material of N or P type silicon, germanium, SOI.
7. A method of fabricating a vertically stacked integrated semiconductor nanowire field effect transistor, comprising:
s1: fabricating vertically stacked integrated semiconductor nanowires using the method of any of claims 1-6;
s2: and taking the semiconductor nanowire as a channel, manufacturing a source electrode and a drain electrode at two ends of the semiconductor nanowire, manufacturing a grid in the middle of the semiconductor nanowire, and etching an isolation groove to realize physical isolation of the source electrode and the drain electrode except channel connection.
8. The method of claim 7, wherein the gate is an omega gate, a pi gate, a GAA wrap-around gate, or a three-dimensional gate, and is made of metal or polysilicon.
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