CN206282823U - A kind of wafer level prepares silicon nanowire array FET - Google Patents
A kind of wafer level prepares silicon nanowire array FET Download PDFInfo
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- CN206282823U CN206282823U CN201621370548.6U CN201621370548U CN206282823U CN 206282823 U CN206282823 U CN 206282823U CN 201621370548 U CN201621370548 U CN 201621370548U CN 206282823 U CN206282823 U CN 206282823U
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Abstract
The utility model provides a kind of wafer level and prepares silicon nanowire array FET, including：One (111) type soi wafer, (111) the type soi wafer includes bottom silicon, oxide layer and top layer silicon；Positioned at the silicon nitride mask layer of the top layer silicon upper surface and oxide layer, wherein, the silicon nitride mask layer surface is formed with the hexagon etching tank array for exposing the oxide layer；Positioned at the silicon nanowire array of silicon nitride mask layer lower surface；Positioned at silicon nitride mask layer upper surface and grid corresponding with the silicon nanowire array position；And the source electrode positioned at silicon nitride mask layer upper surface and drain electrode, wherein, the isolation channel of at least one exposure oxide layer is provided between the source electrode and drain electrode.The wafer level provided by the utility model prepares silicon nanowire array FET, and controllability high and uniformity high cannot be realized when solving the problems, such as to prepare silicon nanowire array based on silicon chip in the prior art.
Description
Technical field
The utility model is related to the preparation field of nano material, and more particularly to a kind of wafer level prepares silicon nanowire array
FET.
Background technology
Nanometer technology is to have merged multi-disciplinary emerging high and new technology perhaps, and wherein nano material is extremely important nanometer technology
Research direction.In recent years, the research of nanometer technology and the exploitation of new nano material all achieves significant progress, and in life
The industries such as thing, medical treatment, environment are applied.When the characteristic size of material is reduced to nanoscale, related mechanics, calorifics,
Optically and electrically etc. performance can occur significant change, occur in that skin effect, small-size effect and macro quanta tunnel effect etc.
Novel physical phenomenon.
Continuous improvement due to sensor field to sensitivity requirement, people turn one's attention to field of nanometer technology one after another,
Silicon nanowires is used as a kind of new one-dimensional nano material, and with performances such as excellent power, heat, light, electricity, its specific surface area is big, extraneous
Environment can cause material nature that very big change occurs, so the material has great potentiality lifting sensor sensitive
Degree, has broad application prospects.
FET based on silicon nanowires can retain the excellent properties of silicon nanowires, while can also be by controlling peripheral hardware
Circuit is operated in the operating point of stabilization by device, obtains more accurately feeding back, so the FET based on silicon nanowires exists
Sensor field has huge application advantage.
But prior art is using common (111) type silicon chip, because different zones dry etching speed is different on silicon chip, institute
So that the depth of different zones silicon groove can be caused different, as shown in Figure 1 to Figure 3, wherein, Fig. 1 is in the prior art by dry method quarter
Erosion forms five structural representations of different depth silicon groove, and Fig. 2 is to form four not after wet etching is carried out to silicon groove described in Fig. 1
The structural representation of stack pile silicon wall, Fig. 3 is that silicon wall described in Fig. 2 is aoxidized, and forms the structural representation of silicon nanowires
Figure.As shown in Figure 1 to Figure 3, see from left to right, because first silicon wall is too thick, silicon wall is remained as after causing oxidation；And by
It is thicker in second silicon wall, cause being relatively large in diameter for the silicon nanowires 3 obtained after oxidation；And after being aoxidized to the 3rd silicon wall
Obtain normal silicon nanowires 3；Because the 5th silicon groove is too deep, there is not silicon wall after causing wet etching.It can be seen that, based on general
When logical silicon chip 1 prepares silicon nanowire array, because the etch rate for being dry-etched in diverse location on silicon chip is different so that etching
Silicon groove depth it is different, cause the thickness of silicon thin-walled different, ultimately result in the size of each silicon nanowires in silicon nanowire array not
Together.
In consideration of it, be necessary to provide a kind of wafer level and preparing silicon nanowire array FET and being used to solve the above problems.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of wafer level and prepare silicon to receive
Nanowire arrays FET, controllability high cannot be realized during for solving and prepare silicon nanowire array based on silicon chip in the prior art
And the problem of uniformity high.
In order to achieve the above objects and other related objects, the utility model provides a kind of silicon nanowire array FET,
The silicon nanowire array FET includes：
One (111) type soi wafer, (111) the type soi wafer includes bottom silicon, oxide layer and top layer silicon；
Positioned at the silicon nitride mask layer of the top layer silicon upper surface and oxide layer, wherein, the silicon nitride mask layer
Surface is formed with the hexagon etching tank array for exposing the oxide layer；
Positioned at the silicon nanowire array of silicon nitride mask layer lower surface；
Positioned at silicon nitride mask layer upper surface and grid corresponding with the silicon nanowire array position；And
Source electrode and drain electrode positioned at silicon nitride mask layer upper surface, wherein, it is provided between the source electrode and drain electrode
The isolation channel of at least one exposure oxide layer.
Preferably, the thickness of the top layer silicon is less than or equal to 30um.
Preferably, the width of any silicon nanowires is 70~110nm in the silicon nanowire array.
Preferably, the silicon nanowire array is interdigital structure, and the grid is interdigital structure.
Preferably, 2 isolation channels are provided between the source electrode and drain electrode.
Preferably, the grid is the one kind in gold, copper, aluminium or polysilicon.
As described above, a kind of wafer level of the present utility model prepares silicon nanowire array FET, with following beneficial
Effect：
1. the utility model is provided with the soi wafer of oxide layer due to use centre, when carrying out dry etching to top layer silicon, by
In the stop of oxide layer, the depth of the groove array is all the thickness of top layer silicon, and the etchant solution corrosion in wet etching
(111) speed of crystal orientation is very low, is capable of the thickness of precise control silicon thin-walled, and then cause the silicon nanometer prepared by the utility model
Line has controllability high and uniformity high.
2. the utility model sets grid by every silicon nanowires, grid is covered all of silicon nanowires,
And be effectively physically separated source electrode and drain electrode by isolation channel, it is ensured that the device performance of FET.
3. silicon nanowires described in the utility model due to its entirety be attached to silicon nitride mask layer on, silicon can be prevented effectively from and received
Rice noodles are broken, high yield rate.
Brief description of the drawings
Fig. 1 is shown as forming five structural representations of different depth silicon groove by dry etching in the prior art.
Fig. 2 is shown as carrying out different depth silicon groove described in Fig. 1 after wet etching being formed four different-thickness silicon walls
Structural representation.
Fig. 3 is shown as aoxidizing silicon wall described in Fig. 2, forms the structural representation of silicon nanowires.
Fig. 4~Figure 12 b are shown as the structural representation of the preparation method of the utility model silicon nanowire array FET,
Wherein, Fig. 6 b are sectional views of Fig. 6 a along AA ' directions, and Fig. 7 b are sectional views of Fig. 7 a along BB ' directions, and Fig. 8 b are Fig. 8 a along CC '
The sectional view in direction, Fig. 9 b are sectional views of Fig. 9 a along DD ' directions, and Figure 12 b are sectional views of Figure 12 a along EE ' directions.
Figure 13 is shown as the electron microscope of silicon nanowire array FET described in the utility model.
Figure 14 is illustrated by silicon nanowires enlarged drawing prepared by preparation method described in the utility model.
Figure 15 is illustrated by the scanning of silicon nanowire array FET prepared by preparation method described in the utility model
Curve.
Figure 16 a and Figure 16 b are shown as representing the schematic diagram of each silicon nanowires width consistency situation in silicon nanowire array,
Wherein, Figure 16 b are the enlarged drawing of region e in Figure 16 a.
Component label instructions
S1~S8 steps
1 silicon chip
2 silicon nitride masks layer
3 silicon nanowires
101 bottom silicon
102 oxide layers
103 top layer silicons
4 rectangular window arrays
5 groove arrays
6 hexagon etching tank arrays
7 silicon thin-walled arrays
8 silicon nanowire arrays
9 grids
10 source electrodes
11 drain electrodes
12 isolation channels
A~l regions a~region l
Specific embodiment
Implementation method of the present utility model is illustrated below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages of the present utility model and effect easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Refer to Fig. 4 to Figure 16.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, when only display is with relevant component in the utility model rather than according to actual implementation in schema then
Component count, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random changing during its actual implementation
Become, and its assembly layout kenel be likely to it is increasingly complex.
Embodiment one
The present embodiment provides a kind of method that wafer level prepares silicon nanowire array FET, the preparation method bag
Include：
S1：One (111) type soi wafer is provided, (111) the type soi wafer includes bottom silicon 101, oxide layer 102 and top
Layer silicon 103；
S2：Silicon nitride mask layer 2 is formed on the surface of the top layer silicon 103, and is covered in the silicon nitride by photoetching process
Inclined rectangular window array 4 is formed in film layer 2；
S3：Dry etching is carried out by 4 pairs of top layer silicons 103 of the rectangular window array, the oxide layer is exposed
102, form groove array 5；
S4：Anisotropic etch is carried out by 5 pairs of top layer silicons 103 of the groove array, hexagon etching tank is formed
The silicon thin-walled of predetermined width is formed between array 6, and two neighboring hexagon etching tank；
S5：Based on being aoxidized to (111) the type soi wafer from limitation thermal oxidation technology, on the top of silicon thin-walled array 7
Portion forms silicon nanowire array 8；
S6：The silicon nitride mask layer 2 of every using in the silicon nanowire array 8 surface of silicon nanowires as gate dielectric layer,
Grid 9 is made on the gate dielectric layer surface；
S7：First, second window is formed in the silicon nitride mask layer 2 at the two ends of the silicon nanowire array 8, is then distinguished
In first, second window make source electrode 10 and drain electrode 11, and the source electrode 10 and drain electrode 11 between be provided with least one every
From raceway groove 12, wherein, the isolation channel 12 exposes the oxide layer 102；
S8：The oxidized silicon thin-walled array 7 of removal, discharges the silicon nanowire array 8.
Detailed is made to the preparation method of silicon nanowire array FET described in the present embodiment with reference to specific accompanying drawing
Introduce.
As shown in Figure 4, there is provided one (111) type soi wafer, (111) the type soi wafer includes bottom silicon 101, oxide layer
102 and top layer silicon 103.Wherein, the thickness of the top layer silicon 103 is less than or equal to 30um, so that silicon nanowires diameter is consistent
Property is more preferable.Preferably, in the present embodiment, the thickness of the top layer silicon 103 is 30um；Certainly, in other embodiments, it is described
The thickness of top layer silicon 103 can also be 5um, 8um, 10um, 13um, 15um, 18um, 20um, 23um, 25um or 28um etc..
It should be noted that soi wafer includes bottom silicon 101, oxide layer 102 and top layer silicon 103 successively from top to bottom, when
When subsequently being performed etching to soi wafer, due to the stop of intermediate oxide layer 102 so that often place's etching all directly arrives oxide layer
102, i.e., the depth for often locating etching is all identical, is all the thickness of top layer silicon 103, thereby ensures that the silicon nanowires battle array being subsequently formed
The uniformity of every silicon nanowires shape, width etc. in row, and because the parameters such as every the shape of silicon nanowires, width are equal
One, therefore silicon nanowires can be made array structure, finally realize the preparation of silicon nanowire array FET.
It should be noted that (111) type soi wafer is big due to surface density, its interplanar distance is also big, therefore its interplanar atom
Attraction is just small, and when subsequently carrying out anisotropic etch, the speed for corroding corrosion (111) self-stopping technology face is very low, such energy
The thickness of silicon thin-walled is enough accurately controlled, to realize the high controllable of any silicon nanowires shape, width etc. in silicon nanowire array
Property and uniformity high.
As shown in Fig. 5 to Fig. 6 b, silicon nitride mask layer 2 is formed on the surface of the top layer silicon 103, and exist by photoetching process
Inclined rectangular window array 4 is formed in the silicon nitride mask layer 2.
Specifically, forming the fine and close nitridation of the low stress in the surface of the top layer silicon 103 using chemical vapour deposition technique
Silicon thin film.
Specifically, first then forming graph window in the photoresist in silicon nitride mask layer 2 surfaces coating photoresist
Afterwards, the graph window is transferred on the silicon nitride mask layer 2 using reactive ion etching method RIE.
It should be noted that the length of any rectangular window and all same wide in the rectangular window array, and according to follow-up
The thickness of silicon thin-walled array 7 defines its length and width and spacing.
As illustrated in figs. 7 a and 7b, dry etching is carried out by 4 pairs of top layer silicons 103 of the rectangular window array, is exposed
Go out the oxide layer 102, form groove array 5.
Specifically, the top layer silicon 103 is performed etching using reactive ion etching method RIE, until exposing the oxygen
Change layer 102, form groove array 5, wherein, the depth of the further groove of the groove array 5 and the thickness phase of the top layer silicon 103
Deng being 30um.
As shown in figs. 8 a and 8b, anisotropic etch is carried out by 5 pairs of top layer silicons 103 of the groove array, is formed
The silicon thin-walled of predetermined width is formed between hexagon etching tank array 6, and two neighboring hexagon etching tank.
Specifically, carrying out anisotropic etch to the top layer silicon 103 using KOH solution, hexagon etching tank battle array is formed
Row 6, wherein, each face of any hexagon etching tank belongs to (111) family of crystal planes in the hexagon etching tank array.
Specifically, the width of silicon thin-walled is 320~380nm.Preferably, in the present embodiment, the width of the silicon thin-walled
It is 350nm；Certainly, in other embodiments, the width of the silicon thin-walled can also be 320nm, 325nm, 330nm, 335nm,
340nm, 345nm, 355nm, 360nm, 365nm, 370nm, 375nm, or 380nm etc..
Specifically, the silicon thin-walled is 70.5 ° with the angle of the oxide layer.
As illustrated in figures 9 a and 9b, based on being aoxidized to (111) the type soi wafer from limitation thermal oxidation technology, in silicon
Silicon nanowire array 8 is formed on the top of thin-walled array 7, wherein, the silicon nanowire array is interdigital structure.
It should be noted that due in silicon nanowire array 8 any silicon nanowires be integrally attached to silicon nitride mask layer on, energy
Enough it is prevented effectively from silicon nanowires fracture.
It should be noted that being set to interdigital structure by by the silicon nanowire array 8, silicon nanowires is effectively increased
Density, and then improve the sensitivity of device.
As shown in Figure 10, using the silicon nitride mask layer 2 of every surface of silicon nanowires in the silicon nanowire array 8 as grid
Dielectric layer, grid 9 is made on the gate dielectric layer surface, wherein, the grid is formed as interdigital structure.
It should be noted that all of silicon nanowires is covered by making grid 9 in every surface of silicon nanowires, to realize
Protection to silicon nanowires, it is to avoid silicon nanowires is broken.
Specifically, the material of the grid can be the metals such as gold, copper, aluminium, it would however also be possible to employ polycrystalline silicon material.
As shown in figure 11, first, second window is formed in the silicon nitride mask layer 2 at the two ends of the silicon nanowire array 8,
Then respectively in first, second window make source electrode 10 and drain electrode 11, and the source electrode 10 and drain electrode 11 between be provided with to
A few isolation channel 12, wherein, the isolation channel 12 exposes the oxide layer 102.
It should be noted that the source electrode 10 and drain electrode 11 are carried out into physical isolation by the isolation channel 12, it is to avoid
Interference between the source electrode 10 and drain electrode 11, to ensure that only having silicon nanowire array 8 connects the source electrode 10 and drain electrode 11,
And then improve the performance of device.
As shown in figures 12 a and 12b, oxidized silicon thin-walled array 7 is removed, the silicon nanowire array 8 is discharged.
Embodiment two
As shown in figures 12 a and 12b, the present embodiment provides a kind of silicon nanowire array FET, the silicon nanowires battle array
Row FET includes：
One (111) type soi wafer, (111) the type soi wafer includes bottom silicon 101, oxide layer 102 and top layer silicon
103；
Positioned at the upper surface of the top layer silicon 103 and the silicon nitride mask layer 2 of the top of oxide layer 102, wherein, the silicon nitride
The surface of mask layer 2 is formed with the hexagon etching tank array 6 for exposing the oxide layer 102；
Positioned at the silicon nanowire array 8 of the silicon nitride mask 2 lower surface of layer；
Positioned at the silicon nitride mask 2 upper surface of layer and grid 9 corresponding with the position of the silicon nanowire array 8；And
Positioned at the silicon nitride mask layer 2 upper surface source electrode 10 and drain electrode 11, wherein, the source electrode 10 and drain electrode 11 it
Between be provided with the isolation channel 12 of at least one exposure oxide layer 102.
Specifically, the thickness of the top layer silicon 103 is less than or equal to 30um.
Preferably, in the present embodiment, the thickness of the top layer silicon 103 is 30um；Certainly, in other embodiments, institute
The thickness for stating top layer silicon 103 can also be for 5um, 8um, 10um, 13um, 15um, 18um, 20um, 23um, 25um or 28um etc..
It should be noted that when the thickness of the top layer silicon 103 is less than or equal to 30um, the one of the silicon nanowires diameter
Cause property is more preferable.
Specifically, the silicon nanowire array 8 is interdigital structure, and the grid 9 is again formed as interdigital structure.
It should be noted that being set to interdigital structure by by the silicon nanowire array 8, silicon nanowires is effectively increased
Density, and then improve the sensitivity of device.And, integrally it is attached on silicon nitride mask layer by by silicon nanowire array,
And grid is covered thereon, to realize the protection to silicon nanowire array, the fracture of silicon nanowires can be prevented effectively from.
Specifically, the grid is the one kind in gold, copper, aluminium or polysilicon.
Specifically, being provided with 2 isolation channels 12 between the source electrode 10 and drain electrode 11.
It should be noted that the source electrode 10 and drain electrode 11 are carried out into physical isolation by the isolation channel 12, it is to avoid
Interference between the source electrode 10 and drain electrode 11, to ensure that only having silicon nanowire array 8 connects the source electrode 10 and drain electrode 11,
And then improve the performance of device.
Silicon nanowire array FET is prepared by preparation method described in embodiment one, its electron microscope is as shown in figure 13,
The enlarged drawing of silicon nanowires is as shown in figure 14.Wherein, the molded breadth of each silicon nanowires is 90nm in the silicon nanowire array,
The FET is tested, test result as shown in Figure 15 and Figure 16 is obtained.
As shown in figure 15, Figure 15 is the silicon nanowire array FET prepared by preparation method described in the utility model
Scanning curve, it can be seen from fig. 15 that the modulation of the grid of silicon nanowire array FET prepared by the utility model
Substantially, device performance is excellent for effect.
As shown in fig 16 a and fig 16b, Figure 16 a and Figure 16 b represent each silicon nanowires width consistency in silicon nanowire array
The schematic diagram of situation, wherein, Figure 16 b are the enlarged drawing of region e in Figure 16 a.Survey to each region silicon nanowires width in Figure 16 a
Amount result is as follows：The width of silicon nanowires is 110nm in a of region, and the width of silicon nanowires is 106nm in the b of region, in the c of region
The width of silicon nanowires is 96nm, and the width of silicon nanowires is 79.4nm in the d of region, and the width of silicon nanowires is in the e of region
107nm, the width of silicon nanowires is 89.3nm in the f of region, and the width of silicon nanowires is 79.4nm in the g of region, and silicon is received in the h of region
The width of rice noodles is 75nm, and the width of silicon nanowires is 83.3nm in the i of region, and the width of silicon nanowires is 103nm in the j of region,
The width of silicon nanowires is 102nm in the k of region, and the width of silicon nanowires is 107nm in the l of region；It can be seen that, by the utility model
The width distribution of silicon nanowires prepared by the preparation method is achieved in silicon nanowire array between 70~110nm
The precision controlling of each silicon nanowires width is within ± 20nm.
Preparation method described in the utility model realizes wafer level and is prepared on a large scale controllability high, the silicon of uniformity high first
Nano-wire array FET, the uniformity high of its silicon nanowire array causes the FET as the sensitive unit such as sensor
During part, all silicon nanowires are detected simultaneously by measured signal in silicon nanowire array, are ensureing the constant feelings of outside noise size
Under condition, the superposition of measured signal is effectively realized, drastically increase signal to noise ratio and device performance so that the circuit part of device
Extremely easily realize, be that the extensive use of silicon nanowires lays the first stone.
In sum, a kind of wafer level of the present utility model prepares silicon nanowire array FET, with following beneficial
Effect：
1. the utility model is provided with the soi wafer of oxide layer due to use centre, when carrying out dry etching to top layer silicon, by
In the stop of oxide layer, the depth of the groove array is all the thickness of top layer silicon, and the etchant solution corrosion in wet etching
(111) speed of crystal orientation is very low, is capable of the thickness of precise control silicon thin-walled, and then cause the silicon nanometer prepared by the utility model
Line has controllability high and uniformity high.
2. the utility model sets grid by every silicon nanowires, grid is covered all of silicon nanowires,
And be effectively physically separated source electrode and drain electrode by isolation channel, it is ensured that the device performance of FET.
3. silicon nanowires described in the utility model due to its entirety be attached to silicon nitride mask layer on, silicon can be prevented effectively from and received
Rice noodles are broken, high yield rate.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all be carried out under without prejudice to spirit and scope of the present utility model to above-described embodiment
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model
All equivalent modifications completed under god and technological thought or change, should be covered by claim of the present utility model.
Claims (6)
1. a kind of silicon nanowire array FET, it is characterised in that the silicon nanowire array FET includes：
One (111) type soi wafer, (111) the type soi wafer includes bottom silicon, oxide layer and top layer silicon；
Positioned at the silicon nitride mask layer of the top layer silicon upper surface and oxide layer, wherein, the silicon nitride mask layer surface
It is formed with the hexagon etching tank array for exposing the oxide layer；
Positioned at the silicon nanowire array of silicon nitride mask layer lower surface；
Positioned at silicon nitride mask layer upper surface and grid corresponding with the silicon nanowire array position；And
Source electrode and drain electrode positioned at silicon nitride mask layer upper surface, wherein, it is provided with least between the source electrode and drain electrode
One isolation channel of the exposure oxide layer.
2. silicon nanowire array FET according to claim 1, it is characterised in that the thickness of the top layer silicon is small
In equal to 30um.
3. silicon nanowire array FET according to claim 1, it is characterised in that appoint in the silicon nanowire array
The width of one silicon nanowires is 70~110nm.
4. silicon nanowire array FET according to claim 1, it is characterised in that the silicon nanowire array is fork
Refer to structure, and the grid is interdigital structure.
5. silicon nanowire array FET according to claim 1, it is characterised in that set between the source electrode and drain electrode
It is equipped with 2 isolation channels.
6. silicon nanowire array FET according to claim 1, it is characterised in that the grid be gold, copper, aluminium or
One kind in polysilicon.
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| CN106449417A (en) * | 2016-12-14 | 2017-02-22 | 中国科学院上海微系统与信息技术研究所 | Method for wafer-level preparation of silicon nanowire array field-effect transistor and structure of silicon nanowire array field-effect transistor |
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| CN106449417A (en) * | 2016-12-14 | 2017-02-22 | 中国科学院上海微系统与信息技术研究所 | Method for wafer-level preparation of silicon nanowire array field-effect transistor and structure of silicon nanowire array field-effect transistor |
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