CN102623347B - Manufacturing method of three-dimensional array SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon - Google Patents
Manufacturing method of three-dimensional array SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a three-dimensional array SiNWFET (Silicon-Nanowire Field Effect Transistor) based on bulk silicon. The manufacturing method comprises the following steps of: providing a bulk-silicon substrate, and alternatively growing SiGe layers and Si layers on the bulk-silicon substrate; photoetching and etching the SiGe layers and the Si layers, forming a fin-shaped active region and using the remaining SiGe layers and the remaining Si layers as source-drain regions; removing the SiGe layers in the fin-shaped active region by selective etching, and forming three-dimensional array silicon nano wires; forming a grid oxidation layer on the silicon nanowires, the bulk-silicon substrate and the source-drain regions; forming a grid in the bulk-silicon substrate among the source-drain regions; and forming an isolating dielectric layer between the source-drain regions and the grid. According to the manufacturing method disclosed by the invention, due to the adoption of the three-dimensional array silicon-nanowire structure, the integration of the device and the current driving capability of the device are multiply increased; and the conventional grid oxidation layer is adopted.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of three-dimensional array type silicon nanowires field-effect transistor (SiNWFET) preparation method based on body silicon.
Background technology
In prior art, by dwindling transistorized size, improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in microelectronics industry development always.Current, the long 20nm that approached of physical gate of field-effect transistor, gate medium also only has several oxygen atom bed thickness, by dwindling the size of conventional field effect transistor, improve performance and faced some difficulties, this is mainly because short-channel effect and grid leakage current degenerate transistorized switch performance under small size.
Nano-wire field effect transistor (Nanowire MOSFET, NWFET) is expected to address this problem.On the one hand, little channel thickness and width make the grid of nano-wire field effect transistor closer to the various piece of raceway groove, contribute to the enhancing of transistor gate modulation capability, and they mostly adopt and enclose grid structure, grid is modulated raceway groove from multiple directions, further enhanced modulation ability, improves Sub-Threshold Characteristic.Therefore, nano-wire field effect transistor can suppress short-channel effect well, and transistor size is further dwindled.On the other hand, nano-wire field effect transistor utilizes the rill road of self and encloses grid Structure Improvement grid modulation power and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced the discrete distribution of impurity and Coulomb scattering in raceway groove.For 1-dimention nano wire channel, due to quantum limitation effect, in raceway groove charge carrier away from surface distributed, therefore carrier transport be subject to surface scattering and channel laterally electric field influence little, can obtain higher mobility.Based on above advantage, nano-wire field effect transistor more and more receives scientific research personnel's concern.Due to silicon materials and technique, in semi-conductor industry, occupy dominant position, compare with other materials, the making of silicon nanowires field-effect transistor (SiNWFET) more easily with current process compatible.
The critical process of nano-wire field effect transistor is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.Making for silicon nanowires, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technique, the latter is gas-liquid-solid (VLS) growth mechanism based on metal catalytic mainly, usings catalyst granules as nucleating point in growth course.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of silicon nanowires field-effect transistor due to its randomness, therefore the silicon nanowires in current silicon nanowires field-effect transistor is mainly to prepare by top-down process route.
At present, the research of field-effect transistor based on single silicon nanowires (MOSFET) its preparation process is more popular, if application number is 200710098812.4, denomination of invention is the Chinese patent of " a kind of preparation method of bulk silicon nano line transistor device ", a kind of process that top-down approach realizes bulk silicon nano line structure of passing through based on body silicon is disclosed, due to its process characteristic based on body silicon, the effectively self-heating effect of suppression device.
But along with dwindling of silicon nanowires sectional area, the current driving ability of device can be subject to the restriction of nano wire sectional area, the application of silicon nanowires field-effect transistor in simulation or radio circuit is restricted, therefore, someone begins one's study and adopts many nano wires as transporting raceway groove, to address this problem.But because many nanowire channel structures are laterally preparations, its integration density will be had a greatly reduced quality.
The people such as W.W.Fang are at IEEE ELECTRON DEVICE LETTERS, VOL.28, NO.3, in the paper < < Vertically Stacked SiGe Nanowire Array ChannelCMOS Transistors > > delivering on MARCH 2007, a kind of method of longitudinally preparing silicon nanowires has been proposed, make silicon nanowires FET device at many silicon nanowires of Top-down design, thereby the current driving ability of device is increased exponentially, integration density is unaffected simultaneously.Not only can keep the advantage of planar structure field-effect transistor (FET) but also strengthened grid modulation ability.Its process is at upper alternating growth (Ge/SiGe)/Si/ (the Ge/SiGe)/Si layer of SOI (Silicon on Insulator), and define fin-shaped (Fin) structure thereon, then carry out 750 ℃ of dry-oxygen oxidations, due to SiGe layer compared with Si layer have faster oxidation rate so that SiGe layer completely oxidized, in oxidizing process, Ge enters contiguous Si layer surface and forms SiGe alloy, erodes and obtains three-dimensional pile up, Si nano wire that surface is wrapped with SiGe alloy after completely oxidized SiGe layer.Then carry out thermal oxidation, on silicon nanowires (SiNW) surface, form Si
1-Xge
xo
2as grid oxic horizon, the more unformed silicon of deposit or polysilicon, finally by chemical etching, form grid.The method can realize vertical stack type silicon nanowires field-effect transistor structure, but has a shortcoming: in SiGe layer oxidizing process, Ge can be concentrated to the surface of Si layer, removes after SiO2, at surface of silicon nanowires, is wrapped with the SiGe alloy after one deck concentrates.Because GeO2 is water-soluble, it makes subsequent technique face huge inconvenience, and in addition, the dielectric constant of GeO2 is little compared with SiO2, and the interfacial state of GeO2 and Si is larger, is not suitable as the gate oxide of field-effect transistor (FET).
Summary of the invention
The object of the present invention is to provide a kind of three-dimensional array type SiNWFET preparation method based on body silicon, can effectively increase integrated level and the device current driving force of SiNWFET, and realize the conventional grid oxic horizon structure of silicon nanowires field-effect transistor.
For solving the problems of the technologies described above, the invention provides a kind of three-dimensional array type SiNWFET preparation method based on body silicon, comprise the following steps:
One silicon substrate is provided, and on described body silicon substrate, alternating growth has SiGe layer and Si layer;
Described SiGe layer and Si layer are carried out to photoetching and etching, form array fin-shaped active area, remaining SiGe layer and Si layer are as source-drain area;
By selective etch, remove the SiGe layer in described array fin-shaped active area, form three-dimensional array type silicon nanowires;
On described three-dimensional array type silicon nanowires, body silicon substrate and source-drain area, form grid oxic horizon;
On the body silicon substrate between described source-drain area, form grid;
Between described source-drain area and described grid, form spacer medium layer.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, the nearest one deck of the described body silicon substrate of distance is SiGe layer, apart from body silicon substrate one deck farthest, is also SiGe layer.
Optionally, in the described three-dimensional array type SiNWFET preparation method based on body silicon, before described SiGe layer and Si layer are carried out to photoetching and etching, Implantation is carried out in the region between described source-drain area.
Optionally, in the described three-dimensional array type SiNWFET preparation method based on body silicon, before described SiGe layer and Si layer are carried out to photoetching and etching, described source-drain area is carried out to Implantation.
Optionally, in the described three-dimensional array type SiNWFET preparation method based on body silicon, after forming grid on the body silicon substrate between described source-drain area, described source-drain area is carried out to Implantation.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, described selective etch adopts time normal pressure chemical gas phase etching method.
Optionally, in the described three-dimensional array type SiNWFET preparation method based on body silicon, described time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, every described silicon nanowires diameter is between 1 nanometer～1 micron.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, the cross sectional shape of every described silicon nanowires is circular, horizontal track type or longitudinal track type.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, form grid oxic horizon on described three-dimensional array type silicon nanowires, body silicon substrate and source-drain area before, also comprise:
Described three-dimensional array type silicon nanowires is carried out to thermal oxidation;
Etch away the silicon dioxide that described thermal oxidation forms.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, the material of described grid oxic horizon is silicon dioxide, silicon oxynitride or high K dielectric layer.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, described high K dielectric layer is a kind of or its combination in any in HfO2, Al2O3, ZrO2.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, the material of described grid is a kind of or its combination in any in polysilicon, amorphous silicon, metal.
In the described three-dimensional array type SiNWFET preparation method based on body silicon, the material of described spacer medium layer is silicon dioxide.
The three-dimensional array type silicon nanowires field-effect transistor structure that the present invention is based on body silicon has the following advantages:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area is connected with body silicon substrate, and the amount of heat that device produces in the course of the work can effectively be passed to body silicon substrate by source-drain area and shed, thereby without self-heating effect.
2, adopt three-dimensional array type silicon nanowire structure to design silicon nanowires field-effect transistor (SiNWFET) structure, three-dimensional array type structure makes device integrated level become multiple to increase, thereby nano wire number also becomes multiple to increase, further, make device current driving force also become multiple to increase.
3, on three-dimensional array type silicon nanowires, forming gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, as silicon dioxide.
4, in fin-shaped active area, form grid, then form spacer medium layer, be rear spacer processes, without carrying out side wall technique; And make source-drain area and gate upper surface in same level, be beneficial to follow-up contact hole technique.
Accompanying drawing explanation
Fig. 1 is the three-dimensional array type SiNWFET preparation method flow chart based on body silicon in one embodiment of the invention;
Fig. 2 is that the X-X ' of body silicon substrate in one embodiment of the invention is to generalized section;
Fig. 3 be in one embodiment of the invention, ion implantation technology is carried out in the region between source-drain area X-X ' to generalized section;
Fig. 4 a and Fig. 4 b be respectively in one embodiment of the invention array fin-shaped active area X-X ' to and Y-Y ' to generalized section;
Fig. 5 a and Fig. 5 b be respectively the array fin-shaped active area X-X ' that removes in one embodiment of the invention after SiGe layer to and Y-Y ' to generalized section;
Fig. 6 forms the schematic perspective view of three-dimensional array type nano wire in one embodiment of the invention;
Fig. 7 is the cross sectional shape schematic diagram of every silicon nanowires in one embodiment of the invention;
Fig. 8 forms the schematic perspective view of grid oxic horizon in one embodiment of the invention;
Fig. 9 a and Fig. 9 b be respectively in one embodiment of the invention after deposition of gate material X-X ' to and Y-Y ' generalized section;
Figure 10 a and Figure 10 b be respectively in one embodiment of the invention to grid material carry out X-X ' after cmp to and Y-Y ' to generalized section;
Figure 11 a and Figure 11 b be respectively the X-X ' that forms in one embodiment of the invention after grid to and Y-Y ' to generalized section;
Figure 12 forms the schematic perspective view after grid in one embodiment of the invention;
Figure 13 a and Figure 13 b be respectively the X-X ' that deposits in one embodiment of the invention after spacer medium to and Y-Y ' to generalized section;
Figure 14 a and Figure 14 b be respectively the X-X ' that forms in one embodiment of the invention after spacer medium layer to and Y-Y ' to generalized section;
Figure 15 be in one embodiment of the invention, source-drain area is carried out to ion implantation technology X-X ' to generalized section;
Figure 16 carries out the X-X ' of autoregistration silicon, germanium silicon metal alloy (Salicidation) technique to generalized section in one embodiment of the invention;
Figure 17 a and Figure 17 b be respectively in one embodiment of the invention by the X-X ' after the metal interconnected technique in rear road to and Y-Y ' to generalized section;
Figure 18 forms the schematic perspective view after source electrode connector, gate plug and drain plug in one embodiment of the invention;
Figure 19 is three-dimensional array type silicon nanowires field-effect transistor structure schematic top plan view in one embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
First, as shown in figure 19, for clearer description the present embodiment, the length direction of the silicon nanowires 6 of definition fin-shaped active area 5 or follow-up formation is X-X ' to, X-X ' to running through grid 8 and source-drain area 14, perpendicular to X-X ' to be Y-Y ' to.In the present embodiment, the 3*3 array silicon nano wire of take is example.Manufacture method below in conjunction with the three-dimensional array type SiNWFET based on body silicon of the detailed description one embodiment of the invention of Fig. 1 to 19.
As shown in Figure 1, the manufacture method of the three-dimensional array type SiNWFET based on body silicon of one embodiment of the invention, comprises the steps:
As shown in Figure 2, one silicon substrate 1 is provided, on body silicon substrate 1, alternating growth has SiGe layer 3 and Si layer 2, the quantity of supposing Si layer 2 is n layer, and the quantity of SiGe layer 3 is n+1 layer, wherein, n >=1, that is, (below) epitaxial loayer nearest apart from body silicon substrate 1 is SiGe layer 3, apart from body silicon substrate 1 (the top) epitaxial loayer farthest, is also SiGe layer 3.Owing to the present invention is based on body silicon, silicon nanowires field-effect transistor source-drain area 14 is connected with body silicon substrate 1, and the amount of heat that device produces in the course of the work can effectively be passed to body silicon substrate 1 by source-drain area 14 and shed, thereby without self-heating effect.In the present embodiment, take four layers of SiGe layer of alternating growth and three layers of Si layer is example.
As shown in Figure 3, Implantation is carried out in the region between source-drain area 14, be and adulterated in the channel region of field-effect transistor.Concrete, this step can be by following process implementation: first by photoetching (Photo) technique, form patterned photoresist layer 4 on SiGe layer 3, then the patterned photoresist layer 4 of take carries out Implantation (Imp) technique as mask, then, remove described patterned photoresist layer 4 (PR Strip), carry out subsequently trap annealing (Well Anneal) technique.It should be noted that, this step is optional step, according to device, electrically requires can omit in permission situation.
As shown in Figs. 4a and 4b, SiGe layer 3 and Si layer 2 are carried out to photoetching and etching, form array fin-shaped active area 5, remaining SiGe layer 3 and Si layer 2 are as source-drain area 14.Preferably, can adopt optical lithography (Photolithography) or electron beam lithography (electron beam lithography), etching runs through all epitaxy Si Ge layers 3 and Si layer 2, until expose the surface of body silicon substrate 1.
As shown in Fig. 5 a and 5b, by selective etch, remove the SiGe layer 3 in array fin-shaped active area 5; Preferably, utilize time normal pressure chemical gas phase etching method to carry out selective etch, temperature can adopt 600 ℃～800 ℃, and etching gas is selected the mist of H2 and HCl, and wherein the dividing potential drop of HCl is greater than 300Torr.This selective etch step is until all etch away the SiGe layer 3 between the Si layer 2 along Y-Y ' direction, and remaining Si layer 2 is as array silicon nano wire 6, and SiGe layer 3 part of X-X ' direction are retained, and usings as source-drain area 14.Optionally, before this step, also can first to source-drain area 14, carry out ion implantation technology.
As shown in Figure 6, pair array formula silicon nanowires 6 is optimized and subtracts thin.This step can be passed through thermal oxidation technology, and pair array formula silicon nanowires 6, body silicon substrate 1 and source-drain area 14 surfaces are oxidized.Further, if described thermal oxidation is furnace oxidation (Furnace Oxidation), oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), oxidization time scope is 1 second to 30 minutes.Then by wet-etching technology, remove the silicon dioxide that above-mentioned steps forms on array silicon nano wire 6, body silicon substrate 1 and source-drain area 14 surfaces.Every the silicon nanowires diameter finally forming is between 1 nanometer～1 micron.Be understandable that, according to the thickness of Si layer 2 and every row fin-shaped active area 5 lateral dimensions, vary in size, the cross sectional shape of every silicon nanowires also can be different, for example, the cross sectional shape of every silicon nanowires can be the longitudinal track type shown in circle, the horizontal track type shown in centre or the rightmost side as shown in the leftmost side in Fig. 7.If by more advanced figure transfer techniques, can fin-shaped active area (Fin) physical dimension more accurately be controlled so, thereby be more conducive to the shape optimization of silicon nanowires and subtract carefully, and can accurately control the diameter of silicon nanowires.
As shown in Figure 8, on array silicon nano wire 6, body silicon substrate 1 and source-drain area 14, form grid oxic horizon 7, described grid oxic horizon 7 can be SiO2, SiON or high K dielectric layer, and described high K dielectric layer is for example a kind of or its combination in any in HfO2, Al2O3, ZrO2.The general oxidation technology that adopts in forming grid oxic horizon step, described oxidation technology can adopt furnace oxidation (Furnace Oxidation), rapid thermal oxidation (RTO), chemical vapor deposition (Chemical Vapor Deposition, CVD) a kind of in, to form silicon dioxide on array silicon nano wire 6, body silicon substrate 1 and source-drain area 14 surfaces, thereby formed conventional grid oxic horizon 7.Be understandable that, also can form SiON adding in nitrogen atmosphere situation; Or, also can adopt ald (ALD) deposition techniques high K dielectric layer.Wherein, between source-drain area 14 above body silicon substrate 1 formed grid oxic horizon 7 using the separator with body silicon substrate 1 as subsequent gate 8.
As shown in Fig. 9 a and Fig. 9 b, on body silicon substrate 1 between source-drain area 14, (outside fin-shaped active area 5) carries out the deposition of grid material 8 ', and described grid material 8 ' can be a kind of or its combination in any in polysilicon, amorphous silicon, metal (being preferably the metallic compound of aluminium or titanium or tantalum).
As shown in Figure 10 a and Figure 10 b, adopt cmp to remove unnecessary grid material 8 ', make the upper surface of remaining grid material 8 ' and SiGe layer 3 in same level.
As shown in Figure 11 a and Figure 11 b, remaining grid material 8 ' is carried out to photoetching and etching technics, form grid 8.At this moment can form the three-dimensional array type silicon nanowires that encloses grid shape as shown in figure 12.Concrete, in described photoetching process, can adopt hard mask or photo-resistive mask.
As shown in Figure 13 a and 13b, between source-drain area 14 and source-drain area 14 and grid 8, deposit spacer medium 9 ', described spacer medium 9 ' is generally silicon dioxide.
As shown in Figure 14 a and 14b, adopt chemical mechanical milling tech, remove unnecessary spacer medium 9 ', remaining spacer medium 9 ' is as spacer medium layer 9; Make the upper surface of spacer medium layer 9 and grid 8 and SiGe layer 3 in same level, thereby be beneficial to follow-up contact hole technique.The present invention adopts and first forms grid 8, then forms spacer medium layer 9, is rear spacer processes, and without carrying out side wall technique.
As shown in figure 15, the patterned photoresist layer 4 of take is mask, and source-drain area 14 is carried out to ion implantation technology; Concrete, this step can be by following process implementation: first by photoetching (Photo) technique, on SiGe layer 3 and grid 8 and spacer medium layer 9 upper surface, form patterned photoresist layer 4, then the patterned photoresist layer 4 of take carries out Implantation (Imp) technique as mask, then, remove described patterned photoresist layer 4 (PR Strip), carry out subsequently source-drain electrode annealing (S/D Anneal) technique.It should be noted that, this step can be carried out before 5 graphical definition of fin-shaped active area, also can through cmp (CMP), carry out afterwards at grid material 8 '.
As shown in figure 16, carry out autoregistration silicon alloy (Salicidation) technique, form silicon, germanium silicon metal alloy layer 10.
As shown in Figure 17 a, 17b and 18, by the metal interconnected technique in rear road, form source electrode connector 11, gate plug 12 and drain plug 13, to draw respectively source electrode, grid and the drain electrode of field-effect transistor (FET).
Finally, please refer to Figure 18 and Figure 19, it is schematic perspective view and the schematic top plan view of the three-dimensional array type SiNWFET based on body silicon after finally completing.
In sum, the three-dimensional array type silicon nanowires field-effect transistor structure based on body silicon that one embodiment of the invention provides has the following advantages:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area is connected with body silicon substrate, and the amount of heat that device produces in the course of the work can effectively be passed to body silicon substrate by source-drain area and shed, thereby without self-heating effect.
2, adopt three-dimensional array type silicon nanowire structure to design silicon nanowires field-effect transistor (SiNWFET) structure, three-dimensional array type structure makes device integrated level become multiple to increase, thereby nano wire number also becomes multiple to increase, further, make device current driving force also become multiple to increase.
3, on three-dimensional array type silicon nanowires, forming gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, as silicon dioxide.
4, in fin-shaped active area, form grid, then form spacer medium layer, be rear spacer processes, without carrying out side wall technique; And make source-drain area and gate upper surface in same level, be beneficial to follow-up contact hole technique.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (14)
1. the three-dimensional array type SiNWFET preparation method based on body silicon, is characterized in that, comprising:
One silicon substrate is provided, and on described body silicon substrate, alternating growth has SiGe layer and Si layer, and SiGe layer is than the many one deck of Si layer;
Described SiGe layer and Si layer are carried out to photoetching and etching, form array fin-shaped active area, the remaining SiGe layer that is positioned at two ends, array fin-shaped active area and Si layer are as source-drain area;
By selective etch, remove the SiGe layer in described array fin-shaped active area, form three-dimensional array type silicon nanowires;
On described three-dimensional array type silicon nanowires, body silicon substrate and source-drain area, form grid oxic horizon;
On the body silicon substrate between described source-drain area, form grid;
Between described source-drain area and described grid, form spacer medium layer.
2. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, the nearest one deck of the described body silicon substrate of distance is SiGe layer, apart from body silicon substrate one deck farthest, is also SiGe layer.
3. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, before described SiGe layer and Si layer are carried out to photoetching and etching, Implantation is carried out in the region between described source-drain area.
4. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, before described SiGe layer and Si layer are carried out to photoetching and etching, described source-drain area is carried out to Implantation.
5. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, after forming grid, described source-drain area is carried out to Implantation on the body silicon substrate between described source-drain area.
6. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, described selective etch adopts time normal pressure chemical gas phase etching method.
7. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 6, it is characterized in that, described time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
8. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, every described silicon nanowires diameter is between 1 nanometer～1 micron.
9. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, the cross sectional shape of every described silicon nanowires is circular, horizontal track type or longitudinal track type.
10. the three-dimensional array type SiNWFET preparation method based on body silicon as claimed in claim 1, is characterized in that, before forming grid oxic horizon, also comprises on described three-dimensional array type silicon nanowires, body silicon substrate and source-drain area:
Described three-dimensional array type silicon nanowires is carried out to thermal oxidation;
Etch away the silicon dioxide that described thermal oxidation forms.
The 11. three-dimensional array type SiNWFET preparation methods based on body silicon as claimed in claim 1, is characterized in that, the material of described grid oxic horizon is silicon dioxide, silicon oxynitride or high K dielectric layer.
The 12. three-dimensional array type SiNWFET preparation methods based on body silicon as claimed in claim 11, is characterized in that, described high K dielectric layer is a kind of or its combination in any in HfO2, Al2O3, ZrO2.
The 13. three-dimensional array type SiNWFET preparation methods based on body silicon as claimed in claim 1, is characterized in that, the material of described grid is a kind of or its combination in any in polysilicon, amorphous silicon, metal.
The 14. three-dimensional array type SiNWFET preparation methods based on body silicon as claimed in claim 1, is characterized in that, the material of described spacer medium layer is silicon dioxide.
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| CN101295677A (en) * | 2007-04-27 | 2008-10-29 | 北京大学 | Production method of bulk silicon nano line transistor device |
| CN101894842A (en) * | 2009-05-21 | 2010-11-24 | 国际商业机器公司 | Field-effect transistor inverter and manufacture method |
| CN102315170A (en) * | 2011-05-26 | 2012-01-11 | 北京大学 | Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9728621B1 (en) | 2016-09-28 | 2017-08-08 | International Business Machines Corporation | iFinFET |
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