CN102664169B - Preparation method of silicon-on-insulator (SOI)-based rear-grid accumulation-mode silicon nanowire field-effect transistor (Si-NWFET) - Google Patents
Preparation method of silicon-on-insulator (SOI)-based rear-grid accumulation-mode silicon nanowire field-effect transistor (Si-NWFET) Download PDFInfo
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Abstract
The invention discloses a preparation method of a silicon-on-insulator (SOI)-based rear-grid accumulation-mode silicon nanowire field-effect transistor (Si-NWFET). The method comprises the following steps of etching a silicon layer and a silicon-germanium layer formed on an SOI substrate to form a fin-shaped active region; forming a silicon nanowire in the fin-shaped active region; forming a trench isolation medium layer and injecting ions in a source-drain region; forming a grid electrode and an accumulated-type PMOSFET through gold half-alloy technique; precipitating an interlayer isolation medium layer, and forming an accumulated nano metal-oxide-semiconductor field-effect transistor (NMOSFET) on the interlayer isolation medium layer. On the basis of the SOI substrate, the grid electrode can be well isolated to the silicon lining layer in the PMOSFET; an upper layer and a lower layer of semiconductor nanowire MOSFET are isolated by the interlayer isolation medium layer, so that the layer transfer technique is convenient to realize, the technical debugging can be completely independently completed, such as the adjustment of a work function of the grid electrode; and in addition, both the PMSOFET and the NMOSFET are of an accumulated type, so that devices have high carrier migration rate.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly a kind of rear grid type accumulation pattern Si-NWFET preparation method based on SOI.
Background technology
Improve by dwindling transistorized size chip operating rate and integrated level, to reduce chip power-consumption density be that microelectronics industry develops the target of pursuing always.In in the past 40 years, Moore's Law is being followed in microelectronics industry development always.Current, the long 20nm that approached of physical gate of field-effect transistor, gate medium also only has several oxygen atom bed thickness, improve performance and faced some difficulties by dwindling the size of conventional field effect transistor, this is mainly because short-channel effect and grid leakage current degenerate transistorized switch performance under small size.
Nano-wire field effect transistor (NWFET, NanowireMOSFET) is expected to address this problem.On the one hand, little channel thickness and width make the grid of NWFET closer to the various piece of raceway groove, contribute to the enhancing of transistor gate modulation capability; On the other hand, NWFET utilizes the rill road of self and encloses grid Structure Improvement grid modulation power and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced the discrete distribution of impurity and Coulomb scattering in raceway groove.For 1-dimention nano wire channel, due to quantum limitation effect, in raceway groove charge carrier away from surface distributed, therefore carrier transport be subject to surface scattering and channel laterally electric field influence little, can obtain higher mobility.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Because Si material and technique are occupied dominant position in semi-conductor industry, compared with other materials, the making of silicon nanowires field-effect transistor (Si-NWFET) more easily with current process compatible.The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of Si nano wire, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and ICP etching (inductively coupled plasma etching), RIE(reactive ion) etching or wet corrosion technique, the latter is gas-liquid-solid (VLS) growth mechanism based on metal catalytic mainly, in growth course using catalyst granules as nucleating point.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of Si-NWFET due to its randomness, and therefore the Si-NW in current silicon nanowires field-effect transistor is prepared by top-down process route.
Application number is that 200910199721.9 Chinese patent discloses a kind of mixed material accumulation type cylinder all-around-gate CMOS field effect transistor structure, and it is round by the full raceway groove cross section surrounding of grid; Application number is that 200910199725.7 Chinese patent discloses a kind of hybrid crystal orientation accumulation type total surrounding grid CMOS field-effect transistor structure, and it is racetrack by the full raceway groove cross section surrounding of grid; Application number is that 200910199723.8 Chinese patent discloses a kind of mixed material accumulation type total surrounding grid CMOS field effect transistor arrangement, it is racetrack by the full raceway groove cross section surrounding of grid, above 3 patents all adopt the MOSFET of accumulation type crystallographic orientation, have following shortcoming:
1.NMOS and PMOS share same grid layer, can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction, and in actual cmos circuit, have a large amount of NMOS and PMOS isolating construction;
2.NMOS and PMOS share same grid layer, cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS;
3. in technique, be difficult to realize for NMOS and PMOS and carry out respectively source leakage Implantation.
Summary of the invention
The invention provides a kind of rear grid type accumulation pattern Si-NWFET preparation method based on SOI, realize NMOSFET and PMOSFET isolating construction, can carry out respectively gate work-function adjusting, the adjusting of resistance rate and carry out respectively source leakage Implantation for NMOS and PMOS for NMOS and PMOS.
For solving the problems of the technologies described above, the invention provides a kind of rear grid type accumulation pattern Si-NWFET preparation method based on SOI, comprising: SOI substrate is provided, and described SOI substrate comprises silicon lining, oxygen buried layer and top layer silicon from the bottom to top successively; Described top layer silicon is converted into initial germanium silicon layer; On described initial germanium silicon layer, form silicon layer and follow-up germanium silicon layer, described initial germanium silicon layer and follow-up germanium silicon layer form germanium silicon layer jointly; To described germanium silicon layer and silicon layer etching processing, form fin-shaped active area; Germanium silicon layer described in etching, forms fin-shaped channel district, and remaining region is as source-drain area; In described fin-shaped active area, form silicon nanowires; In raceway groove on described SOI substrate, form spacer medium layer; Form grid oxic horizon on described silicon nanowires, SOI substrate and source-drain area surface; On the SOI substrate between described source-drain area, form grid; Carry out autoregistration gold half alloy technique, form accumulation type PMOSFET; Carry out the zone isolation cvd dielectric layer of accumulation type PMOSFET; On described zone isolation dielectric layer, form accumulation type NMOSFET; Carry out the metal interconnected technique of autoregistration gold half alloy and rear road, draw each port.
As preferably, the step that described SOI substrate top layer silicon is converted into initial germanium silicon layer comprises: deposit a germanium layer or germanium silicon layer at described SOI substrate surface; To described germanium layer and germanium silicon layer oxidation processes, the silicon that in described germanium layer or germanium silicon layer, germanium is oxidized in concentrated and described top layer silicon forms initial germanium silicon layer, and the upper surface of described initial germanium silicon layer is SiO
2layer; Wet method is removed described SiO
2layer.
As preferably, in described accumulation type PMOSFET, the surface orientation of silicon nanowires is (110), and described accumulation type PMOSFET channel direction is <110>.
As preferably, in accumulation type NMOSFET, the surface orientation of silicon nanowires is (100), and described accumulation type NMOSFET channel direction is <110>.
As preferably, after described germanium silicon layer and silicon layer etching processing, Implantation is carried out in the region between described source-drain area, described ionic type is P type.
As preferably, after forming spacer medium layer in the raceway groove on described SOI substrate, carry out source-drain area Implantation and annealing process.
As preferably, after forming grid on the SOI substrate between described source-drain area, carry out source-drain area Implantation and annealing process.
As preferably, the diameter of described silicon nanowires is between 1 nanometer ~ 1 micron.
As preferably, the cross sectional shape of described silicon nanowires is circular, laterally track type or longitudinal track type.
As preferably, described zone isolation dielectric layer is silicon dioxide or the low K silicon dioxide of the carbon containing with microcellular structure.
As preferably, the surface roughness of described zone isolation dielectric layer is less than 10nm.
As preferably, adopt germanium-silicon layer described in time normal pressure chemical gas phase etching method etching.
As preferably, described time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, and wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 DEG C～800 DEG C, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
As preferably, on described zone isolation dielectric layer, form in accumulation type NMOSFET step and adopt laser annealing technique to anneal to the source-drain area of described NMOSFET.
Compared with prior art, the rear grid type accumulation pattern Si-NWFET preparation method who the present invention is based on SOI has the following advantages:
1. based on SOI substrate, between PMOSFET and silicon lining, be provided with insulator layer, make can isolate well between grid and silicon lining;
2. upper and lower two-layer semiconductor nanowires MOSFET is kept apart by zone isolation dielectric layer, can completely independently carry out process debugging, as gate work-function regulates, resistance rate regulates and carry out respectively source leakage ion implantation technology for NMOS and PMOS;
3. in the present invention, PMOSFET and NMOSFET are accumulation type, and again because carrier mobility is body material mobility, therefore of the present invention have higher carrier mobility based on the double-deck isolation of SOI crystallographic orientation accumulation type Si-NWFET device.
Brief description of the drawings
Fig. 1 be in the present invention's one specific embodiment SOI substrate X-X ' to generalized section;
Fig. 2 be after forming germanium layer or germanium silicon layer in the present invention's one specific embodiment device X-X ' to generalized section;
Fig. 3 be in the present invention's one specific embodiment after oxidation technology device X-X ' to generalized section;
Fig. 4 be after removing silicon dioxide in the present invention's one specific embodiment device X-X ' to generalized section;
Fig. 5 be after forming silicon layer and germanium silicon layer in the present invention's one specific embodiment device X-X ' to generalized section;
Fig. 6 be in the present invention's one specific embodiment after the Implantation of channel region device X-X ' to generalized section;
Fig. 7 is that the present invention's one specific embodiment forms behind fin-shaped active area device Y-Y ' to generalized section;
Fig. 8 A ~ 8B be in the present invention's one specific embodiment after the germanium silicon etching of fin-shaped active area device X-X ' to and Y-Y ' to generalized section;
Fig. 8 C is the perspective view that forms device after silicon nanowires in the present invention's one specific embodiment;
Fig. 9 is the generalized section of silicon nanowires in the present invention's one specific embodiment;
Figure 10 A ~ 10B be in the present invention's one specific embodiment, deposit after spacer medium layer device X-X ' to and Y-Y ' to generalized section;
Figure 11 A ~ 11B be in the present invention's one specific embodiment, remove after unnecessary spacer medium layer device X-X ' to and Y-Y ' to generalized section;
Figure 12 be while carrying out source-drain area Implantation in the present invention's one specific embodiment device X-X ' to generalized section;
Figure 13 A ~ 13B be in the present invention's one specific embodiment, form after gate trench device X-X ' to and Y-Y ' to generalized section;
Figure 14 be after forming grid oxic horizon in the present invention's one specific embodiment device X-X ' to generalized section;
Figure 15 A ~ 15B be in the present invention's one specific embodiment after deposition of gate material device X-X ' to and Y-Y ' to generalized section;
Figure 16 A ~ 16B be in the present invention's one specific embodiment, remove after unnecessary grid material device X-X ' to and Y-Y ' to generalized section;
Figure 17 be in the present invention's one specific embodiment after autoregistration gold half alloy technique device X-X ' to generalized section;
Figure 18 be after depositing zone isolation dielectric layer in the present invention's one specific embodiment device X-X ' to generalized section;
Figure 19 A ~ 19B be after forming the process flow diagram of upper strata monocrystalline silicon layer and each technique in the present invention's one specific embodiment and completing device X-X ' to generalized section;
Figure 20 be after depositing silicon layer and follow-up germanium silicon layer in the present invention's one specific embodiment device X-X ' to generalized section;
Figure 21 be the present invention's one specific embodiment at the middle and upper levels when NMOSFET source-drain area Implantation device X-X ' to generalized section;
Figure 22 A ~ 22B be the present invention's one specific embodiment at the middle and upper levels after autoregistration gold half alloy technique device X-X ' to and Y-Y ' to generalized section;
Figure 23 A ~ 23B be in the present invention's one specific embodiment after metal interconnected technique X-X ' to and Y-Y ' to generalized section;
Figure 24 is the perspective view based on the double-deck isolation of SOI crystallographic orientation accumulation type Si-NWFET in the present invention's one specific embodiment;
Figure 25 is the schematic top plan view based on the double-deck isolation of SOI crystallographic orientation accumulation type Si-NWFET in the present invention's one specific embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
As shown in figure 25, for clearer description the present embodiment, the length direction of the silicon nanowires of definition fin-shaped active area or follow-up formation is X-X ' to, X-X ' to running through grid and source-drain area, perpendicular to X-X ' to be Y-Y ' to.
Rear grid type accumulation pattern Si-NWFET preparation method below in conjunction with the detailed description one embodiment of the invention of Fig. 1 to 25 based on SOI, specifically comprises:
Please refer to Fig. 1, SOI substrate is provided, the bottom of described SOI substrate is the silicon lining 1 for mechanical support is provided, and is insulator layer on silicon lining 1, and the present invention adopts oxygen buried layer (BOX) 2 as insulator layer, is top layer silicon 3 on oxygen buried layer 2.
Then, the top layer silicon of described SOI substrate 3 is converted into initial germanium silicon layer 6 '; Specifically comprise: first, please refer to Fig. 2, forming a germanium layer 4(germanium layer at SOI substrate surface can be substituted by germanium silicon layer); Then, please refer to Fig. 3, SOI substrate surface is carried out to oxidation processes, germanium layer 4, because oxidation is concentrated to be seeped in top layer silicon 3, forms initial germanium silicon layer 6 ', and the silicon of initial germanium silicon layer 6 ' upper surface is oxidized into silicon dioxide layer 5; Then, please refer to Fig. 4, wet-etching technology is removed the silicon dioxide layer 5 of SOI substrate surface; Now, the silicon layer 3 of SOI substrate is converted into initial germanium silicon layer 6 '.
Please refer to Fig. 5, on initial germanium silicon layer 6 ', form respectively silicon layer 7 and follow-up germanium silicon layer 6 ", first at the upper epitaxial growth silicon layer 7 of initial germanium silicon layer 6 ', the follow-up germanium silicon layer 6 of epitaxial growth ", for convenience of describing, by initial germanium silicon layer 6 ' and follow-up germanium silicon layer 6 " be referred to as germanium silicon layer 6.
Please refer to Fig. 6, Implantation is carried out in the channel region of SOI substrate, be specially: first, on germanium silicon layer 6, carry out photoetching process, cover photoresist 8 and please refer to Figure 26 at follow-up formation source-drain area 10(), then carry out Implantation, ionic type is P type, the photoresist 8 on removal source-drain area 10 surfaces after Implantation completes.It should be noted that, this step is optional step, electrically requires can omit in permission situation according to device.
Please refer to Fig. 7, to described germanium silicon layer 6 and silicon layer 7 etching processing, form fin-shaped active area 201(and please refer to Figure 26), remaining region is as source-drain area 10; Can adopt optical lithography (Photolithography) or electron beam lithography (electron beam lithography), etch away fin-shaped active area 201 unnecessary germanium silicon layer 6 and silicon layer 7 around, until expose oxygen buried layer 2 surfaces.
Please refer to Fig. 8 A ~ 8C, continue the germanium silicon layer 6 in etching fin-shaped active area, form fin-shaped channel district, at the interior formation silicon nanowires 71 in described fin-shaped active area 201; Be specially, selective etch is removed the germanium silicon layer 6 in fin-shaped active area 201, forms fin-shaped channel district, optional, utilizes time normal pressure chemical gas phase etching method to carry out selective etch, can adopt the H under 600 ~ 800 degrees Celsius
2with HCL mist, wherein the dividing potential drop of HCL is greater than 300Torr, and selective etch step is until all removals of germanium silicon layer 6 in fin-shaped active area 201;
Then, fin-shaped active area 201, SOI substrate and source-drain area 10 surfaces are oxidized, control oxidization time, utilize wet processing to remove the SiO on fin-shaped active area 201, SOI substrate and source-drain area 10 surfaces
2thereby, form silicon nanowires 71(and please refer to Fig. 8 C).Further, if described thermal oxidation is furnace oxidation (Furnace Oxidation), oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), oxidization time scope is 1 second to 30 minutes, then removes by wet processing the silicon dioxide that above-mentioned steps forms on silicon nanowires 71 and oxygen buried layer 2 and source-drain area 10 surfaces.The diameter of the silicon nanowires 71 finally forming is between 1 nanometer ~ 1 micron.
Because thickness and fin-shaped active area 201 lateral dimensions of silicon layer 7 vary in size, the cross sectional shape of silicon nanowires 71 is also different, please refer to Fig. 9, the cross sectional shape of silicon nanowires 71 comprises circular 301, laterally track type 302 and longitudinally track type 303, preferred cross-sections of the present invention is shaped as circular 301 silicon nanowires 71, by more advanced figure transfer techniques, can more accurately control fin-shaped active area (Fin) physical dimension, thereby more be conducive to the shape optimization of silicon nanowires 71 and the diameter of accurate control silicon nanowires 71.
Please refer to Figure 10 A ~ 13B, the channel region outside fin-shaped active area forms channel isolation dielectric layer 9 ', is specially:
As shown in Figure 10 A ~ 10B, the SOI substrate in fin-shaped active area 201 and source-drain area 10 surface deposition channel isolation dielectric layers 9 '; Then, please refer to Figure 11 A ~ 11B, remove fin-shaped active area 201 and the source-drain area 10 unnecessary channel isolation dielectric layers 9 ' in surface, make spacer medium layer 9 ' after etching with source-drain area 10 upper surfaces in same level.
Please refer to Figure 12, carry out source-drain area ion implantation technology, be specially: first carry out photoetching process, the region of part covers photoresist 8 ' beyond source-drain area 10; Then, select dissimilar ion to inject for dissimilar MOS transistor; Finally, remove photoresist 8 ' and source-drain area 10 annealed to activate the ion being injected into.Alternatively, source-drain area Implantation and annealing process also can carry out after grid forms.
Please refer to Figure 13 A ~ 13B, photoetching and selective etch are removed unnecessary channel isolation dielectric layer 9 ' between source-drain area, form gate trench, and described gate trench is for follow-up formation grid 202.
Please refer to Figure 14 ~ 16B, on silicon nanowires 71, form grid oxic horizon, in gate trench, form grid 202, be specially:
First, please refer to Figure 14, form grid oxic horizon 11 at surface of silicon nanowires, what wherein grid oxic horizon adopted is conventional grid oxic horizon material, and therefore the material of grid oxic horizon 11 can be the SiO that furnace oxidation, rapid thermal oxidation or technique for atomic layer deposition (ALD) form
2or SiON or for adopting the high K medium (high dielectric radio medium) of ald or its combination, high K medium is HfO
2, Al
2o
3, ZrO
2in a kind of or its combination in any; Because the existence of the oxygen buried layer 2 in grid oxic horizon 11 and SOI substrate, makes subsequent gate 202 better with the isolation effect of SOI substrate.
Then, please refer to Figure 15 A ~ 15B, at fin-shaped active area 201 and source-drain area 10 surface deposition grid materials 12, grid material 12 can be polysilicon, amorphous silicon, and metal or its combination in any, wherein metal is preferably the metallic compound of aluminium or titanium or tantalum.
Then, please refer to Figure 16 A ~ 16B, adopt cmp to remove fin-shaped active area 201, the source-drain area 10 unnecessary grid materials 12 in surface, make grid material 12 and source-drain area 10 upper surfaces in same level.
Then, please refer to Figure 17, carry out autoregistration gold half alloy technique, form silicon alloy 13 at source-drain area 10 and grid 202 surfaces.Now, complete the formation of the accumulation type PMOSFET101 of lower floor based on the double-deck isolation of SOI crystallographic orientation accumulation type Si-NWFET device.
Then, please refer to Figure 18, carry out the zone isolation dielectric layer 9 of PMOSFET101 " deposition, and the surface roughness of described zone isolation dielectric layer 9 ' is less than 10nm; described zone isolation dielectric layer 9 " and identical with the material of channel isolation dielectric layer 9 ' employing, nominal is spacer medium layer 9.It should be noted that, described spacer medium layer 9 is silicon dioxide; Further, in order to reduce the capacitive coupling benefit between device, can be also the low K silicon dioxide layer of carbon containing of microcellular structure.
It should be noted that, accumulation type PMOSFET101 not exclusively covers SOI substrate, and remainder is for subsequent deposition spacer medium layer 9; In like manner, follow-up at zone isolation dielectric layer 9 " the upper NMOSFET102 forming also not exclusively covers described zone isolation dielectric layer 9 ", remainder is used for depositing spacer medium layer 9.
In addition, theoretically, in upper and lower two-layer transistor, can adopt the silicon nanowires of any surface orientation, and from achievement in research, (100) the electron mobility maximum in surface orientation and <110> raceway groove crystal orientation, the hole mobility maximum in (110) surface orientation and <110> raceway groove crystal orientation.Therefore, preferably, the channel material of the present invention using the silicon nanowires of (110) surface orientation as PMOSFET, and the channel direction of PMOSFET is <110>; Channel material using the silicon nanowires of (100) surface orientation as the NMOSFET of follow-up formation, and the channel direction of NMOSFET is <110>.
Then, on described PMOSFET101, form NMOSFET102, because PMOSFET101 has been prepared, in order not affect the performance of PMOSFET101 and metallic silicon alloy, in the preparation process of follow-up NMOSFET102, must adopt low temperature method.
First, please refer to Figure 19 A ~ 19B, monocrystalline silicon layer 3 ' and the support chip of the PMOSFET101 that is prepared with silicon nanowires are carried out to low-temperature bonding, specifically comprise: the routine of the silicon adhesive piece with monocrystalline silicon layer 3 ' 14 being carried out to silicon is cleaned, then carry out chemistry or plasma-activated processing, hydrophilic treated, room temperature laminating, low-temperature bonding, low temperature is peeled off and Low Temperature Solid-Phase or rheotaxial growth, makes zone isolation dielectric layer 9 " combine closely with monocrystalline silicon layer 3 '; Wherein, Low Temperature Solid-Phase or rheotaxial growth are optional step.
Preferably, in low temperature stripping technology, can adopt dosage is 5*10
16cm
-2to 9*10
16cm
-2note hydrogen sheet or hydrogen helium note altogether sheet and peel off in 500 about degree, and silicon adhesive piece 14 temperature are less than 400 degree; As preferably, described monocrystalline silicon layer 3 ' surface orientation is (100), more easily carries out peeling off of monocrystalline silicon layer 3 '.
Please refer to Figure 20, adopt low-temperature epitaxy technology and germanium oxidation concentration method, make monocrystalline silicon layer 3 ' be converted into initial germanium silicon layer 6A ', then epitaxial growth silicon layer 7 ' and follow-up germanium silicon layer 6A ", described initial germanium silicon layer 6A ' and follow-up germanium silicon layer 6A " jointly form germanium silicon layer 6A.As preferably, for reducing follow-up heat budget (thermal budget), in the time of silicon epitaxial layers, directly N-type ion doping is carried out in channel region, follow-uply do not need to carry out again channel ion injection technology.
Please refer to Figure 21, because formation, grid and the spacer medium preparation of silicon nanowires in NMOSFET102 and grid oxic horizon are basic identical with PMOSFET101, just adopt low temperature preparation method, repeat no more herein.Wherein, in source-drain area Implantation and annealing process, due to the requirement of temperature control, in this step, adopt laser anneal method, thereby can not affect PMOSFET101 performance while guaranteeing the NMOSFET102 differential annealing on upper strata.
Finally, please refer to Figure 22 A ~ 23B, carry out autoregistration gold half alloy and metal interconnected technique, each port of drawing the PMOSFET101 of lower floor and upper strata NMOSFET102.
In sum, continue referring to Figure 23 A ~ 23B, and in conjunction with Figure 24 ~ 25, the present invention is based on the double-deck isolation of SOI crystallographic orientation accumulation type Si-NWFET and have the following advantages:
1. adopt the accumulation type PMSOFET of lower floor to add a layer accumulation type NMOSFET pattern, effectively reduce the contact hole resistance of NMOSFET and improve NMOSFET performance;
2. accumulation type field-effect transistor source-drain area doping type is identical with channel doping type, conduction charge carrier is majority carrier, between source electrode and drain electrode and raceway groove, there is not PN junction, therefore be otherwise known as without PN junction field-effect transistor, in the present invention, PMOSFET and NMOSFET are accumulation type mode of operation, because carrier mobility is body material mobility, therefore the rear grid type accumulation pattern Si-NWFET device based on SOI of the present invention has higher carrier mobility again;
3. the channel material using the silicon nanowires of (110) surface orientation as PMOSFET, and the channel direction of PMOSFET is <110>; Channel material using the silicon nanowires of (100) surface orientation as NMOSFET, and the channel direction of NMOSFET is <110>, effectively increases the current driving ability of NMOSFET and PMOSFET;
4. upper and lower two-layer semiconductor nanowires MOSFET is kept apart by zone isolation dielectric layer, can completely independently carry out process debugging, as gate work-function regulates, resistance rate regulates and ion implantation technology is leaked in source;
5. based on SOI substrate, between PMOSFET and silicon lining, be provided with insulator layer, make can isolate well between grid and silicon lining;
The preparation of 6.NMOSFET adopts cryogenic technique and laser annealing, thereby realizes differential annealing, has effectively avoided the impact on lower floor's device performance;
7. longitudinally arrange owing to isolating crystallographic orientation accumulation type Si-NWFET based on SOI bilayer, thereby keep higher device integration density;
8. grid technology after adopting, the control of interests gate profile and device are electrically controlled;
9, adopt (100) surface orientation silicon layer as upper layer device initial silicon layer, facilitate layer transfer process to realize.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (13)
1. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI, comprising:
SOI substrate is provided, and described SOI substrate comprises silicon lining, oxygen buried layer and top layer silicon from the bottom to top successively;
Described top layer silicon is converted into initial germanium silicon layer;
On described initial germanium silicon layer, form silicon layer and follow-up germanium silicon layer, described initial germanium silicon layer and follow-up germanium silicon layer form germanium silicon layer jointly;
To described germanium silicon layer and silicon layer etching processing, form fin-shaped active area;
Germanium silicon layer described in etching, forms fin-shaped channel district, and remaining region is as source-drain area;
In described fin-shaped active area, form silicon nanowires;
In raceway groove on described SOI substrate, form spacer medium layer;
Form grid oxic horizon at described surface of silicon nanowires;
On SOI substrate in described fin-shaped active area, form grid;
Autoregistration gold half alloy technique forms accumulation type PMOSFET;
Carry out the zone isolation cvd dielectric layer of accumulation type PMOSFET;
By carrying out low-temperature bonding on monocrystalline silicon layer and described zone isolation dielectric layer, spacer medium layer and monocrystalline silicon layer are combined closely; Then monocrystalline silicon is converted to germanium silicon layer, and on germanium silicon layer, forms silicon layer and follow-up germanium silicon layer; Germanium silicon layer and silicon layer described in K cryogenic treatment, adopt low temperature preparation method and the identical method of accumulation type PMOSFET, prepare formation, grid and the spacer medium of silicon nanowires and grid oxic horizon, thereby form accumulation type NMOSFET on described zone isolation dielectric layer;
Carry out the metal interconnected technique of autoregistration gold half alloy and rear road.
2. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, the step that described SOI substrate top layer silicon is converted into initial germanium silicon layer comprises:
Deposit a germanium layer or germanium silicon layer at described SOI substrate surface;
To described germanium layer or germanium silicon layer oxidation processes, the silicon that in described germanium layer or germanium silicon layer, germanium is oxidized in concentrated and described top layer silicon forms initial germanium silicon layer, and the upper surface of described initial germanium silicon layer is SiO
2layer;
Wet method is removed described SiO
2layer.
3. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, it is characterized in that, in described accumulation type PMOSFET, the surface orientation of silicon nanowires is (110), and described accumulation type PMOSFET channel direction is <110>.
4. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, it is characterized in that, in described accumulation type NMOSFET, the surface orientation of silicon nanowires is (100), and described accumulation type NMOSFET channel direction is <110>.
5. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, it is characterized in that, form silicon layer and follow-up germanium silicon layer on described initial germanium silicon layer after, Implantation is carried out in the channel region of described SOI substrate, described ionic type is P type.
6. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, the diameter of described silicon nanowires is between 1 nanometer～1 micron.
7. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, the cross sectional shape of described silicon nanowires is circular, horizontal track type or longitudinal track type.
8. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, after forming spacer medium layer, described source-drain area is carried out to Implantation and annealing process in the raceway groove on described SOI substrate.
9. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, described zone isolation dielectric layer is silicon dioxide or the low K silicon dioxide of the carbon containing with microcellular structure.
10. the rear grid type accumulation pattern Si-NWFET preparation method based on SOI as claimed in claim 1, is characterized in that, the surface roughness of described zone isolation dielectric layer is less than 10nm.
The 11. rear grid type accumulation pattern Si-NWFET preparation methods based on SOI as claimed in claim 1, is characterized in that, adopt germanium silicon layer described in time normal pressure chemical gas phase etching method etching.
The 12. rear grid type accumulation pattern Si-NWFET preparation methods based on SOI as claimed in claim 11, it is characterized in that, described time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 DEG C～800 DEG C, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
The 13. rear grid type accumulation pattern Si-NWFET preparation methods based on SOI as claimed in claim 1, it is characterized in that, on described zone isolation dielectric layer, form in accumulation type NMOSFET step, adopt laser annealing technique to carry out differential annealing to the source-drain area of described accumulation type NMOSFET.
Priority Applications (1)
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| (110)-Surface Strained-SOI CMOS Devices;Tomohisa Mizuno et al.;《IEEE TRANSACTIONS ON ELECTRON DEVICES》;20050331;第52卷(第3期);第368页左栏第2段，图2 * |
| Tomohisa Mizuno et al..(110)-Surface Strained-SOI CMOS Devices.《IEEE TRANSACTIONS ON ELECTRON DEVICES》.2005,第52卷(第3期),367~372. |
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