CN102709245B - Method for preparing double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor) - Google Patents

Method for preparing double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor) Download PDF

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CN102709245B
CN102709245B CN 201210136020 CN201210136020A CN102709245B CN 102709245 B CN102709245 B CN 102709245B CN 201210136020 CN201210136020 CN 201210136020 CN 201210136020 A CN201210136020 A CN 201210136020A CN 102709245 B CN102709245 B CN 102709245B
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CN102709245A (en
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黄晓橹
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上海华力微电子有限公司
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Abstract

本发明提供一种制备双层SOI混合晶向后栅型反型模式SiNWFET的方法。 The present invention provides a method of double-gate SOI rearwardly mixed crystal inversion mode SiNWFET prepared. 本发明中PMOSFET采用(110)表面晶向硅层,NMOSFET采用(100)表面晶向硅层。 PMOSFET employed in the present invention (110) crystal surface of the silicon layer, NMOSFET from (100) crystal surface of the silicon layer. 在低温剥离技术中,随着氢气的压力增大,裂缝更倾向于沿(100)晶向生长,因此沿(100)晶向更容易进行硅层剥离,方便了层转移工艺实现。 In the cryogenic lift-off technique, as the hydrogen pressure increases, cracks tend along the (100) crystal to grow, and therefore along the (100) crystal for the silicon layer peeled off more easily and conveniently achieve a layer transfer process.

Description

制备双层SOI混合晶向后栅型反型模式SiNWFET的方法 A double layer back-gate SOI mixed crystal inversion mode method SiNWFET

技术领域 FIELD

[0001] 本发明涉及半导体场效应晶体管技术领域,尤其涉及一种制备双层SOI混合晶向后栅型反型模式SiNWFET的工艺步骤。 [0001] The present invention relates to the technical field of semiconductor field effect transistors, in particular, to a double SOI process step mixed crystal back-gate inversion mode SiNWFET prepared.

背景技术 Background technique

[0002] 通过缩小晶体管的尺寸来提高芯片的工作速度和集成度、减小芯片功耗密度一直是微电子工业发展所追求的目标。 [0002] to increase the operating speed of the chip and integration by reducing the size of transistors, reducing the power consumption of the chip density microelectronics industry has been the development of the objectives pursued. 在过去的四十年里,微电子工业发展一直遵循着摩尔定律。 Over the past four decades, the development of the microelectronics industry has followed Moore's Law. 当前,场效应晶体管的物理栅长已接近20nm,栅介质也仅有几个氧原子层厚,通过缩小传统场效应晶体管的尺寸来提高性能已面临一些困难,这主要是因为小尺寸下短沟道效应和栅极漏电流使晶体管的开关性能变坏。 Currently, the physical gate length of field effect transistors is close to 20 nm, the gate dielectric layer thickness is also only a few oxygen atoms, by reducing the size to improve the performance of a conventional field effect transistor has faced some difficulties, mainly because short-channel small size channeling and gate leakage current of the switching performance of the transistor deteriorates.

[0003] 纳米线场效应晶体管(NWFET,Nanowire MOSFET)有望解决这一问题。 [0003] nanowire field effect transistor (NWFET, Nanowire MOSFET) is expected to solve this problem. 一方面,小的沟道厚度和宽度使NWFET的栅极更接近于沟道的各个部分,有助于晶体管栅极调制能力的增强,而且它们大多采用围栅结构,栅极从多个方向对沟道进行调制,能够进一步增强调制能力,改善亚阈值特性。 In one aspect, a small channel width and thickness of the gate NWFET closer to the respective portion of the channel, gate modulation helps to enhance the ability of the transistor, and most of them employ the structure of a fence, a gate from a plurality of directions channel modulation, modulation capability can be further enhanced, improving the subthreshold. 因此,NWFET可以很好地抑制短沟道效应,使晶体管尺寸得以进一步缩小。 Thus, good rejection nwFET short channel effect, so that the transistor size can be further reduced. 另一方面,NWFET利用自身的细沟道和围栅结构改善栅极调制力和抑制短沟道效应,缓解了减薄栅介质厚度的要求,有望减小栅极漏电流。 On the other hand, fine nwFET using its own channel and gate structure surrounding gate modulation to improve strength and suppress the short channel effect, easing the required thickness of the thinned gate dielectric, the gate leakage current is expected to decrease. 此外,纳米线沟道可以不掺杂,减少了沟道内杂质离散分布和库仑散射。 Further, the nanowire channel may be undoped, it reduces the discrete channel impurity distribution and Coulomb scattering. 对于一维纳米线沟道,由于量子限制效应,沟道内载流子远离表面分布,故载流子输运受表面散射和沟道横向电场影响小,可以获得较高的迁移率。 For Nanowire channel, because of quantum confinement effects of carriers in the channel away from the surface profile, so that the carrier transport and the channel surface scattering by small transverse electric field effect mobility is high can be obtained. 基于以上优势,NWFET越来越受到科研人员的关注。 Based on the above advantages, NWFET more and more attention of researchers. 由于Si材料和工艺在半导体工业中占有主流地位,与其他材料相比,硅纳米线场效应晶体管(SiNWFET)的制作更容易与当前工艺兼容。 Since Si materials and processes in the mainstream in the semiconductor industry, as compared with other materials to produce silicon nanowire field effect transistor (SiNWFET) more easily compatible with the current technology.

[0004] NWFET的关键工艺是纳米线的制作,可分为自上而下和自下而上两种工艺路线。 [0004] NWFET key process is to produce nanowires, it can be divided into top-down and bottom-up process route. 对于Si纳米线的制作,前者主要利用光刻(光学光刻或电子束光刻)和刻蚀(ICP、RIE刻蚀或湿法腐蚀)工艺,后者主要基于金属催化的气-液-固(VLS)生长机制,生长过程中以催化剂颗粒作为成核点。 For the production of Si nanowires, the former mainly by photolithography (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) process, which is mainly based on metal-catalysed gas - liquid - solid (VLS) growth mechanism, the growth process the catalyst particles as nucleation sites. 目前,自下而上的工艺路线制备的硅纳米线由于其随机性而不太适合SiNWFET的制备,因此目前的硅纳米线场效应晶体管中的SiNW主要是通过自上而下的工艺路线制备。 Currently, silicon nanowires bottom due to randomness process route is not suitable for the preparation SiNWFET, so the current silicon nanowire field effect transistor SiNW mainly prepared by a top-down process route. 同时,现有的纳米线场效应晶体管也有其自身的缺陷。 Meanwhile, conventional nanowire field effect transistor has its own drawbacks.

[0005] 美国专利US20110254101A1中公开一种混合材料反型模式圆柱体全包围栅CMOS场效应晶体管的结构示意图。 [0005] U.S. Patent No. US20110254101A1 discloses a hybrid material inversion mode cylindrical structural diagram of CMOS field effect transistor gate-all-around. 所述全包围栅CMOS场效应晶体管被栅极区500'全包围的沟道301'、401'截面为圆型。 The gate-all-around 'the all-around channel 301' is the CMOS FET gate region 500, 401 'of circular cross section.

[0006] 美国专利US20110254102A1中公开了一种混合晶向反型模式全包围栅CMOS场效应晶体管的结构示意图。 [0006] U.S. Patent No. US20110254102A1 discloses a configuration diagram of a mixed crystal of the all-around inversion mode CMOS gate field effect transistor. 所述全包围栅CMOS场效应晶体管被栅极区500'全包围的沟道301'、401'截面为跑道型。 The gate-all-around 'the all-around channel 301' is the CMOS FET gate region 500, 401 'racetrack cross-section.

[0007] 美国专利US20110248354A1中公开了一种混合材料反型模式全包围栅CMOS场效应晶体管的结构示意图。 [0007] U.S. Patent No. US20110248354A1 discloses a hybrid material inversion mode FET gate CMOS structure diagram of the all-around. 所述全包围栅CMOS场效应晶体管被栅极区500'全包围的沟道301'、401'截面为跑道型。 The gate-all-around 'the all-around channel 301' is the CMOS FET gate region 500, 401 'racetrack cross-section. [0008] 上述公开文件中都采用反型模式混合晶向的M0SFET,其都存在以下缺陷:(1)NMOS区300'和PMOS区400'共用同一栅极区500',只能实现钳位式的CMOS结构,无法实现NMOS和PMOS分离结构;(2)NMOS区300'和PMOS区400'共用同一栅极区500',无法针对NMOS和PMOS分别进行栅极功函数调节和栅极电阻率调节;(3)实现针对NMOS和PMOS分别进行源漏离子注入的工艺难度大。 [0008] In the above-mentioned publication are used M0SFET inversion mode hybrid orientation, which have the following shortcomings: (1) NMOS region 300 'and a PMOS region 400' share the same gate region 500 'can be achieved only clamped CMOS structure, separation can not be achieved NMOS and PMOS structures; (2) NMOS region 300 'and a PMOS region 400' share the same gate region 500 ', respectively, can not be adjusted and the gate work function of the gate resistance adjustment for NMOS and PMOS ; (3) the source and drain, respectively achieve large ion implantation process difficulty for NMOS and PMOS.

发明内容 SUMMARY

[0009] 本发明是针对现有技术中,现有的半导体纳米线MOSFET无法实现NMOS和PMOS分离结构,无法针对NMOS和PMOS分别进行栅极功函数调节和栅极电阻率调节,以及实现针对NMOS和PMOS分别进行源漏离子注入的工艺难度大等缺陷提供一种制备SOI上双层隔离混合晶向后栅型反型模式SiNWFET的方法。 [0009] The present invention is directed to the prior art, the conventional MOSFET semiconductor nanowire separation can not be achieved NMOS and PMOS structures, can not be adjusted and the gate work function of the gate resistance adjustment for NMOS and PMOS, respectively, to achieve for the NMOS and respectively, and the PMOS source and drain ion implantation process defects difficult to provide a method for preparing a mixed crystal SOI isolation double inversion mode back gate of SiNWFET.

[0010] 为了实现上述目的本发明提供一种制备双层SOI混合晶向后栅型反型模式SiNWFET的方法,包括以下顺序步骤: [0010] The present invention provides a method for double-gate SOI rearwardly mixed crystal inversion mode SiNWFET prepared, comprising the sequential steps to achieve the above object:

[0011] 步骤1:在SOI顶层先后形成SiGe层、Si层和SiGe层和SOI硅片上的沟道区N型尚子注入: [0011] Step 1: SiGe layer formed successively top SOI, Si and SiGe layers and N-type channel region of the SOI wafer Naoko injection:

[0012] 步骤2:对器件进行光刻工艺,刻蚀形成鳍形有源区,利用选择性刻蚀技术去除鳍形有源区中的SiGe层,形成SiNWFET沟道的硅纳米线; [0012] Step 2: the device is a photolithography process, forming a fin-shaped active region is etched, using a selective etching technique for removing the SiGe layer fin-shaped active region, forming a silicon nanowire SiNWFET channel;

[0013] 步骤3:在器件上沉积隔离介质层,采用化学机械研磨去除多余的隔离介质材料; [0013] Step 3: depositing a spacer dielectric layer on the device, chemical mechanical polishing to remove excess isolating dielectric material;

[0014] 步骤4:对下层PMOS进行源漏区离子注入和退火, [0014] Step 4: the lower layer for PMOS source and drain region ion implantation and annealing,

[0015] 步骤5:在SiNWFET沟道的硅纳米线上方的隔离介质层上进行光刻和选择性刻蚀形成栅极沟槽,所述栅极沟槽中暴露出硅纳米线; [0015] Step 5: photolithography and selectively etched to form a gate trench isolation dielectric layer on the silicon nanowires SiNWFET channel side of the gate trench exposes the silicon nanowires;

[0016] 步骤6:对器件进行栅极氧化层工艺;再在栅极氧化层淀积栅极材料,采用化学机械研磨去除多余的栅极材料,对器件进行金属、半导体合金工艺处理形成下层SiNW反型模式PM0SFET结构; [0016] Step 6: the device is a gate oxide process; re-depositing of gate material gate oxide layer using chemical mechanical polishing to remove excess gate material, the device is a metal, a semiconductor alloy underlayer formed Process SiNW PM0SFET structure inversion mode;

[0017] 步骤7:在器件上沉积下层PM0SFET的ILD层,在ILD层表面,Si键合片和下面已制备有(110)/〈110〉SiNW PM0SFET的支撑片低温键合处理,使得ILD层上形成一(110)表面晶向Si层; [0017] Step 7: depositing a lower layer PM0SFET ILD layer on the device, the surface of the ILD layer, Si bonding sheet and the following have been prepared with a (110) / <110> SiNW PM0SFET support piece low temperature bonding process, so that the ILD layer formed on a (110) surface of the Si crystal layer;

[0018] 步骤8:在上步骤形成的Si层上重复进行上述步骤I至6所述的步骤,形成上层SiNW反型模式NM0SFET结构,所述Si层选用P型离子进行沟道的离子掺杂; [0018] Step 8: repeating the step of forming a Si layer on the above-described step I to step 6, forming the upper structure NM0SFET SiNW inversion mode, the P-type Si layer selected ion channel ion doping ;

[0019] 步骤9:通过后道金属互连工艺引出下层PM0SFET和上层NM0SFET各端口。 [0019] Step 9: PM0SFET lower and upper lead NM0SFET through each port, after metal interconnection process.

[0020] 在本发明的一个优选实施例中,其中所述步骤I中包括在顶层硅表面外延一层表面晶向SiGe或Ge层,采用锗氧化浓缩法对晶圆进行氧化处理形成SiGe层,去除SiGe层上的SiO2层露出SiGe层。 [0020] In a preferred embodiment of the present invention, wherein said step I comprises the top silicon surface of the epitaxial layer to the surface of the crystal or Ge SiGe layer, the germanium oxide concentration method using the wafer is oxidized SiGe layer is formed, removing the SiO2 layer on the SiGe layer is exposed SiGe layer.

[0021] 在本发明的一个优选实施例中,其中所述去除鳍形有源区中的SiGe层采用次常压化学汽相法,用60(T800°C的H2和HCl混合气体进行选择性刻蚀,其中HCl的分压大于300 torrD [0021] In a preferred embodiment of the present invention, wherein the SiGe layer is removed fin-shaped active regions using sub-atmospheric chemical vapor phase method, with selective 60 (H2 and HCl in the mixed gas T800 ° C etching, wherein the partial pressure of HCl of 300 torrD

[0022] 在本发明的一个优选实施例中,其中所述SiNWFET沟道的硅纳米线的截面形状为圆形、横向跑道型或纵向跑道型。 [0022] In a preferred embodiment of the present invention, wherein the sectional shape of the silicon nanowires SiNWFET channel is circular, racetrack lateral or longitudinal racetrack.

[0023] 在本发明的一个优选实施例中,其中所述栅极氧化层工艺采用炉管氧化、快速氧化或原子层淀积技术,在SiNW和衬底及源漏区域表面形成SiO2或者SiON (加上氮气气氛)或者高k介质层(如Hf02、Al203、ZrO2或者其混合物等),或者它们的混合层。 [0023] In a preferred embodiment of the present invention, wherein the gate oxide layer using furnace oxidation process, rapid oxidation or atomic layer deposition techniques, SiON or SiO2 is formed on the substrate and the source and drain SiNW surface region ( plus nitrogen) or a high-k dielectric layer (e.g., Hf02, Al203, ZrO2 or a mixture thereof, etc.), or their mixed layer.

[0024] 在本发明的一个优选实施例中,其中所述栅极材料选用多晶硅、无定形硅、金属氧化物或其组合物,所述金属氧化物为铝或钛或钽的金属氧化物。 [0024] In a preferred embodiment of the present invention, wherein the material selection gate polycrystalline silicon, amorphous silicon, or a metal oxide composition, the metal oxide is aluminum or titanium or tantalum metal oxide.

[0025] 在本发明的一个优选实施例中,其中所述步骤8中个各步骤在低温环境下进行。 [0025] In a preferred embodiment of the present invention, wherein each step is carried out at a low temperature in the step 8.

[0026] 在本发明的一个优选实施例中,其中所述ILD层为SiO2层或微孔结构的含碳低k [0026] In a preferred embodiment of the present invention, wherein the ILD layer is a SiO2 layer or a low carbon micropore structure k

二氧化硅层。 Silicon dioxide layer.

[0027] 通过本发明提供的方法形成下层PM0SFET和上层NM0SFET结构的双层隔离混合晶向后栅型反型模式SiNWFET,所形成的双层隔离半导体纳米线MOSFET的第一半导体纳米线MOSFET与第二半导体纳米线MOSFET通过隔离介质层间隔,可以完全独立的进行工艺调试,且器件集成度高。 [0027] The first semiconductor nanowire and the second MOSFET semiconductor nanowires double isolated MOSFET forming the lower layer and the upper layer NM0SFET PM0SFET structure by the process of the present invention provides a double-gate isolation rearwardly mixed crystal inversion mode SiNWFET, the formed two MOSFET semiconductor nanowires spaced by isolation dielectric layer may be completely independent of the debugging process, and the device is highly integrated. 同时,本发明采用第一半导体纳米线MOSFET为PM0SFET,第二半导体纳米线MOSFET为NM0SFET的结构设计。 Meanwhile, the present invention is employed as a first semiconductor nanowire MOSFET PM0SFET, the second semiconductor nanowire MOSFET for the structural design of NM0SFET. 本发明中PM0SFET采用(110)表面晶向硅层,NM0SFET采用(100)表面晶向硅层。 PM0SFET employed in the present invention (110) crystal surface of the silicon layer, NM0SFET from (100) crystal surface of the silicon layer. 在低温剥离技术中,随着氢气的压力增大,裂缝更倾向于沿(100)晶向生长,因此沿(100)晶向更容易进行硅层剥离,方便了层转移工艺实现。 In the cryogenic lift-off technique, as the hydrogen pressure increases, cracks tend along the (100) crystal to grow, and therefore along the (100) crystal for the silicon layer peeled off more easily and conveniently achieve a layer transfer process.

附图说明 BRIEF DESCRIPTION

[0028] 图1 (a)为本发明双层隔离半导体纳米线MOSFET的俯视结构示意图。 [0028] FIG 1 double isolation structure diagram (a) of the present invention, a top view of a semiconductor nanowire MOSFET.

[0029] 图1 (b)所示为图1 (a)沿X-X'方向的剖视结构示意图。 [0029] FIG. 1 (b) (a) is a schematic cross-sectional view of the structure of FIG. 1 along X-X 'direction.

[0030] 图1 (C)所示为图1 (a)沿Y-Y'方向的剖视结构示意图。 [0030] FIG. 1 (C) (a) is a schematic structural diagram shown in FIG. 1 along the Y-Y 'direction cross-sectional view.

[0031] 图2为本发明双层隔离半导体纳米线MOSFET的立体结构示意图。 [0031] Figure 2 a perspective schematic structural view of a semiconductor nanowire double isolation MOSFET of the present invention.

[0032] 图3为本发明双层隔离半导体纳米线MOSFET经过后续半导体制备工艺所形成的完整场效应晶体管的立体结构示意图。 [0032] FIG. 3 is a schematic perspective structural diagram of a complete double isolation FET semiconductor nanowire MOSFET subsequent semiconductor manufacturing process through the formation of the present invention.

[0033] 图4为本发明形成双层SiGe层后的结构示意图。 [0033] FIG. 4 is a schematic structure of the SiGe layer to form a bilayer of the present invention.

[0034] 图5 (a)和图5 (b)分别为本发明刻蚀去除鳍形Si有源区中的SiGe层后的沿X-X'方向和Y-Y'方向的剖视结构示意图。 [0034] FIG. 5 (a) and 5 (b) are schematic cross-sectional view of the present invention, the structure is etched along X-X 'direction and in Y-Y' direction of the fin-shaped active region in the SiGe layer is removed Si .

[0035] 图6为本发明中SiNW截面示意图。 [0035] FIG. 6 a schematic sectional view of the present disclosure SiNW.

[0036] 图7 (a)和图7 (b)分别为本发明中淀积隔离介质层并去除多余隔离介材料后的沿X-X'方向和Y-Y'方向的剖视结构示意图。 [0036] FIG. 7 (a) and 7 (b) a schematic cross-sectional structure taken along X-X 'direction and in Y-Y' direction, the invention is deposited isolation dielectric layer and removing the excess dielectric isolation are examples of the material.

[0037] 图8为本发明中针对下层PMOS进行源漏区离子注入工艺示意图。 [0037] Figure 8 is for source and drain regions an ion implantation process of the invention in a schematic view for lower PMOS.

[0038] 图9 (a)和图9 (b)分别为本发明中形成栅极沟槽后下层硅纳米线的沿X_X'方向和Y-Y'方向的剖视结构示意图。 [0038] FIG. 9 (a) and 9 (b) a schematic cross-sectional structure taken along X_X 'direction and in Y-Y' direction after formation of the gate trenches invention underlying silicon nanowires are present.

[0039] 图10 (a)和图10 (b)分别为本发明中化学机械研磨去多余栅极材料后的沿X_X'方向和Y-Y'方向的剖视结构示意图。 [0039] FIG. 10 (a) and 10 (b) is a schematic view of a chemical mechanical polishing after the excess material along the gate X_X 'direction and in Y-Y' direction cross-sectional view of the structure of the present invention, respectively.

[0040] 图11为本发明中淀积下层PM0SFET的ILD层后的沿X_X'方向和Y_Y'方向的剖视结构示意图。 [0040] FIG 11 present a schematic cross-sectional structure after the deposition of the ILD layer of the invention along the lower PM0SFET X_X 'direction and Y_Y' direction.

[0041] 图12为本发明中Si键合片与制备有(110)/〈110〉SiNW PM0SFET支撑片低温键合的工艺示意图。 [0041] FIG. 12 is in the preparation of Si-bonded sheet has a (110) / <110> SiNW PM0SFET support sheet bonded to a low temperature process schematic of the present invention.

[0042] 图13为本发明中低温键合完成后的剖面结构示意图。 [0042] FIG. 13 is a schematic cross-sectional structure of the invention, the low-temperature bonding is completed.

[0043] 图14 (a)和图14 (b)分别为本发明中形成上层NM0SFET后的沿X_X'方向和Y_Y' 方向的剖视结构示意图。 [0043] FIG. 14 (a) and 14 (b) a schematic cross-sectional structure taken along X_X 'direction and Y_Y' direction after forming the upper NM0SFET invention are present.

具体实施方式 Detailed ways

[0044] 本发明提供一种双层SOI混合晶向后栅型反型模式SiNWFET制备方法。 [0044] The present invention provides a double layer SOI wafer back-gate inversion mode SiNWFET mixed preparation. 即上下两层MOSFET的沟道区是具有不同表面晶向的硅纳米线。 I.e. upper and lower layers of the channel region of the MOSFET is a silicon nanowire having a surface of different crystal orientations. 由于在低温剥离技术中,随着氢气压力的增加,裂缝更加倾向于沿着(100)晶向生长,因此沿(100)晶向更容易进行硅层剥离,故采用下层PM0SFET+上层NM0SFET模式,以方便层转移工艺实现。 Since the cryogenic lift-off technique, as the hydrogen pressure increases, more inclined to fracture along the (100) crystal to grow, and therefore along the (100) crystal for the silicon layer peeled off more easily, so the use of the lower top NM0SFET PM0SFET + mode to a layer transfer process to facilitate implementation.

[0045] 理论上讲,上下两层的SiNWFET可以采用任何表面晶向的娃纳米线,根据Yang M等人的研究成果,(100)/<110>的电子迁移率最大,(110)/<110>的空穴迁移率最大。 [0045] In theory, the upper and lower layers may be employed SiNWFET baby nanowires to any surface orientation, according to the research Yang M et al., (100) / <110> of the maximum electron mobility, (110) / < 110> hole mobility maximum. 因此,优选地,我们以(100)表面晶向的硅纳米线作为NM0SFET的沟道材料,并且NM0SFET的沟道方向为〈110〉,以(110)表面晶向的硅纳米线作为PM0SFET的沟道材料,并且PM0SFET的沟道方向为〈110〉。 Thus, preferably, We (100) crystal surface of the silicon nanowire as a channel material NM0SFET and NM0SFET channel direction is <110>, the (110) crystal surface of the silicon nanowire as a groove PM0SFET the channel material, and the channel PM0SFET direction is <110>.

[0046] 为详细说明本发明创造的技术内容、构造特征、所达成目的及功效,下面将结合实施例并配合附图予以详细说明。 [0046] The teachings of the present inventions described in detail, structural features, objects and reached effect, and with reference to examples below be described in detail with the accompanying drawings.

[0047] 采用顶层硅为(110)表面晶向硅层的SOI硅片,先进行顶层SiGe制备。 [0047] The top layer of silicon (110) crystal surface of silicon to the SOI silicon layer, SiGe top layer to be prepared. 在顶层硅表面外延一层(110)表面晶向的SiGe或者Ge层。 In the top surface of the epitaxial layer of silicon (110) surface crystal orientation layer of SiGe or Ge. 利用锗氧化浓缩法,在晶圆表面进行氧化处理,这时,Ge会向下浓缩到下面的Si层,使得Si层变为SiGe层,而上层为SiO2层,湿法去除表面的SiO2层,这样就使顶层硅转化为顶层锗硅。 Germanium oxide using a concentration method, oxidation treatment is performed on the wafer surface, then, Ge will be concentrated down to the underlying Si layer, the Si layer becomes such that the SiGe layer and the upper layer is a SiO2 layer, the SiO2 layer is removed a wet surface, This allows the top layer of the top silicon layer into silicon germanium. 再次,在顶层SiGe层上外延一层Si层和SiGe层,从而形成SiGe层、Si层和SiGe层的结构,结构如图4所示。 Again, on the top layer of the SiGe layer epitaxial Si layer and the SiGe layer, the SiGe layer to thereby form the structure, the Si layer and the SiGe layer, the structure shown in FIG. 在制备双层锗硅层的过程中,可在外延Si层时进行N型离子掺杂,也可以在形成双层锗硅层后进行N型离子掺杂。 In the preparation of the double layer of silicon germanium may be doped with N-type ions during epitaxial Si layer may be performed after the N-type ion-doped silicon-germanium layer to form a bilayer.

[0048] 对器件进行光学光刻或电子束光刻工艺,刻蚀形成鳍形有源区。 [0048] The device for optical lithography or electron beam lithography, etching to form the fin-shaped active region. 利用选择性刻蚀技术去除鳍形Si有源区中的SiGe层,例如采用60(T80(TC的H2和HCl混合气体,利用次常压化学气相刻蚀法进行选择性刻蚀,其中HCl的分压大于300 Torr。Y_Y'方向的Si有源区之间的SiGe层全部去除干净为止,使得Χ-Χ'方向的SiGe层部分保留(该区域为源、漏区),形成SiNWFET沟道的硅纳米线,结构如图5 (a)和(b)所示。热氧化工艺对鳍形有源区及衬底和源漏区域表面进行氧化,控制氧化时间,然后湿法工艺去除鳍形有源区及衬底和源漏区域表面的SiO2,这时鳍形有源区沿Y-Y'方向的截面图可能形成圆形、横向跑道型或纵向跑道型,横截面如图6所示,从而形成后续作为SiNWFET沟道的硅纳米线。 Using a selective etching technique for removing the SiGe layer fin Si active region, for example, using 60 (T80 (H2 and HCl gas mixture is TC, selective etching is performed using a sub-atmospheric chemical vapor etching, wherein the HCl partial pressure of greater than 300 Torr.Y_Y 'SiGe layer between the Si active area is clean to remove all directions, so that Χ-Χ' SiGe layer remained direction (the source region, a drain region), a channel is formed SiNWFET silicon nanowire, the structure in FIG. 5 (a) and (b), thermal oxidation process of the fin-shaped active region and the source and drain regions and the substrate surface is oxidized, oxidation time is controlled, then there is a wet process to remove the fin a source region and a surface of the substrate and the source and drain regions in SiO2, fin-shaped active region at this time may be a circular cross section along Y-Y 'direction, transverse or longitudinal runway racetrack type, the cross-section shown in Figure 6, thereby forming a silicon nanowire SiNWFET subsequent channel.

[0049] 如图7 (a)和(b)所示结构,在器件上沉积隔离介质层(如SiO2),采用化学机械研磨(CMP)去除多余的隔离介质材料。 [0049] FIG. 7 (a) and the structure shown in (B), is deposited isolation dielectric layer (e.g. SiO2) on the device, chemical mechanical polishing (CMP) to remove excess isolating dielectric material. 如图8所示,对下层PMOS进行源漏区离子注入和退火工艺。 Shown, the lower layer for PMOS source and drain region ion implantation and annealing process as shown in FIG 8. 在SiNWFET沟道的硅纳米线上方的隔离介质层上进行光刻和选择性刻蚀形成栅极沟槽,栅极沟槽中暴露出硅纳米线,如图9 Ca)和(b)硅纳米线的剖面示意图所示。 Progressive isolation dielectric layer in the channel silicon nanowires SiNWFET side lithography and selective etching to form the gate trench, the gate trench exposes the silicon nanowires, as shown in FIG 9 Ca) and (b) silicon nano diagram shown hatched.

[0050] 如图10 (a)和(b)所示,在对器件进行栅极氧化层工艺,如采用炉管氧化(FurnaceOxidation)、快速热氧化(RTO)、原子层沉积(ALD),在SiNW和衬底及源漏区域表面形成SiO2或者SiON (加上氮气气氛)或者高k介质层(如Hf02、A1203、ZrO2或者其混合物等),或者它们的混合层。 [0050] FIG. 10 (a) and (b), in the device is a gate oxide process, such as the use furnace oxidation (FurnaceOxidation), rapid thermal oxidation (the RTO), atomic layer deposition (ALD), in SiNW and the substrate and source-drain regions formed on the surface SiO2 or the SiON (nitrogen plus) or a high-k dielectric layer (e.g., Hf02, A1203, ZrO2 or a mixture thereof, etc.), or their mixed layer. 再在栅极氧化层上淀积栅极材料,可以为多晶硅、无定形硅、金属化合物(优选为铝或者钛或钽的金属化合物)或者其组合。 And then deposited on the gate oxide layer of gate material may be polysilicon, amorphous silicon, a metal compound (preferably aluminum or titanium or tantalum metal compound), or a combination thereof. 采用化学机械研磨去除多余的栅极材料。 Chemical mechanical polishing to remove excess gate material. 对器件进行金属、半导体合金工艺处理形成下层M0SFET,为(110)/〈110〉SiNW反型模式PMOSFET结构。 The device is a metal, a semiconductor alloy underlayer formed Process M0SFET, of (110) / <110> SiNW inversion mode PMOSFET structure.

[0051 ] 如图11所示,在器件上沉积下层PMOSFET的ILD层,可以为Si02层,为了减少上下器件层之间的电容偶合效应,也可以为具有微孔结构的含碳低k 二氧化硅层。 [0051] As shown, the carbon deposited on the device PMOSFET lower ILD layer, may be a Si02 layer, in order to reduce the capacitive coupling effect between the upper and lower layer of the device may be a microporous structure having a low k dioxide 11 silicon layer. 其中,为了保证层转移质量,必须保证下层ILD在CMP之后足够小的表面粗糙度,优选地,可以采用FACMP(Fixed Abrasive CMP),使得表面粗糖度小于10nm。 Wherein, in order to ensure the quality of the transfer layer, the lower layer must ensure that a sufficiently small surface roughness ILD after the CMP, preferably, may be employed FACMP (Fixed Abrasive CMP), so that the surface roughness is less than sugar 10nm.

[0052] 如图12所示,在ILD层表面,Si键合片和下面已制备有(110)/〈110〉SiNWPMOSFET的支撑片低温键合处理,使得ILD层上形成一(100)表面晶向Si层,该工艺具体过程见申请号为201210090253.3的中国专利,低温键合处理完成后的结构如图13所示。 [0052] 12, the surface of the ILD layer, Si bonding sheet and the following have been prepared (110) / <110> SiNWPMOSFET support piece low temperature bonding process, so as to form a (100) crystal surface layer on the ILD the Si layer, particularly during the process, see the Chinese application No. 201210090253.3 patent, the structure of the low-temperature bonding process is completed as shown in Fig.

[0053] 在形成的Si层上再次进行之前从形成SiGe层至金属、半导体合金工艺处理的过程,从而形成成上层SiNW反型模式NM0SFET结构。 [0053] from the Si layer is formed on the previously formed again SiGe layer to a metal, a semiconductor alloy Process process, to thereby form an upper structure NM0SFET SiNW inversion mode. 其中与之前步骤不同之处在于Si层选用P型离子进行沟道的离子掺杂。 And wherein prior to the step difference is that P-type Si layer selected ion channel ion doping.

[0054] 此外,由于下层PMOSFET已制备完成,为了不影响下层器件和金属、半导体合金的性能,后续上层NM0SFET制备过程中必须采用低温方法,一般要求< 400°C。 [0054] Further, since the lower layer PMOSFET been prepared, the order not to affect the device and the underlying metal, a semiconductor alloy properties, the subsequent preparation of the upper layer must be used NM0SFET cryogenic process generally requires <400 ° C. 在采用低温外延技术和锗氧化浓缩法,使得原来的硅层转化为锗硅层。 In the low-temperature epitaxial technique and germanium oxide concentration method, so the original silicon layer into a silicon germanium layer. 再低温外延一层Si层和SiGe层,为了尽量减少后续的热预算,在外延Si层时直接进行沟道P型离子掺杂,这样不需要后续再进行沟道离子注入工艺,形成结构如图14 (a)和(b)所示。 Then the low-temperature epitaxial Si layer and the SiGe layer layer, in order to minimize subsequent thermal budgets, the epitaxial Si layer is performed when the P-channel type direct ion doping, so that no subsequent further channel ion implantation process to form the structure of FIG. 14 (a) and (b) shown in FIG.

[0055] 形成上层反型模式NM0SFET结构后,通过后道金属互连工艺引出下层PMOSFET和上层NM0SFET各端口。 After [0055] forming an upper structure NM0SFET inversion mode, the lower lead each port NM0SFET PMOSFET and an upper metal interconnection process by the channel.

[0056] 请参阅图1 (a)、图1 (b)、图1 (C),图1 (a)所示为本发明方法形成的双层隔离半导体纳米线MOSFET的俯视结构示意图。 [0056] Please refer to FIG. 1 (a), a schematic top view of the structure of double isolating semiconductor nanowire MOSFET of FIG. 1 (b), FIG. 1 (C), FIG. 1 (a) method of the present invention is formed as shown. 图1 (b)所示为图1 (a)沿X-X'方向的剖视结构示意图。 FIG 1 (a) a schematic cross-sectional view of the structure of (b) shown in FIG. 1 along X-X 'direction. 图1 (c)所示为图1 (a)沿Y-Y'方向的剖视结构示意图。 FIG 1 (a) a schematic cross-sectional view of the structure (c) shown in FIG. 1 along the Y-Y 'direction. 所述双层隔离半导体纳米线MOSFET I包括半导体衬底10,第一半导体纳米线MOSFET 11,第二半导体纳米线MOSFET 12,设置在所述第一半导体纳米线MOSFET 11与所述第二半导体纳米线M0SFET12之间的隔离介质层13,设置在所述第一半导体纳米线MOSFET 11与所述半导体衬底10之间的埋氧层14,设置在所述第一半导体纳米线MOSFET 11的第一源极区110、第一漏极区111和第一栅极区112之间的第一绝缘介质层113,设置在所述第二半导体纳米线MOSFET 12的第二源极区120、第二漏极区121和第二栅极区122之间的第二绝缘介质层123,设置在介于所述隔离介质层13与所述埋氧层14之间并位于所述第一半导体纳米线MOSFET 11 一侧且与所述第一源极区110、第一漏极区111以及第一栅极区112相连的第三绝缘介质层114,与所述第三绝缘介质层114呈面向设置并与所述第二源极区120、第二漏极区121以及第二栅极 The double isolation semiconductor nanowire MOSFET I 10 includes a semiconductor substrate, a first semiconductor nanowire MOSFET 11, the second semiconductor nanowire MOSFET 12, disposed in the first semiconductor nanowire MOSFET 11 and the second semiconductor nano isolation dielectric layer between lines M0SFET12 13, disposed on the first semiconductor nanowire first MOSFET 11 and the buried oxide layer 10 between the semiconductor substrate 14, disposed on the first semiconductor nanowire MOSFET 11 is source region 110, a first drain region of the first insulating dielectric layer 111 between the gate and the first region 112 113, provided in the second source region 120 and the second semiconductor nanowire MOSFET 12, the second drain a second insulating dielectric layer 122 between the source region 121 and the second gate region 123, disposed between the spacer 13 and the dielectric layer 14 between the buried oxide layer and in the first semiconductor nanowire MOSFET 11 and side 110, the first drain region 111 and the third dielectric layer 114 is connected to a first gate region of the first source region 112, the third insulating layer 114 as a dielectric and is disposed facing the 121 and a second gate electrode 120, a second drain region of said second source region 122连接的第四绝缘介质层124,以及分别设置在所述隔离介质层13与所述第一源极区110、第一漏极区111和第一栅极区112之间的第一导电层115和分别设置在第二源极区120、第二漏极区121和第二栅极区122之异于所述隔离介质层13 —侧的第二导电层125。 The fourth insulating dielectric layer 122 is connected to 124, and 13 are respectively provided with the first source region, the first conductive layer 112 between the dielectric spacer layer 110 of the first drain region 111 and the first gate region 115 and 120 are provided, the second drain region 121 and the second gate region 122 of the isolation dielectric layer 13 is different from a second source region - of the second conductive layer 125 side.

[0057] 结合参阅图1 (a)、图1 (b)和图1 (C),图2所示为本发明双层隔离半导体纳米线MOSFET I的立体结构示意图。 [0057] Referring to FIG 1 (a), FIG. 1 (b) and 1 (C), FIG. 2 a perspective schematic structural view of a semiconductor nanowire double isolation MOSFET I of the present invention is shown. 第一半导体纳米线MOSFET 11进一步包括横向贯穿于所述第一栅极区112并设置在所述第一源极区110与所述第一漏极区111之间的第一半导体纳米线116,以及环包设置在所述第一半导体纳米线116外侧并介于所述第一半导体纳米线116与所述第一栅极区112之间的第一栅氧化层117。 The first semiconductor nanowire MOSFET 11 further comprises a transverse through to the first gate region 112 and disposed in the first source region 110 and the first semiconductor nanowire 111 between the first drain region 116, bag 116 and a ring disposed outside the first semiconductor nanowire and interposed between the first semiconductor nanowire 116 and the first gate oxide layer 112 between the first gate region 117. [0058] 本发明双层隔离半导体纳米线MOSFET I的第二半导体纳米线MOSFET 12进一步包括横向贯穿于所述第二栅极区122并设置在所述第二源极区120与所述第二漏极区121之间的第二半导体纳米线126,以及环包设置在所述第二半导体纳米线126外侧并介于所述第二半导体纳米线126与所述第二栅极区122之间的第二栅氧化层127。 [0058] The semiconductor nanowire double isolation MOSFET I of the present invention a second semiconductor nanowire MOSFET 12 further comprises transversely across said second gate region 122 and disposed in said second source region 120 and the second the second semiconductor nanowire 126 between the drain region 121, and a ring packet 126 disposed outside the second semiconductor nanowire 122 and between the second semiconductor nanowire 126 and the second gate region a second gate oxide layer 127. 所述第一半导体纳米线116与所述第二半导体纳米线126在空间上叠置,并具有圆形、横向跑道形或者纵向跑道型的截面结构。 The first semiconductor nanowire 116 126 spatially overlaps with the second semiconductor nanowire, and has a circular, racetrack-shaped transverse or longitudinal sectional structure of the racetrack.

[0059] 第一源极区110、第一漏极区111的垂直于所述第一半导体纳米线116的宽度大于第一半导体纳米线116的直径,所述第二源极区120、第二漏极区121的垂直于第二半导体纳米线126的宽度大于第二半导体纳米线126的直径,所以本发明双层隔离半导体纳米线MOSFET I俯视时呈中间细两端宽大的鳍形。 [0059] The first source region 110, drain region 111 of the first vertical to the width of the first semiconductor nanowire 116 is larger than the diameter of the first semiconductor nanowire 116 and the second source region 120, a second vertical drain region 121 is greater than the diameter of the second semiconductor nanowire 126 in the width of the second semiconductor nanowire 126, the present invention was wide and intermediate the ends of fin-shaped plan view fine double isolation semiconductor nanowire MOSFET I. 由于第一半导体纳米线MOSFET 11为PM0SFET,第二半导体纳米线MOSFET 12为NM0SFET,而本发明中PMOSFET采用(110)表面晶向硅层,NM0SFET采用(100)表面晶向硅层。 Since the first semiconductor nanowire MOSFET 11 is PM0SFET, the second MOSFET 12 as a semiconductor nanowire NM0SFET, PMOSFET employed in the present invention (110) crystal surface of the silicon layer, NM0SFET from (100) crystal surface of the silicon layer. 由于在低温剥离技术中,随着氢气压力的增加,裂缝更加倾向于沿着(100)晶向生长,因此沿(100)晶向更容易进行硅层剥离,故下层PMOSFET+上层NM0SFET模式可以方便层转移工艺实现。 Since the cryogenic lift-off technique, as the hydrogen pressure increases, more inclined to fracture along the (100) crystal to grow, and therefore along the (100) crystal for the silicon layer peeled off more easily, so the lower PMOSFET + NM0SFET upper layer pattern can be easily transfer process implementation.

[0060] 在第一源极区110、第一漏极区111和第一栅极区112之间设置第一绝缘介质层113以避免第一源极区110、第一漏极区111和第一栅极区112之间的相互干扰。 [0060] 110, a first insulating dielectric layer 113 disposed between the first source region 112 in the first drain region 111 and the first gate region 111 and 110 to prevent the first source drain region of the first region a mutual interference between the gate region 112. 在第二源极区120、第二漏极区121和第二栅极区122之间设置第二绝缘介质层123以避免第二源极区120、第二漏极区121和第二栅极区122之间的相互干扰。 In the second source region 120, a second dielectric layer 123 a second insulating region 121 and drain region between the second gate 122 to prevent the second source region 120, a second gate 121 and a second drain region mutual interference between regions 122. 在第一半导体纳米线MOSFET11与半导体衬底10之间设置埋氧层14,将所述第一半导体纳米线MOSFET 11与所述半导体衬底10隔离,有效的减少漏电流,从而提高器件性能。 Disposed in the first semiconductor nanowire 14 MOSFET11 buried oxide layer between the substrate 10 and the semiconductor, the first semiconductor nanowire MOSFET 11 isolated from the semiconductor substrate 10, effectively reducing the leakage current, thereby improving the device performance.

[0061] 图3所示为经过后续半导体制备工艺所形成的完整场效应晶体管的立体结构示意图。 [0061] FIG. 3 is a perspective structural integrity through manufacturing process of the field effect transistor formed in a semiconductor subsequent FIG. 第一半导体纳米线MOSFET 11可以通过第四绝缘介质层124将电极从第一导电层115引出,以分别形成第一源极118a、第一漏极118b和第一栅极119。 The first semiconductor nanowire electrode of MOSFET 11 can be drawn out from the first conductive layer 115, to form a first source electrode 118a, the first drain electrode 118b and the first gate 119, respectively, through the fourth dielectric layer 124. 所述第二半导体纳米线MOSFET 12可以通过位于第二源极区120、第二漏极区121和第二栅极区122上的第二导电层125将电极引出,以分别形成第二源极128a、第二漏极128b和第二栅极129。 The second semiconductor nanowire MOSFET 12 may be formed by a second source in the second source region 120, a second lead-out electrode 125 drain region 121 and the second conductive layer on the second gate region 122, electrode 128a, 128b of the second drain electrode 129 and the second gate.

[0062] 综上所述,本发明双层隔离半导体纳米线MOSFET的第一半导体纳米线MOSFET与第二半导体纳米线MOSFET通过隔离介质层间隔,可以完全独立的进行工艺调试,且器件集成度高。 The first semiconductor nanowire and the second semiconductor nanowire MOSFET [0062] In summary, the present invention is a double separator MOSFET semiconductor nanowire by a MOSFET isolation dielectric spacer layer, may be completely independent of the debugging process, and high integration devices . 同时,本发明采用第一半导体纳米线MOSFET为PM0SFET,第二半导体纳米线MOSFET为NM0SFET的结构设计可以方便层转移工艺实现,并适用于前沿纳米器件技术领域。 Meanwhile, the present invention is employed as a first semiconductor nanowire MOSFET PM0SFET, the second MOSFET is a semiconductor nanowire design NM0SFET layer transfer process can be advantageously realized, and is applicable to cutting-edge technology nanodevices.

[0063] 以上对本发明的具体实施例进行了详细描述,但其只是作为范例,本发明并不限制于以上描述的具体实施例。 [0063] The foregoing specific embodiments of the present invention has been described in detail, but just as an example, the present invention is not limited to the specific embodiments described above. 对于本领域技术人员而言,任何对本发明进行的等同修改和替代也都在本发明的范畴之中。 To those skilled in the art, any equivalent modifications and alternatives to the present invention are also in the scope of the invention. 因此,在不脱离本发明的精神和范围下所作的均等变换和修改,都应涵盖在本发明的范围内。 Thus, variations and modifications made to uniformly without departing from the spirit and scope of the present invention, shall fall within the scope of the present invention.

Claims (8)

1.一种制备双层SOI混合晶向后栅型反型模式SiNWFET的方法,其特征在于,包括以下顺序步骤: 步骤1:在SOI顶层先后形成SiGe层、Si层和SiGe层和SOI硅片上的沟道区N型离子注入: 步骤2:对器件进行光刻工艺,刻蚀形成鳍形有源区,去除鳍形有源区中的SiGe层,形成SiNWFET沟道的硅纳米线; 步骤3:在器件上沉积隔离介质层; 步骤4:对下层PMOS进行源漏区离子注入和退火, 步骤5:在SiNWFET沟道的硅纳米线上方的隔离介质层上进行光刻和选择性刻蚀形成栅极沟槽,所述栅极沟槽中暴露出硅纳米线; 步骤6:在对器件进行栅极氧化层工艺,在SiNW和衬底及源漏区域表面形成SiO2或SiON或者高k介质层或其混合层;再在栅极氧化层淀积栅极材料,对器件进行金属、半导体合金工艺处理形成下层SiNW反型模式PM0SFET结构; 步骤7:在器件上沉积下层PM0SFET的ILD层,在ILD层表面,Si键合片和下 A mixed crystal back-gate inversion mode SiNWFET double SOI process preparation, characterized by comprising the following sequential steps: Step 1: has formed in the SOI layer top SiGe, Si and SiGe layers and the SOI wafer the channel region on the N-type ion implantation: step 2: the device is a photolithography process, forming a fin-shaped active region is etched, removing the SiGe layer fin-shaped active region, forming a silicon nanowire SiNWFET channel; step 3: depositing a spacer dielectric layer on the device; step 4: the lower layer for ion implantation and annealing PMOS source and drain regions, step 5: photolithography and selective etching a trench isolation dielectric layer in the silicon nanowires SiNWFET side forming a gate trench, said gate trench to expose the silicon nanowires; step 6: the device is in the process of gate oxide layer, an SiO2 or SiON or a high-k dielectric in the substrate and the source and drain SiNW surface area layer or a mixed layer; re-depositing the gate oxide layer of gate material, the device is a metal, a semiconductor alloy underlayer formed process SiNW inversion mode PM0SFET structure; step 7: depositing a lower layer PM0SFET ILD layer on the device, the ILD surface layer, Si-bonded plate and the lower 已制备有(110)/〈110>SiNW PM0SFET的支撑片低温键合处理,使得ILD层上形成一(100)表面晶向Si层; 步骤8:在上步骤形成的Si层上重复进行上述步骤I至6所述的步骤,采用低温方法形成上层SiNW反型模式NM0SFET结构,所述Si层选用P型离子进行沟道的离子掺杂; 步骤9:通过后道金属互连工艺引出下层PM0SFET和上层NM0SFET各端口。 Have been prepared with a (110) / <110> SiNW PM0SFET support piece low temperature bonding process, so as to form a (100) surface crystal orientation of Si layer on the ILD layer; Step 8: Repeat the above steps on the Si layer on the step formed I to step 6, the upper layer is formed using the low temperatures SiNW inversion mode NM0SFET structure, the P-type Si layer is chosen for the channel ion doping ions; step 9: after passage through the extraction PM0SFET lower metal interconnect process and upper NM0SFET each port.
2.根据权利要求1所述的方法,其特征在于,所述步骤I中包括在顶层硅表面外延一层(110)表面晶向SiGe或Ge层,采用锗氧化浓缩法对晶圆进行氧化处理形成SiGe层,去除SiGe层上的SiO2层露出SiGe层。 2. The method according to claim 1, wherein said step I comprises the top surface of the epitaxial layer of silicon (110) surface crystal orientation layer of SiGe or Ge, germanium oxide condensation method the wafer is oxidized SiGe layer is formed, removing the SiO2 layer on the SiGe layer is exposed SiGe layer.
3.根据权利要求1所述的方法,其特征在于,所述去除鳍形有源区中的SiGe层采用次常压化学汽相法,用600〜800°C的H2和HCl混合气体进行选择性刻蚀,其中HCl的分压大于300torr。 3. The method according to claim 1, wherein said SiGe layer is removed fin-shaped active regions using sub-atmospheric chemical vapor phase method, using a mixed gas of H2 and HCl are selected 600~800 ° C of etching, wherein the partial pressure of HCl 300torr.
4.根据权利要求1所述的方法,其特征在于,所述SiNWFET沟道的硅纳米线的截面形状为圆形、横向跑道型或纵向跑道型。 4. The method according to claim 1, characterized in that the cross-sectional shape of the silicon nanowires SiNWFET channel is circular, racetrack lateral or longitudinal racetrack.
5.根据权利要求1所述的方法,其特征在于,所述栅极氧化层工艺采用炉管氧化、快速氧化或原子层淀积技术。 5. The method according to claim 1, wherein said gate oxide layer using furnace oxidation process, rapid oxidation or atomic layer deposition techniques.
6.根据权利要求5所述的方法,其特征在于,所述高k介质层为Hf02、A1203、ZrO2或其混合物材质。 6. The method as claimed in claim 5, wherein said high-k dielectric layer is Hf02, A1203, ZrO2 materials, or mixtures thereof.
7.根据权利要求1所述的方法,其特征在于,所述栅极材料选用多晶硅、无定形硅、金属氧化物或其组合物,所述金属氧化物为铝或钛或钽的金属氧化物。 7. The method according to claim 1, wherein said gate material selection polycrystalline silicon, amorphous silicon, or a metal oxide composition, the metal oxide is aluminum or titanium or tantalum metal oxide .
8.根据权利要求1所述的方法,其特征在于,所述ILD层为SiO2层或微孔结构的含碳低k 二氧化硅层。 8. The method according to claim 1, wherein the ILD layer is a SiO2 layer or a carbon-containing low k silicon oxide layer of the microporous structure.
CN 201210136020 2012-05-04 2012-05-04 Method for preparing double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor) CN102709245B (en)

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