CN104282558A - Knot-free nanowire FinFET and manufacturing method thereof - Google Patents

Knot-free nanowire FinFET and manufacturing method thereof Download PDF

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CN104282558A
CN104282558A CN201310275445.6A CN201310275445A CN104282558A CN 104282558 A CN104282558 A CN 104282558A CN 201310275445 A CN201310275445 A CN 201310275445A CN 104282558 A CN104282558 A CN 104282558A
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semiconductor substrate
fin structure
requested
epitaxial loayer
layer
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CN104282558B (en
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黄新运
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

Abstract

The invention relates to a knot-free nanowire FinFET semiconductor device and a manufacturing method thereof. The method comprises the steps that a semiconductor substrate is provided, and an epitaxial layer is formed on the semiconductor substrate; the epitaxial layer and a part of the semiconductor substrate are patterned to form a fin structure and a nanowire structure on the fin structure; gate structures are formed on the fin structure and the nanowire structure. According to the knot-free nanowire FinFET semiconductor device, the knot-free nanowire FinFET semiconductor device has large currents in a turned-on state and has small currents in a turned-off state, performance of the device is greatly improved compared with a FinFET, the device has a larger on-off ratio compared with a planar device, and the whole technological process can be completely compatible with the existing process. Moreover, the manufacturing method of the transistor is suitable for a small-size semiconductor substrate, the transistor is lower than a nanowire cylindrical grid-full-surrounding knot-free field effect transistor in manufacturing cost, the manufacturing process of the transistor is simpler, and the process cost is lowered.

Description

A kind of without junction nanowire FinFET and preparation method thereof
Technical field
The present invention relates to semiconductor fabrication process, particularly, the present invention relates to a kind of by FinFET (FinFET) and semiconductor device of combining without junction nanowire field-effect transistor and preparation method thereof.
Background technology
The device development of a small amount of interconnection that integrated circuit (IC) has made from single silicon becomes millions of device.Current I C provides and far exceedes former conceptive performance and complexity.In order to realize the improvement of complexity and current densities (namely can be packaged into the device count on given chip area), the size of minimum device feature, also referred to as device " geometry ", become less along with each generation IC.Be less than the feature of 1/4th microns to make semiconductor device with span now.
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.At present, because in pursuit high device density, high-performance and low cost, semi-conductor industry has advanced to nanometer technology process node, the preparation of semiconductor device receives the restriction of various physics limit.
Along with the challenge constantly reduced from manufacture and design aspect of cmos device impels three dimensional design as the development of FinFET (FinFET).Relative to existing planar transistor, described FinFET has more superior performance in raceway groove control and reduction shallow channel effect etc.; Planar gate is arranged at above described raceway groove, and described in FinFET, gate loop is arranged around described fin, therefore can control electrostatic from three faces, and the performance in electrostatic control is also more outstanding.
In prior art, the formation method of FinFET as shown in figs. ia-1 c, and in Figures IA-1 C, Figure 1A and Fig. 1 C is the schematic diagram along YY ˊ direction, and Figure 1B is the schematic diagram in X1X1 ˊ direction, shown in wherein said YY ˊ, X1X1 ˊ direction figure as little in the upper right corner.As seen in figs. 1 a-1b, first in described Semiconductor substrate 100, trap 101 is formed, as shown in Figure 1A, then on described trap, form semiconductor material layer 102, described in patterning, semiconductor material layer obtains fin pattern, described fin pattern forms grid structure, as shown in Figure 1B, then form clearance wall, carry out ion implantation, finally form electrical connection, in order to improve the performance of device further, in FinFET, introduce high-K metal gate electrode structure.As shown in Figure 1 C, be the structural representation of FinTFET device, FinTFET device comprises: Semiconductor substrate 100; Be arranged in the trap 101 of described Semiconductor substrate 100; Be positioned at the fin 102 on described trap; Around the grid structure 103 of described fin; Be positioned at the shallow doped source doped region different from described trap doping type of described grid structure both sides and shallow doped-drain doped region; Be arranged in the described shallow doped source doped region raised source 105 identical with the doping type of shallow doped-drain doped region and lifting drain electrode 104.Wherein, relative to the high-K metal gate electrode structure of plane, FinFET performance is more superior, can improve 10-20%, but along with the progress with technology of reducing of device, it is far from being enough that the performance of 10-20% improves.
FinFET can not meet the needs of device development, constantly reducing facing new challenges property of feature sizes of semiconductor devices, because the various techniques used in production of integrated circuits may have certain restriction.That is, given technique only works to down to certain characteristic size usually, so need the layout changing technique or device.
The nano wire cylinder all-around-gate developed at present can solve prior art institute facing challenges without junction field effect transistor (GAAC JLFET), such as, and the larger problem such as doping content gradient, low heat budget.Nano wire all-around-gate has larger on-off ratio (larger on-off ratio) without junction field effect transistor compared with traditional three grid (tri-gate) effect transistor.But, all-around-gate without the cost of manufacture of junction field effect transistor far away higher than the cost of manufacture of traditional grid fin-shaped field effect transistor.
Therefore, propose and nano wire cylinder all-around-gate is applied in multiple-grid fin-shaped field effect transistor without junction field effect transistor structure, to reduce the improvement of problem device performance of traditional multiple-grid fin-shaped field effect transistor and scaled ability, reduce the cost of manufacture of device.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to effectively solve the problem, the present invention proposes a kind of manufacture method without junction nanowire FinFET, comprising: Semiconductor substrate is provided; Form epitaxial loayer on the semiconductor substrate; Epitaxial loayer described in patterning and the described Semiconductor substrate of part, to form fin structure and to be positioned at the nano thread structure on described fin structure; Described fin structure and described nano thread structure form grid structure.
Preferably, the material of described epitaxial loayer is SiGe or SiC.
Preferably, described epitaxy layer thickness is 5-10nm.
Preferably, the width of described fin structure is less than 8nm.
Preferably, the doping type of described epitaxial loayer is different from the doping type of described fin structure.
Preferably, in-situ doped technique or shallow link doping process is adopted to form described epitaxial loayer.
Preferably, in described Semiconductor substrate, trap is formed with.
Preferably, described Semiconductor substrate is Si.
Preferably, described grid structure is high-K metal gate electrode structure.
Preferably, described method be also included in formed to be formed in the Semiconductor substrate of described fin structure both sides before described grid structure shallow trench isolation from step.
Preferably, after the described grid structure of formation, described method is further comprising the steps of: perform LDD ion implantation; The sidewall of described grid structure is formed the first clearance wall; Epitaxial growth first semiconductor material layer is to form lifting source and drain; Described first clearance wall forms the second clearance wall; Perform ion implantation, form source-drain area in described grid structure both sides and carry out short annealing; Described source-drain area forms silicide layer, then forms electrical connection.
Preferably, described first semiconductor material layer is Si, SiGe or SiC material layer.
Preferably, the method for epitaxial loayer described in patterning and the described Semiconductor substrate of part comprises: form patterned photo glue-line on said epitaxial layer there, to define the pattern of described fin structure and described nano thread structure; With described photoresist layer for epitaxial loayer described in mask etch and the described Semiconductor substrate of part, form described fin structure and be positioned at the described nano thread structure on described fin structure; Remove described photoresist layer.
Preferably, the doping type of described epitaxial loayer is identical with the doping type of described source-drain area.
The invention allows for a kind of without junction nanowire FinFET semiconductor device, comprising: Semiconductor substrate; The nano thread structure being positioned at the fin structure in described Semiconductor substrate and being positioned on described fin structure; Around the grid structure of described fin structure and described nano thread structure.
Preferably, the material of described nano thread structure is SiGe or SiC.
Preferably, described grid structure is high-K metal gate electrode structure.
Preferably, the doping type of described nano thread structure is different from the doping type of described fin structure.
In semiconductor device of the present invention and manufacture method, the problems such as the high-dopant concentration gradient that transistor has in prior art and low heat budget, will combine without junction nanowire transistor AND gate FinFET and be formed without junction nanowire FinFET in preparation process.Transistor formed according to the present invention, when device is in open mode, there is larger electric current, when device is in off-state, there is less electric current, relative and FinFET performance is greatly improved, relative to planar device, also there is larger on-off ratio (larger on-off ratio), whole technical process and existing technique completely compatible, and the preparation method of this transistor is applicable to undersized Semiconductor substrate, its cost of manufacture is lower than the cost of manufacture of nano wire cylinder all-around-gate without junction field effect transistor (GAAC JLFET), therefore the manufacturing process of this transistor is simpler, reduce process costs simultaneously.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1C is the process generalized section preparing FinTFET according to prior art;
Fig. 2 A-2C is the process generalized section preparing N-type FinTFET according to an embodiment of the invention;
Fig. 3 A-3C is the process generalized section preparing P type FinTFET according to another implementation of the invention;
Fig. 4 is the process chart preparing FinTFET according to another implementation of the invention
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, with illustrate of the present invention improve thin film deposition time grain defect method.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
In the present invention in order to solve the defect existed in prior art, merge without the preparation technology of junction nanowire transistor (junction less nanowire transistors) with FinFET (FinFET) in the present invention, in the technique of FinFET (FinFET), preparation is without junction nanowire layer, obtain without junction nanowire field-effect transistor, by described method to solve the drawback existed in prior art.
Be described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing 2A-2C and Fig. 3 A-3C, wherein Fig. 2 A-2C is preparation N-type FinTFET preparation process generalized section; Fig. 3 A-3C is preparation P type FinTFET preparation process generalized section.In Fig. 2 A-2C and Fig. 3 A-3C, Fig. 2 A, Fig. 2 C, Fig. 3 A and Fig. 3 C are the schematic diagram along YY ˊ direction, and Fig. 2 B and Fig. 3 B is the schematic diagram in X1X1 ˊ direction, shown in wherein said YY ˊ, X1X1 ˊ direction figure as little in the upper right corner.
The present invention, in order to overcome problems of the prior art, provides a kind of preparation method without junction nanowire FinFET semiconductor device, comprising:
Semiconductor substrate is provided;
Deposition forms epitaxial loayer on the semiconductor substrate;
Epitaxial loayer described in patterning and described Semiconductor substrate, to form fin structure and to be positioned at the nano thread structure on described fin structure;
Described fin structure and nano thread structure form grid structure.
Be described in detail the preparation method of semiconductor device of the present invention below in conjunction with Fig. 2 A-2C, described in the embodiment of the invention, semiconductor device can be that N-type is without junction nanowire FinFET.
As shown in Figure 2 A, provide Semiconductor substrate 200, in the substrate 200 of described semiconductor, be formed with trap 201;
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In addition, Semiconductor substrate can be defined active area.
Trap 201 is formed in described Semiconductor substrate, described in an embodiment of the present invention, substrate selects N-type substrate, particularly, the N-type substrate that those skilled in the art select this area conventional, then in described N-type substrate, form P trap, in an embodiment of the present invention, first in described N-type substrate, form P trap window, in described P trap window, carry out ion implantation, then perform annealing steps and advance to form P trap.
As preferably, described Semiconductor substrate 200 is the thickness of Si material layer is 10-100nm, is preferably 30-50nm.
In described Semiconductor substrate 200, growth forms epitaxial loayer 202, and its material can be SiGe or SiC.As preferably, the material of epitaxial loayer 202 is SiGe, be 1-50nm at the thickness of of the present invention one epitaxial loayer 202 described in execution mode particularly, be preferably 5-10nm, described Si material layer 200 and described epitaxial loayer 202 but be not limited to described number range, above-mentioned scope is only exemplary, and those skilled in the art can select as required.As preferably, in described sige material layer, the content of Ge is 15% weight portion-45% weight portion.
Described epitaxial loayer 202 can select in-situ doped (in-situ doping) or an ultra shallow to link doping (ultra-shallow junction doping) technique.In an embodiment of the present invention, in-situ doped method is selected to form described sige material layer 202, particularly, when adopting chemical gaseous phase depositing process or gas source molecular beam epitaxy method growth N-type silicon, with silane or disilane as silicon source, with phosphine as N-type impurity gas, add a certain amount of germane simultaneously.Such as, GeH is selected 4and SiH 2cl 2as reacting gas, and select H 2as carrier gas, the flow-rate ratio of wherein reacting gas and carrier gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, and be preferably 650-750 DEG C, gas pressure is 1-50torr, is preferably 20-40Torr.
In one embodiment of this invention, utilize growth technology, at 1000-1600 DEG C of temperature, form epitaxial growth SiC on a semiconductor substrate, in epitaxial growth, used source gas is SiH 4and C 3h 8, in epitaxial process, pass into H 2, N 2as carrier gas, realize the in-situ doped of N-shaped, typical growth temperature is 1500 ~ 1600 DEG C simultaneously, then further annealing at 1600 ~ 1700 DEG C.
Then, described Semiconductor substrate 200 forms fin structure and is positioned at the nano thread structure on fin structure, as shown in Figure 2 B, the formation method of described device architecture is the mask layer forming patterning on described epitaxial loayer 202, such as photoresist mask layer, described photoresist mask layer defines the width of described fin structure and nano thread structure, length and position etc., then with described photoresist mask layer for Semiconductor substrate described in mask etch 200 and epitaxial loayer 202, form fin structure 203 and nano thread structure 204 on the semiconductor substrate, wherein nano thread structure 204 is the top that epitaxial loayer 202 is formed in fin structure after etching, then described photoresist mask layer is removed, the method removing described photoresist mask layer can be oxidative ashing method.It should be noted that the formation of described fin structure and nano thread structure is only exemplary, be not limited to the method.
In an embodiment of the present invention, with described graphical photoresist layer for mask, passing into CF 4and CHF 3etching condition under, the described Semiconductor substrate 200 of part and epitaxial loayer 202 are etched, described etching pressure: 50-150mTorr in this step; Power: 300-800W; Time: 5-15s; Wherein gas flow: CF 4, 10-30sccm; CHF 3, 10-30sccm, it should be noted that above-mentioned engraving method is only exemplary, does not limit to and the method, and those skilled in the art can also select other conventional methods.
In of the present invention one particularly execution mode, Si is deposited on the semiconductor substrate as preferred implementation, light dope can also be carried out while deposition Si, carry out the doping of P type, doping type is not identical with the type of doping in source/drain region in subsequent technique, and then forming fin further, described fin is P type fin, and the light dope type of fin is identical with the doping type of trap.As an example, adulterate to epitaxial loayer, to obtain all even highly doped epitaxial loayer, carry out N-type doping, its doping type is different from the doping type of fin structure or silicon substrate, but it is identical with the doping type of follow-up source/drain regions.
Then isolation structure 205 is formed on the semiconductor substrate, such as on the semiconductor substrate formed shallow trench isolation from or localised oxide layer, in an embodiment of the present invention, be preferably formed fleet plough groove isolation structure, described shallow trench isolation from formation method can to select in prior art conventional method, such as first, deposited oxide layer on semiconductor substrate 200, then oxide skin(coating) described in etch-back, forms the fleet plough groove isolation structure of top lower than described fin.
Then on described fin structure, grid structure 206 is formed, described grid structure 206 is around described fin structure and nano thread structure, form all around gate structure 206, described fin structure and nano thread structure are positioned under described grid structure, after the described all around gate structure 206 of formation, described nano thread structure is as raceway groove, described all around gate structure 206, relative to existing planar transistor, has more superior performance in raceway groove control and reduction shallow channel effect etc.; Planar gate is arranged at above described raceway groove, and described in FinFET, gate loop is arranged around described fin, therefore can control electrostatic from three faces, and the performance in electrostatic control is also more outstanding.Simultaneously, without junction nanowire FinFET, there is narrower fin structure, in of the present invention one particularly execution mode, the width critical size of described fin structure is less than 8nm, finds out that without junction nanowire layer be depletion layer when being in off status without junction nanowire FinFET from the energy band diagram of FinFET.
In of the present invention one particularly execution mode, described grid structure 206 is polysilicon gate construction, first the formation method of described polysilicon gate construction for form dielectric layer on described fin structure and nano thread structure, form gate oxide on the dielectric layer, as preferably, the material of described gate oxide is silicon dioxide, and the mode of thermal oxidation can be adopted to be formed.
Be preferably formed polysilicon gate construction in the present invention, the formation method of polysilicon layer can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Then patterning is carried out, to form polysilicon gate construction 206 on described fin structure and nano thread structure, described patterning method is the photoresist layer first forming patterning, with described photoresist layer for polysilicon layer described in mask etch and gate oxide, described photoresist layer is removed in last ashing, but the patterning method of described polysilicon gate construction is not limited to above-mentioned example.
As preferably, in order to improve the performance of described device further, described grid structure 206 is metal gate structure or high-K metal gate electrode structure, in an embodiment of the present invention, the formation method of described metal gate structure is first at fin structure with without junction nanowire structure being formed polysilicon gate construction, it is as dummy gate, then described dummy gate is removed to form groove, U-shaped gate dielectric is formed in the bottom of described groove and sidewall, as preferably, described gate dielectric is that includes high-k dielectric is to form described gate dielectric, such as be used in HfO 2middlely introduce the element such as Si, Al, N, La, Ta and the hafnium etc. that obtains of the ratio optimizing each element.The method forming described includes high-k dielectric can be physical gas-phase deposition or atom layer deposition process.Then, in the trench described gate dielectric is filled multiple film stack and formed, described film comprises workfunction layers, barrier layer and conductive layer.Described barrier layer comprises TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or above-mentioned combination.Described deposit barrier layer method limiting examples comprises chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).Final formation high-k/metal gate electrode structure.Etching removes dummy gate to form metal gate structure is for a person skilled in the art that the common technology means of this area are not just discussed one by one in detail at this.
LDD ion implantation is performed, to form lightly doped region in the both sides of described grid structure.The method of described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will be formed, and the device namely formed is nmos device, then the foreign ion mixed in LDD injection technology is one in phosphorus, arsenic, antimony, bismuth or combination; The device formed in an embodiment of the present invention is PMOS device, and the foreign ion of injection is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.Or can not perform LDD ion implantation technology and directly perform manufacture craft below, LDD doping process not necessarily.
After completing described ion implantation, can be subjected to displacement with the atomic collision in semiconductor lattice, lattice atoms to eliminate high-octane incident ion, cause a large amount of rooms, described device is annealed at a certain temperature, to recover the structure of crystal and to eliminate defect.The temperature of annealing is 200-800 DEG C.
Described grid structure 206 forms the first clearance wall, described first clearance wall, the material of described first clearance wall is such as silicon nitride, the insulating material such as silica or silicon oxynitride.Along with diminishing further of device size, the channel length of device is more and more less, the particle of source-drain electrode injects that the degree of depth is also more and more less, and the effect of the first clearance wall is the channel length of the transistor improving formation, the hot carrier's effect reducing short-channel effect and cause due to short-channel effect.Form the technique such as chemical vapour deposition (CVD) of the first clearance wall in grid structure 206 both sides, in the present embodiment, the thickness of described first clearance wall may diminish to 80 dusts.
Further epitaxial growth first semiconductor material layer on described Si material layer 200, as preferably, described first semiconductor material layer is Si, SiGe or SiC material layer, to form lifting source and drain 207a, 207b in the both sides of described grid structure 206, as shown in Figure 2, described Si material layer is the Si of undoped, its thickness is 10-30nm, be preferably 20nm, in an embodiment of the present invention, the epitaxy method of described Si material layer is: by hydrogen (H 2) gas carries silicon tetrachloride (SiCl 4) or trichlorosilane (SiHCl 3), silane (SiH 4) or dichloro hydrogen silicon (SiH 2cl 2) etc. enter the reative cell being equipped with silicon substrate, carry out high-temperature chemical reaction at reative cell, make siliceous reacting gas reduce or thermal decomposition, the silicon atom produced is at substrate silicon surface Epitaxial growth.The highly diluted ratio of 98.5% can be selected in this step, the temperature of reaction is 1500-1800 DEG C, and to control air pressure be about 1pa, the substrate Epitaxial growth that can be 200 DEG C in temperature obtains the silicon thin film of 200nm or more, can also regulate temperature in this step, the time controls silicon thin film.
Described first clearance wall is formed the second clearance wall (spacer); Described second clearance wall can be a kind of in silica, silicon nitride, silicon oxynitride or their combinations are formed.As an optimal enforcement mode of the present embodiment, described second clearance wall is silica, silicon nitride forms jointly, concrete technology is: form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer on a semiconductor substrate, then adopts engraving method to form clearance wall.
Grid structure 206 is formed the second clearance wall.Described second clearance wall, comprises nitride, oxynitride or their combination, by depositing and etching formation.Described second clearance wall structure can have different thickness, but measures from basal surface, and the thickness of described second clearance wall structure is generally 10nm to 30nm.
Described second clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.It should be noted that, clearance wall structure is optional and nonessential, its be mainly used in follow-up carry out etching or ion implantation time grill-protected electrode structure 206 sidewall injury-free.
As preferably, after the described grid structure 206 of formation, the step that grid both sides form source-drain area 208a, 208b can also be included in further, particularly, described source-drain area can be formed by the method for ion implantation or diffusion, as further preferably, after carrying out ion implantation or diffusion, can further include the step of a thermal annealing.
Described annealing steps is generally under described substrate is placed in the protection of high vacuum or high-purity gas; be heated to certain temperature and carry out RTA (RTA) technique; nitrogen or inert gas is preferably at high-purity gas of the present invention; the temperature of described rapid thermal annealing process step is 800-1200 DEG C; be preferably 1050 DEG C, the described thermal anneal step time is 1-300s.As further preferred, the rapid thermal annealing selected in the present invention, the one in following several mode can be selected: pulse laser short annealing, the short annealing of the Pulse Electric philosophical works, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc., but be not limited to examples cited.
Last formation in described lifting source and drain is electrically connected, deposits conductive material in lifting source and drain, then planarization, for electrical connection, electric conducting material is formed by the deposition technique of low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or other advanced person.Preferably, electric conducting material is tungsten material.In another embodiment, electric conducting material can be cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the electric conducting material containing tungsten or its combination.
As preferably, in one embodiment, in order to reduce contact resistance, the silicification technics (silicidation) forming silicide layer was also comprised further before filling described electric conducting material, particularly, at semiconductor substrate surface sputtered metal layer, such as nickel metal layer, then RTA (RTA) technique is carried out, the partial reaction that metal level is contacted with grid and regions and source/drain becomes metal silicide layer, completes silicification technics (silicidation).
The formation of metal silication layer region, first depositing metal layers, it can comprise the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or its combination.Then heated substrate, cause metal level and the silicon layer generation silicification under it, thus metal silication layer region is formed.Then erodable metal level is used, but the etchant in unlikely attack metal disilicide layer region, so that unreacted metal level is removed.As shown in Figure 2 C, the structural representation without junction nanowire FinTFET device for being formed
In addition, Fig. 3 A-3C describes and forms the process schematic of P type without junction nanowire FinTFET, in this forming process, N trap is formed in described P type substrate, described P type substrate forms epitaxial loayer, and its material is SiGe or SiC, according to mask layer etching epitaxial loayer and Semiconductor substrate to form fin structure and nano thread structure, described fin structure and nano wire form grid structure, the sidewall of described grid structure is formed the first clearance wall; Epitaxial growth first semiconductor material layer is to form lifting source and drain; Described first clearance wall forms the second clearance wall; Form P type light dope in described drain region, described source region forms the doping of P type, then anneals, described source-drain area forms silicide layer, then forms electrical connection.Its concrete formation method with reference to the formation method of N-type without junction nanowire FinTFET, can not repeat them here.In order to distinguish with Fig. 2, in figure 3 described numbering is adjusted, Semiconductor substrate 300 specific as follows, trap 301, epitaxial loayer 302, fin structure 303, nano thread structure 304, shallow trench isolation from 305, grid structure 306, source electrode 308a and drain electrode 308b, lifting drain electrode 307b and raised source 307a.
Fig. 4 is the preparation method of semiconductor device described in embodiment of the invention flow chart, comprises the following steps particularly:
Step 401 provides Semiconductor substrate;
Step 402 is shape epitaxial loayer on the semiconductor substrate;
Epitaxial loayer described in step 403 patterning and described Semiconductor substrate, to form fin structure and without junction nanowire structure;
Step 404 formed on the semiconductor substrate shallow trench isolation from;
Step 405 forms grid structure at described fin structure with without in junction nanowire structure;
Step 406 performs LDD ion implantation;
Step 407 forms the first clearance wall on the sidewall of described grid structure;
Step 408 epitaxial growth first semiconductor material layer is to form lifting source and drain;
Step 409 forms the second clearance wall on described first clearance wall;
Step 410 performs ion implantation, forms source-drain area and anneal in described grid structure both sides;
Step 411 forms silicide layer on described source-drain area, then forms electrical connection.
In addition, the invention provides beyond the described preparation method without junction nanowire FinFET, brightly additionally provide a kind of semiconductor device, comprising:
Semiconductor substrate;
Be arranged in the trap of described Semiconductor substrate;
Be positioned at the fin structure on described trap and be positioned on described fin structure without junction nanowire structure;
Around the grid structure of described fin structure and described nano thread structure;
Wherein, described trap is N trap, and described fin structure is N-type, and described is P type without junction nanowire structure, and source and drain is P type very, and described device is that P type is without junction nanowire FinFET; Or described trap is P trap, described fin structure is P type, and described is N-type without junction nanowire structure, and source and drain is N-type very, and described device is that N-type is without junction nanowire FinFET.
As further preferred, described device also comprises:
Be positioned at the first clearance wall on described grid structure and the second clearance wall;
The shallow trench isolation being positioned at described grid structure both sides from;
Be positioned at the source-drain area of described grid structure both sides;
Be positioned at the electrical connecting element on described grid structure.
In semiconductor device of the present invention and preparation method, the problems such as the high-dopant concentration gradient that transistor has in prior art and low heat budget, will combine without junction nanowire transistor AND gate FinFET and be formed without junction nanowire FinFET in preparation process.Transistor formed according to the present invention, when device is in open mode, there is larger electric current, when device is in off-state, there is less electric current, relative and FinFET performance is greatly improved, relative to planar device, also there is larger on-off ratio (larger on-off ratio), whole technical process and existing technique completely compatible, and the preparation method of this transistor is applicable to undersized Semiconductor substrate, its cost of manufacture is lower than the cost of manufacture of nano wire cylinder all-around-gate without junction field effect transistor (GAAC JLFET), therefore the manufacturing process of this transistor is simpler, reduce process costs simultaneously.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.

Claims (18)

1., without a manufacture method of junction nanowire FinFET, comprising:
Semiconductor substrate is provided;
Form epitaxial loayer on the semiconductor substrate;
Epitaxial loayer described in patterning and the described Semiconductor substrate of part, to form fin structure and to be positioned at the nano thread structure on described fin structure;
Described fin structure and described nano thread structure form grid structure.
2. the method as requested described in 1, is characterized in that, the material of described epitaxial loayer is SiGe or SiC.
3. the method as requested described in 1, is characterized in that, described epitaxy layer thickness is 5-10nm.
4. the method as requested described in 1, is characterized in that, the width of described fin structure is less than 8nm.
5. the method as requested described in 1, is characterized in that, the doping type of described epitaxial loayer is different from the doping type of described fin structure.
6. the method as requested described in 5, is characterized in that, adopts in-situ doped technique or shallow link doping process to form described epitaxial loayer.
7. the method as requested described in 1, is characterized in that, in described Semiconductor substrate, be formed with trap.
8. the method as requested described in 1, is characterized in that, described Semiconductor substrate is Si.
9. the method as requested described in 1, is characterized in that, described grid structure is high-K metal gate electrode structure.
10. the method as requested described in 1, is characterized in that, described method be also included in formed to be formed in the Semiconductor substrate of described fin structure both sides before described grid structure shallow trench isolation from step.
11. methods as requested described in 1, is characterized in that, after the described grid structure of formation, described method is further comprising the steps of:
Perform LDD ion implantation;
The sidewall of described grid structure is formed the first clearance wall;
Epitaxial growth first semiconductor material layer is to form lifting source and drain;
Described first clearance wall forms the second clearance wall;
Perform ion implantation, form source-drain area in described grid structure both sides and carry out short annealing;
Described source-drain area forms silicide layer, then forms electrical connection.
12. methods as requested described in 11, it is characterized in that, described first semiconductor material layer is Si, SiGe or SiC material layer.
13. methods as requested described in 1, it is characterized in that, the method for epitaxial loayer described in patterning and the described Semiconductor substrate of part comprises:
Form patterned photo glue-line on said epitaxial layer there, to define the pattern of described fin structure and described nano thread structure;
With described photoresist layer for epitaxial loayer described in mask etch and the described Semiconductor substrate of part, form described fin structure and be positioned at the described nano thread structure on described fin structure;
Remove described photoresist layer.
14. methods as requested described in 11, it is characterized in that, the doping type of described epitaxial loayer is identical with the doping type of described source-drain area.
15. 1 kinds, without junction nanowire FinFET semiconductor device, comprising:
Semiconductor substrate;
The nano thread structure being positioned at the fin structure in described Semiconductor substrate and being positioned on described fin structure;
Around the grid structure of described fin structure and described nano thread structure.
16. devices according to claim 15, is characterized in that, the material of described nano thread structure is SiGe or SiC.
17. devices according to claim 15, is characterized in that, described grid structure is high-K metal gate electrode structure.
18. devices according to claim 15, is characterized in that, the doping type of described nano thread structure is different from the doping type of described fin structure.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990240A (en) * 2015-03-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US20120025312A1 (en) * 2010-07-30 2012-02-02 Globalfoundries Inc. Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material
CN102610642A (en) * 2011-01-21 2012-07-25 台湾积体电路制造股份有限公司 Non-uniform channel junction-less transistor
CN102916048A (en) * 2012-10-24 2013-02-06 中国科学院半导体研究所 Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor
CN104183488A (en) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 FinFET semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US20120025312A1 (en) * 2010-07-30 2012-02-02 Globalfoundries Inc. Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material
CN102610642A (en) * 2011-01-21 2012-07-25 台湾积体电路制造股份有限公司 Non-uniform channel junction-less transistor
CN102916048A (en) * 2012-10-24 2013-02-06 中国科学院半导体研究所 Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor
CN104183488A (en) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 FinFET semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990240A (en) * 2015-03-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
CN105990240B (en) * 2015-03-04 2019-06-28 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method thereof, electronic device

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