CN105990240A

CN105990240A - Semiconductor device and manufacturing method thereof, and electronic device

Info

Publication number: CN105990240A
Application number: CN201510095432.XA
Authority: CN
Inventors: 周飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Corp
Priority date: 2015-03-04
Filing date: 2015-03-04
Publication date: 2016-10-05
Anticipated expiration: 2035-03-04
Also published as: CN105990240B

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method comprises the steps of: step S1, providing a semiconductor substrate, forming a plurality of fins and virtual gates surrounding the fins on the semiconductor substrate, and forming an inter-layer dielectric layer which fills gaps between the adjacent virtual gates on the semiconductor substrate; step S2, removing the virtual gates to expose the fins; step S3: forming a gate dielectric layer and a covering layer on the fins in sequence; step S4: and carrying out a silicon ion implantation step to form a silicon-containing covering layer. According to the semiconductor device and the manufacturing method thereof, the silicon ion implantation step is carried out on a TiN layer before depositing a work function metal layer so as to form a TiSiN layer, thereby controlling Al diffusion performance of a conductive layer formed in a subsequent step by the covering layer, and solving the problem of multi-threshold voltage (multi-Vt); in addition, the manufacturing method can effectively reduce the ion implantation shadowing effect (IMP shadowing effect).

Description

A kind of semiconductor devices and preparation method thereof, electronic installation

Technical field

The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation thereof Method, electronic installation.

Background technology

With the development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing The size of IC-components realizes with the speed improving it.At present, due to pursue high device close In degree, high-performance and low cost, semi-conductor industry has advanced to nanometer technology process node, semiconductor device The preparation of part is limited by various physics limits.

With constantly reducing of cmos device size, promote three from the challenge manufacturing with design aspect Dimension design is such as the development of FinFET (FinFET).Relative to existing planar transistor, FinFET is the advanced semiconductor device for 20nm and following process node, and it can effective controller Scaled the caused short-channel effect being difficult to overcome of part, can also effectively improve shape on substrate The density of the transistor array becoming, meanwhile, the grid in FinFET is arranged around fin (fin-shaped channel), Therefore can control electrostatic from three faces, the performance in terms of Electrostatic Control is also more prominent.

Current multi-Vt (multi-Vt) is a very big challenge for 3D FINFET, Threshold voltage ion implanting and the ion implanting to workfunction layers may be used for solving multi-Vt (multi-Vt) problem, but threshold voltage ion implanting will reduce mobility and the mismatch of MOS Performance, is faced with ion implanting capture-effect (shadowing simultaneously to the ion implanting of workfunction layers Effect) challenge, in particular for workfunction layers TiAl in nmos device, due to its tool Bigger thickness is had to be further exacerbated by the capture-effect of ion implanting.

In order to improve performance and the yield of semiconductor devices, the preparation method to device is needed to make further Improve, in order to eliminate the problems referred to above.

Content of the invention

Introducing the concept of a series of reduced form in Summary, this will be in detailed description of the invention Part further describes.The Summary of the present invention is not meant to attempt to limit institute The key feature of claimed technical scheme and essential features, more do not mean that attempting determination is wanted Seek the protection domain of the technical scheme of protection.

The present invention, in order to overcome the problem of presently, there are, provides the preparation method of a kind of semiconductor devices, bag Include:

Step S1: Semiconductor substrate is provided, is formed with some fins and ring on the semiconductor substrate It around the dummy gate of described fin, is also formed with on the semiconductor substrate filling adjacent described virtual grid The interlayer dielectric layer in gap between pole；

Step S2: remove described dummy gate, to expose described fin；

Step S3: sequentially form gate dielectric and cover layer on described fin；

Step S4: perform Si ion implantation step, to form siliceous cover layer.

Alternatively, in described step S3, described cover layer includes TiN layer and the TaN being sequentially depositing Layer, performs described Si ion implantation step, to form TiSiN in described TiN layer.

Alternatively, after described step S4, described method also includes:

Step S5: form workfunction layers on described cover layer；

Alternatively, described Semiconductor substrate includes NMOS area and PMOS area, wherein said step S5 includes:

Step S51: deposit PMOS work function in described NMOS area and described PMOS area Metal level；

Step S52: remove the described PMOS workfunction layers in described NMOS area；

Step S53: deposit NMOS workfunction layers in described NMOS area.

Alternatively, described method still further comprises formation barrier layer and metallic aluminium after described step S4 The step of material layer, to form metal gates.

Alternatively, described step S1 includes:

Step S11: Semiconductor substrate is provided and performs ion implanting, to form trap；

Step S12: pattern described Semiconductor substrate, forms described fin；

Step S13: deposition dummy gate dielectric layer and dummy gate material layer simultaneously pattern, to be formed State dummy gate.

Alternatively, described step S1 may further comprise:

Step S14: perform source and drain LDD and inject, and in the described Semiconductor substrate of dummy gate both sides Epitaxial growth of semiconductor material layer, to form lifting source and drain；

Step S15: again perform ion implanting, and carry out rapid thermal annealing；

Step S16: deposit described interlayer dielectric layer and planarize, to fill between described dummy gate Gap.

Alternatively, in described step S3, described fin is sequentially depositing boundary layer and high k dielectric Layer.

Present invention also offers the semiconductor devices that a kind of above-mentioned method prepares.

Present invention also offers a kind of electronic installation, including above-mentioned semiconductor devices.

In the present invention in order to solve problems of the prior art, provide a kind of semiconductor devices and Its preparation method, in the process after removing described dummy gate, deposition height on described fin K dielectric layer, then depositing TiN layer and TaN layer are as cover layer, in the described workfunction layers of deposition Described Si ion implantation step is performed to described TiN layer before, to form TiSiN layer, cover for control Cap rock, for the diffusion of the conductive layer Al being formed in subsequent step, will solve multi-Vt simultaneously (multi-Vt) problem, additionally, described method can also be effectively reduced ion implanting screen effect (IMP shadowing effect)。

Brief description

The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Accompanying drawing shows Go out embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,

Fig. 1 is the preparation process schematic diagram of semiconductor devices described in prior art；

Fig. 2 is the preparation process schematic diagram of heretofore described semiconductor devices；

Fig. 3 is the process chart preparing semiconductor devices of the present invention.

Detailed description of the invention

In the following description, a large amount of concrete details is given to provide to the present invention more thoroughly Understand.It is, however, obvious to a person skilled in the art that the present invention can be not necessarily to one Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention, Some technical characteristics well known in the art are not described.

It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to this In propose embodiment.On the contrary, it is open thorough and complete to provide these embodiments to make, and incite somebody to action this The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.

It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling Conjunction is arrived " other elements or during layer, its can directly on other elements or layer, adjacent thereto, connect Or be coupled to other elements or layer, or can there is element between two parties or layer.On the contrary, when element is claimed For " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan When part or layer, then there is not element between two parties or layer.Although it should be understood that and can using term the firstth, 2nd, the third various element, parts, district, floor and/or part of describing, these elements, parts, district, Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, parts, District, floor or part and another element, parts, district, floor or part.Therefore, without departing from the present invention Under teaching, the first element discussed below, parts, district, floor or part be represented by the second element, Parts, district, floor or part.

Spatial relationship term for example " ... under ", " ... below ", " following ", " ... under ", " ... on ", " above " etc., here can describe for convenience and be used thus in description figure A shown element or the relation of feature and other elements or feature.It should be understood that except shown in figure Orientation beyond, spatial relationship term is intended to also include the different orientation of device in using and operating.Example As if the device upset in accompanying drawing, then, being described as " below other elements " or " its it Under " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, example Property term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally take Correspondingly explained to (90-degree rotation or other orientations) and spatial description language as used herein.

The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention System.When using at this, " one " of singulative, " one " and " described/should " be also intended to include plural number Form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ", When using in this specification, determine described feature, integer, step, operation, element and/or parts Existence, but be not excluded for one or more other feature, integer, step, operation, element, parts And/or group existence or interpolation.When using at this, term "and/or" includes any of related Listed Items And all combinations.

The preparation method of semiconductor devices described in prior art as it is shown in figure 1, first provide substrate 101, Substrate forms hard mask layer；Then, pattern described hard mask layer, formed be used for etching substrate with It is formed on multiple masks being isolated from each other of fin；Then, substrate is etched multiple to be formed on Fin 103；Then, deposition forms the isolation structure between multiple fin；Finally, etching removal is described firmly Mask layer.

Then on described fin, dummy gate, and dielectric layer (not shown) are formed, to cover Described dummy gate, then removes described dummy gate, exposes described fin, and depends on described fin Secondary interlevel dielectric deposition the 104th, high k dielectric layer the 105th, cover layer the 106th, 107 and workfunction metal Layer 108, then performs ion implanting, owing to workfunction layers 108 has bigger thickness, and Ion implanting gap between described fin is very little, owing to ion implanting screen effect is for workfunction metal The ion implanting of layer sidewall is a very big challenge.

Embodiment 1

Below in conjunction with Fig. 2, semiconductor devices of the present invention and preparation method are described further.

Step 201, provides Semiconductor substrate 201 and performs ion implanting, to form trap.

Described Semiconductor substrate 201 can be at least in the following material being previously mentioned in this step Kind: stacking germanium in stacking silicon (SSOI) on silicon, silicon-on-insulator (SOI), insulator, insulator SiClx (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) Deng.

Wherein said Semiconductor substrate includes NMOS area and PMOS area, with in follow-up step Form nmos device and PMOS device in rapid.

Then in described Semiconductor substrate 201, form pad oxide skin(coating) (Pad oxide), wherein said pad The forming method of oxide skin(coating) (Pad oxide) can be formed by the method for deposition, such as chemical gaseous phase The methods such as deposition, ald, can also be formed by the surface of Semiconductor substrate described in thermal oxide, Do not repeat them here.

Further, the step performing ion implanting can also be comprised in this step further, with described Forming trap in Semiconductor substrate, the ionic species wherein injecting and method for implanting can be normal in this area Method, do not repeat one by one at this.

Then step 202, form multiple fin 203, the width of fin in Semiconductor substrate 201 All identical, or fin is divided into multiple fins group with different in width.

Concrete forming method includes: form hard mask layer (not shown) in Semiconductor substrate 201, Form the various suitable technique that described hard mask layer can use those skilled in the art to be familiar with, for example Chemical vapor deposition method, described hard mask layer can be the oxide skin(coating) and silicon nitride being laminated from bottom to top Layer；Pattern described hard mask layer, formed and be used for etching Semiconductor substrate 201 to be formed on fin Multiple masks being isolated from each other, in one embodiment, use self-aligned double patterning case (SADP) technique Implement described patterning process；Etching Semiconductor substrate 201 is to be formed on fin structure.

Step 203, depositing isolation material layer 202, to cover described fin structure.

Specifically, as in figure 2 it is shown, depositing isolation material layer 202, to be filled up completely with between fin structure Gap.In one embodiment, the chemical vapor deposition method with flowable is used to implement described Deposition.The material of spacer material layer 202 can be with selective oxidation thing, such as HARP.

Then spacer material layer 202 described in etch-back, to the object height of described fin.

Specifically, as in figure 2 it is shown, spacer material layer 102 described in etch-back, with fin described in exposed portion Piece, and then form the fin with certain height.As example, implement high annealing, so that isolation material The bed of material 102 is densified, and the temperature of described high annealing can be 700 DEG C-1000 DEG C；Perform chemical machinery Grind, until exposing the top of described hard mask layer；Remove the silicon nitride layer in described hard mask layer, In one embodiment, using wet etching to remove silicon nitride layer, the corrosive liquid of described wet etching is dilution Hydrofluoric acid；Remove the oxide skin(coating) in described hard mask layer and part spacer material layer 102, to expose The part of fin structure, and then form the fin structure with certain height, in one embodiment, adopt Implementing this removal with SiCoNi etching, the etching gas of described SiCoNi etching mainly has NH₃And NF₃。

Step 204, forms dummy gate, to cover described fin on described spacer material layer.

Specifically, as in figure 2 it is shown, deposit dummy gate material layer, described dummy gate in this step Material layer can select semi-conducting material commonly used in the art, for example, can select polysilicon etc., not office It is limited to a certain kind, will not enumerate at this,

The deposition process of described gate material layers can select the sides such as chemical gaseous phase deposition or ald Method.

Then described gate material layers is patterned, to form the dummy gate around described fin.

Pattern described dummy gate material layer in this step, to be formed around dummy gate, specifically, Described dummy gate material layer forms photoresist layer, then exposure imaging, to form opening, then Dummy gate material layer described in described photoresist layer as mask etch, to form around dummy gate.

Alternatively, dummy gate can also be formed between described fin and described dummy gate further be situated between Electric layer.

Step 205, performs source and drain LDD and injects, and in the both sides epitaxial growth of described dummy gate Semiconductor material layer, to form lifting source and drain.

Specifically, the method that ability can be used in this step conventional performs source and drain LDD and injects, at this Repeat no more.

Then in the both sides epitaxial growth SiC layer of described dummy gate in NMOS area, lift to be formed Rise SiC source-drain electrode.Selective epitaxial growth (SEG) is used to form described SiC layer, specifically in the present invention Ground, selects silicon-containing gas as unstrpped gas, selects gas containing C as doping, under the conveying of carrier gas Enter reative cell, and then extension obtains described SiC layer.Alternatively, SiC layer described in epitaxial growth is same When can carry out adulterating (in-situ doped) in situ, can be with Doping Phosphorus or arsenic etc., such as extension same When be passed through phosphorous or arsenic gas.

Same, at the both sides epitaxial growth SiGe of described dummy gate in described PMOS area, with Form the lifting source and drain of PMOS.

Step 206, again performs ion implanting step and carries out rapid thermal annealing.

The degree of depth and the horizontal proliferation of impurity can be suppressed again in the present invention in order to demonstrate,prove activator impurity, performed institute Carrying out rapid thermal annealing after stating ion implanting, alternatively, described rapid thermal annealing temperature is 1000-1050 ℃。

Step 207, deposits described interlayer dielectric layer and planarizes, with fill described dummy gate it Between gap.

Specifically, interlevel dielectric deposition planarizing, planarizes described to interlayer dielectric layer to described void Intend the top of grid.The non-limiting examples that described planarization is processed includes mechanical planarization method and chemistry Mechanical polishing flattening method.

Step 208, removes described dummy gate.

Specifically, remove described dummy gate, form groove.The method of described removal can be photoetching and Etching.Gas used in etching process includes HBr, and it is as main etch gas；Also include making For etching the 02 or Ar of make-up gas, it can improve the quality of etching.

Step 209, deposits gate interface layer the 204th, high k dielectric layer 205.

Specifically, wherein, the material of described high k dielectric layer 205 includes hafnium oxide, hafnium silicon oxide, nitrogen Hafnium silicon oxide, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, oxygen Change barium titanium, strontium oxide strontia titanium, aluminum oxide etc., particularly preferably hafnium oxide, zirconium oxide or aluminum oxide.

It should be noted that can also form boundary layer 204 in the lower section of high k dielectric layer, it constitutes material Material includes Si oxide (SiOx), and the effect forming boundary layer is to improve high k dielectric layer and Semiconductor substrate Between interfacial characteristics.

Step 210, depositing TiN layer 206 and TaN layer 207 on described high k dielectric layer, make For cover layer, and in described TiN layer 206, perform described Si ion implantation step, to form TiSiN Layer.

Specifically, forming cover layer on described high k dielectric layer, its constituent material includes titanium nitride and nitrogen Changing tantalum, the effect forming cover layer is to prevent the metal material Al in metal gate structure to high k dielectric layer Diffusion, to regulate the threshold voltage of described semiconductor devices.

In order to improve the regulation performance to threshold voltage, in described TiN layer 206, perform described silicon ion Implantation step, to form TiSiN layer, in the present invention formed perform before workfunction layers silicon from Son injects, to increase the gap of ion implanting so that the ion implanting of described cover layer is more prone to, Avoid ion implanting screen effect, further increase threshold voltage performance.

Step 211, forms workfunction layers, barrier layer and metal aluminium on described cover layer The bed of material, to form metal gates.

Specifically, PMOS workfunction layers, such as TiN are first deposited in this step；Then go Except the described PMOS workfunction layers in NMOS area, then in described NMOS area deposition NMOS workfunction layers, such as TiAl etc..

So far, the introduction of the preparation process of the semiconductor devices of the embodiment of the present invention is completed.In above-mentioned step After Zhou, can also include other correlation step, here is omitted.Further, except above-mentioned steps it Outward, the preparation method of the present embodiment can also be among each step above-mentioned or include between different steps Other steps, these steps all can be realized by various techniques of the prior art, no longer superfluous herein State.

Fig. 3 is the present invention one specifically figure of semiconductor devices preparation flow described in embodiment, specifically Including:

Step S2: remove described dummy gate, to expose described fin；

Step S3: sequentially form gate dielectric and cover layer on described fin；

Step S4: perform Si ion implantation step, to form siliceous cover layer.

Embodiment 2

Present invention also offers a kind of semiconductor devices, described semiconductor devices is selected described in embodiment 1 Prepared by method.Hold in described semiconductor devices is before the described workfunction layers of deposition to described TiN The described Si ion implantation step of row, to form TiSiN, therefore can well control cover layer conductive layer The diffusion of Al, the problem that simultaneously will solve multi-Vt (multi-Vt), can also effectively release Put ion implanting screen effect.

Embodiment 3

Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment 2.Wherein, Semiconductor devices is the semiconductor devices described in embodiment 2, or the preparation method according to embodiment 1 The semiconductor devices obtaining.

The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, Game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, MP3, Any electronic product such as MP4, PSP or equipment, it is possible to be any centre including described semiconductor devices Product.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor devices, thus has Better performance.

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment It is only intended to citing and descriptive purpose, and be not intended to limit the invention to described scope of embodiments In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc. Effect scope is defined.

Claims

1. the preparation method of a semiconductor devices, comprising:

Step S1: Semiconductor substrate is provided, is formed with some fins and the dummy gate around described fin on the semiconductor substrate, is also formed with filling the interlayer dielectric layer in gap between adjacent described dummy gate on the semiconductor substrate；

Step S2: remove described dummy gate, to expose described fin；

Step S3: sequentially form gate dielectric and cover layer on described fin；

Step S4: perform Si ion implantation step, to form siliceous cover layer.

2. method according to claim 1, it is characterised in that in described step S3, described cover layer includes TiN layer and the TaN layer being sequentially depositing, performs described Si ion implantation step, to form TiSiN in described TiN layer.

3. method according to claim 1, it is characterised in that described method also includes after described step S4:

Step S5: form workfunction layers on described cover layer.

4. method according to claim 3, it is characterised in that described Semiconductor substrate includes NMOS area and PMOS area, wherein said step S5 includes:

Step S51: deposit PMOS workfunction layers in described NMOS area and described PMOS area；

Step S53: deposit NMOS workfunction layers in described NMOS area.

5. method according to claim 3, it is characterised in that described method still further comprises the step forming barrier layer and metallic aluminum material layer after described step S4, to form metal gates.

6. method according to claim 1, it is characterised in that described step S1 includes:

Step S12: pattern described Semiconductor substrate, forms described fin；

Step S13: deposition dummy gate dielectric layer and dummy gate material layer simultaneously pattern, to form described dummy gate.

7. method according to claim 6, it is characterised in that described step S1 may further comprise:

Step S14: perform source and drain LDD and inject, and at the described Semiconductor substrate Epitaxial growth semiconductor material layer of dummy gate both sides, to form lifting source and drain；

Step S16: deposit described interlayer dielectric layer and planarize, to fill the gap between described dummy gate.

8. method according to claim 1, it is characterised in that in described step S3, is sequentially depositing boundary layer and high k dielectric layer on described fin.

9. the semiconductor devices that the method described in one of claim 1 to 8 prepares.

10. an electronic installation, including the semiconductor devices described in claim 9.